| blob | e960b09ff01cd91a60df32aebafb81387bbc7286 |
1 /*
2 * Device Tree Source for UniPhier Pro4 SoC
3 *
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6 *
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
10 * whole.
11 *
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * Or, alternatively,
23 *
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
31 * conditions:
32 *
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
35 *
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
44 */
46 /include/ "skeleton.dtsi"
48 / {
49 compatible = "socionext,uniphier-pro4";
51 cpus {
52 #address-cells = <1>;
53 #size-cells = <0>;
55 cpu@0 {
56 device_type = "cpu";
57 compatible = "arm,cortex-a9";
58 reg = <0>;
59 enable-method = "psci";
60 next-level-cache = <&l2>;
61 };
63 cpu@1 {
64 device_type = "cpu";
65 compatible = "arm,cortex-a9";
66 reg = <1>;
67 enable-method = "psci";
68 next-level-cache = <&l2>;
69 };
70 };
72 psci {
73 compatible = "arm,psci-0.2";
74 method = "smc";
75 };
77 clocks {
78 refclk: ref {
79 compatible = "fixed-clock";
80 #clock-cells = <0>;
81 clock-frequency = <25000000>;
82 };
84 arm_timer_clk: arm_timer_clk {
85 #clock-cells = <0>;
86 compatible = "fixed-clock";
87 clock-frequency = <50000000>;
88 };
89 };
91 soc {
92 compatible = "simple-bus";
93 #address-cells = <1>;
94 #size-cells = <1>;
95 ranges;
96 interrupt-parent = <&intc>;
98 l2: l2-cache@500c0000 {
99 compatible = "socionext,uniphier-system-cache";
100 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
101 <0x506c0000 0x400>;
102 interrupts = <0 174 4>, <0 175 4>;
103 cache-unified;
104 cache-size = <(768 * 1024)>;
105 cache-sets = <256>;
106 cache-line-size = <128>;
107 cache-level = <2>;
108 };
110 serial0: serial@54006800 {
111 compatible = "socionext,uniphier-uart";
112 status = "disabled";
113 reg = <0x54006800 0x40>;
114 interrupts = <0 33 4>;
115 pinctrl-names = "default";
116 pinctrl-0 = <&pinctrl_uart0>;
117 clocks = <&peri_clk 0>;
118 };
120 serial1: serial@54006900 {
121 compatible = "socionext,uniphier-uart";
122 status = "disabled";
123 reg = <0x54006900 0x40>;
124 interrupts = <0 35 4>;
125 pinctrl-names = "default";
126 pinctrl-0 = <&pinctrl_uart1>;
127 clocks = <&peri_clk 1>;
128 };
130 serial2: serial@54006a00 {
131 compatible = "socionext,uniphier-uart";
132 status = "disabled";
133 reg = <0x54006a00 0x40>;
134 interrupts = <0 37 4>;
135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_uart2>;
137 clocks = <&peri_clk 2>;
138 };
140 serial3: serial@54006b00 {
141 compatible = "socionext,uniphier-uart";
142 status = "disabled";
143 reg = <0x54006b00 0x40>;
144 interrupts = <0 177 4>;
145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_uart3>;
147 clocks = <&peri_clk 3>;
148 };
150 i2c0: i2c@58780000 {
151 compatible = "socionext,uniphier-fi2c";
152 status = "disabled";
153 reg = <0x58780000 0x80>;
154 #address-cells = <1>;
155 #size-cells = <0>;
156 interrupts = <0 41 4>;
157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_i2c0>;
159 clocks = <&peri_clk 4>;
160 clock-frequency = <100000>;
161 };
163 i2c1: i2c@58781000 {
164 compatible = "socionext,uniphier-fi2c";
165 status = "disabled";
166 reg = <0x58781000 0x80>;
167 #address-cells = <1>;
168 #size-cells = <0>;
169 interrupts = <0 42 4>;
170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_i2c1>;
172 clocks = <&peri_clk 5>;
173 clock-frequency = <100000>;
174 };
176 i2c2: i2c@58782000 {
177 compatible = "socionext,uniphier-fi2c";
178 status = "disabled";
179 reg = <0x58782000 0x80>;
180 #address-cells = <1>;
181 #size-cells = <0>;
182 interrupts = <0 43 4>;
183 pinctrl-names = "default";
184 pinctrl-0 = <&pinctrl_i2c2>;
185 clocks = <&peri_clk 6>;
186 clock-frequency = <100000>;
187 };
189 i2c3: i2c@58783000 {
190 compatible = "socionext,uniphier-fi2c";
191 status = "disabled";
192 reg = <0x58783000 0x80>;
193 #address-cells = <1>;
194 #size-cells = <0>;
195 interrupts = <0 44 4>;
196 pinctrl-names = "default";
197 pinctrl-0 = <&pinctrl_i2c3>;
198 clocks = <&peri_clk 7>;
199 clock-frequency = <100000>;
200 };
202 /* i2c4 does not exist */
204 /* chip-internal connection for DMD */
205 i2c5: i2c@58785000 {
206 compatible = "socionext,uniphier-fi2c";
207 reg = <0x58785000 0x80>;
208 #address-cells = <1>;
209 #size-cells = <0>;
210 interrupts = <0 25 4>;
211 clocks = <&peri_clk 9>;
212 clock-frequency = <400000>;
213 };
215 /* chip-internal connection for HDMI */
216 i2c6: i2c@58786000 {
217 compatible = "socionext,uniphier-fi2c";
218 reg = <0x58786000 0x80>;
219 #address-cells = <1>;
220 #size-cells = <0>;
221 interrupts = <0 26 4>;
222 clocks = <&peri_clk 10>;
223 clock-frequency = <400000>;
224 };
226 system_bus: system-bus@58c00000 {
227 compatible = "socionext,uniphier-system-bus";
228 status = "disabled";
229 reg = <0x58c00000 0x400>;
230 #address-cells = <2>;
231 #size-cells = <1>;
232 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_system_bus>;
234 };
236 smpctrl@59800000 {
237 compatible = "socionext,uniphier-smpctrl";
238 reg = <0x59801000 0x400>;
239 };
241 mioctrl@59810000 {
242 compatible = "socionext,uniphier-pro4-mioctrl",
243 "simple-mfd", "syscon";
244 reg = <0x59810000 0x800>;
246 mio_clk: clock {
247 compatible = "socionext,uniphier-pro4-mio-clock";
248 #clock-cells = <1>;
249 };
251 mio_rst: reset {
252 compatible = "socionext,uniphier-pro4-mio-reset";
253 #reset-cells = <1>;
254 };
255 };
257 perictrl@59820000 {
258 compatible = "socionext,uniphier-pro4-perictrl",
259 "simple-mfd", "syscon";
260 reg = <0x59820000 0x200>;
262 peri_clk: clock {
263 compatible = "socionext,uniphier-pro4-peri-clock";
264 #clock-cells = <1>;
265 };
267 peri_rst: reset {
268 compatible = "socionext,uniphier-pro4-peri-reset";
269 #reset-cells = <1>;
270 };
271 };
273 usb2: usb@5a800100 {
274 compatible = "socionext,uniphier-ehci", "generic-ehci";
275 status = "disabled";
276 reg = <0x5a800100 0x100>;
277 interrupts = <0 80 4>;
278 pinctrl-names = "default";
279 pinctrl-0 = <&pinctrl_usb2>;
280 clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
281 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
282 <&mio_rst 12>;
283 };
285 usb3: usb@5a810100 {
286 compatible = "socionext,uniphier-ehci", "generic-ehci";
287 status = "disabled";
288 reg = <0x5a810100 0x100>;
289 interrupts = <0 81 4>;
290 pinctrl-names = "default";
291 pinctrl-0 = <&pinctrl_usb3>;
292 clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
293 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
294 <&mio_rst 13>;
295 };
297 soc-glue@5f800000 {
298 compatible = "socionext,uniphier-pro4-soc-glue",
299 "simple-mfd", "syscon";
300 reg = <0x5f800000 0x2000>;
302 pinctrl: pinctrl {
303 compatible = "socionext,uniphier-pro4-pinctrl";
304 };
305 };
307 timer@60000200 {
308 compatible = "arm,cortex-a9-global-timer";
309 reg = <0x60000200 0x20>;
310 interrupts = <1 11 0x304>;
311 clocks = <&arm_timer_clk>;
312 };
314 timer@60000600 {
315 compatible = "arm,cortex-a9-twd-timer";
316 reg = <0x60000600 0x20>;
317 interrupts = <1 13 0x304>;
318 clocks = <&arm_timer_clk>;
319 };
321 intc: interrupt-controller@60001000 {
322 compatible = "arm,cortex-a9-gic";
323 reg = <0x60001000 0x1000>,
324 <0x60000100 0x100>;
325 #interrupt-cells = <3>;
326 interrupt-controller;
327 };
329 sysctrl@61840000 {
330 compatible = "socionext,uniphier-pro4-sysctrl",
331 "simple-mfd", "syscon";
332 reg = <0x61840000 0x10000>;
334 sys_clk: clock {
335 compatible = "socionext,uniphier-pro4-clock";
336 #clock-cells = <1>;
337 };
339 sys_rst: reset {
340 compatible = "socionext,uniphier-pro4-reset";
341 #reset-cells = <1>;
342 };
343 };
344 };
345 };
347 /include/ "uniphier-pinctrl.dtsi"