2 * Performance event support - powerpc architecture code
4 * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
11 #include <linux/kernel.h>
12 #include <linux/sched.h>
13 #include <linux/perf_event.h>
14 #include <linux/percpu.h>
15 #include <linux/hardirq.h>
16 #include <linux/uaccess.h>
19 #include <asm/machdep.h>
20 #include <asm/firmware.h>
21 #include <asm/ptrace.h>
22 #include <asm/code-patching.h>
24 #define BHRB_MAX_ENTRIES 32
25 #define BHRB_TARGET 0x0000000000000002
26 #define BHRB_PREDICTION 0x0000000000000001
27 #define BHRB_EA 0xFFFFFFFFFFFFFFFCUL
29 struct cpu_hw_events
{
36 struct perf_event
*event
[MAX_HWEVENTS
];
37 u64 events
[MAX_HWEVENTS
];
38 unsigned int flags
[MAX_HWEVENTS
];
40 * The order of the MMCR array is:
41 * - 64-bit, MMCR0, MMCR1, MMCRA, MMCR2
42 * - 32-bit, MMCR0, MMCR1, MMCR2
44 unsigned long mmcr
[4];
45 struct perf_event
*limited_counter
[MAX_LIMITED_HWCOUNTERS
];
46 u8 limited_hwidx
[MAX_LIMITED_HWCOUNTERS
];
47 u64 alternatives
[MAX_HWEVENTS
][MAX_EVENT_ALTERNATIVES
];
48 unsigned long amasks
[MAX_HWEVENTS
][MAX_EVENT_ALTERNATIVES
];
49 unsigned long avalues
[MAX_HWEVENTS
][MAX_EVENT_ALTERNATIVES
];
51 unsigned int txn_flags
;
55 u64 bhrb_filter
; /* BHRB HW branch filter */
56 unsigned int bhrb_users
;
58 struct perf_branch_stack bhrb_stack
;
59 struct perf_branch_entry bhrb_entries
[BHRB_MAX_ENTRIES
];
63 static DEFINE_PER_CPU(struct cpu_hw_events
, cpu_hw_events
);
65 static struct power_pmu
*ppmu
;
68 * Normally, to ignore kernel events we set the FCS (freeze counters
69 * in supervisor mode) bit in MMCR0, but if the kernel runs with the
70 * hypervisor bit set in the MSR, or if we are running on a processor
71 * where the hypervisor bit is forced to 1 (as on Apple G5 processors),
72 * then we need to use the FCHV bit to ignore kernel events.
74 static unsigned int freeze_events_kernel
= MMCR0_FCS
;
77 * 32-bit doesn't have MMCRA but does have an MMCR2,
78 * and a few other names are different.
83 #define MMCR0_PMCjCE MMCR0_PMCnCE
89 #define MMCR0_PMCC_U6 0
91 #define SPRN_MMCRA SPRN_MMCR2
92 #define MMCRA_SAMPLE_ENABLE 0
94 static inline unsigned long perf_ip_adjust(struct pt_regs
*regs
)
98 static inline void perf_get_data_addr(struct pt_regs
*regs
, u64
*addrp
) { }
99 static inline u32
perf_get_misc_flags(struct pt_regs
*regs
)
103 static inline void perf_read_regs(struct pt_regs
*regs
)
107 static inline int perf_intr_is_nmi(struct pt_regs
*regs
)
112 static inline int siar_valid(struct pt_regs
*regs
)
117 static bool is_ebb_event(struct perf_event
*event
) { return false; }
118 static int ebb_event_check(struct perf_event
*event
) { return 0; }
119 static void ebb_event_add(struct perf_event
*event
) { }
120 static void ebb_switch_out(unsigned long mmcr0
) { }
121 static unsigned long ebb_switch_in(bool ebb
, struct cpu_hw_events
*cpuhw
)
123 return cpuhw
->mmcr
[0];
126 static inline void power_pmu_bhrb_enable(struct perf_event
*event
) {}
127 static inline void power_pmu_bhrb_disable(struct perf_event
*event
) {}
128 static void power_pmu_sched_task(struct perf_event_context
*ctx
, bool sched_in
) {}
129 static inline void power_pmu_bhrb_read(struct cpu_hw_events
*cpuhw
) {}
130 static void pmao_restore_workaround(bool ebb
) { }
131 static bool use_ic(u64 event
)
135 #endif /* CONFIG_PPC32 */
137 static bool regs_use_siar(struct pt_regs
*regs
)
140 * When we take a performance monitor exception the regs are setup
141 * using perf_read_regs() which overloads some fields, in particular
142 * regs->result to tell us whether to use SIAR.
144 * However if the regs are from another exception, eg. a syscall, then
145 * they have not been setup using perf_read_regs() and so regs->result
146 * is something random.
148 return ((TRAP(regs
) == 0xf00) && regs
->result
);
152 * Things that are specific to 64-bit implementations.
156 static inline unsigned long perf_ip_adjust(struct pt_regs
*regs
)
158 unsigned long mmcra
= regs
->dsisr
;
160 if ((ppmu
->flags
& PPMU_HAS_SSLOT
) && (mmcra
& MMCRA_SAMPLE_ENABLE
)) {
161 unsigned long slot
= (mmcra
& MMCRA_SLOT
) >> MMCRA_SLOT_SHIFT
;
163 return 4 * (slot
- 1);
170 * The user wants a data address recorded.
171 * If we're not doing instruction sampling, give them the SDAR
172 * (sampled data address). If we are doing instruction sampling, then
173 * only give them the SDAR if it corresponds to the instruction
174 * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC, the
175 * [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA, or the SDAR_VALID bit in SIER.
177 static inline void perf_get_data_addr(struct pt_regs
*regs
, u64
*addrp
)
179 unsigned long mmcra
= regs
->dsisr
;
182 if (ppmu
->flags
& PPMU_HAS_SIER
)
183 sdar_valid
= regs
->dar
& SIER_SDAR_VALID
;
185 unsigned long sdsync
;
187 if (ppmu
->flags
& PPMU_SIAR_VALID
)
188 sdsync
= POWER7P_MMCRA_SDAR_VALID
;
189 else if (ppmu
->flags
& PPMU_ALT_SIPR
)
190 sdsync
= POWER6_MMCRA_SDSYNC
;
191 else if (ppmu
->flags
& PPMU_NO_SIAR
)
192 sdsync
= MMCRA_SAMPLE_ENABLE
;
194 sdsync
= MMCRA_SDSYNC
;
196 sdar_valid
= mmcra
& sdsync
;
199 if (!(mmcra
& MMCRA_SAMPLE_ENABLE
) || sdar_valid
)
200 *addrp
= mfspr(SPRN_SDAR
);
203 static bool regs_sihv(struct pt_regs
*regs
)
205 unsigned long sihv
= MMCRA_SIHV
;
207 if (ppmu
->flags
& PPMU_HAS_SIER
)
208 return !!(regs
->dar
& SIER_SIHV
);
210 if (ppmu
->flags
& PPMU_ALT_SIPR
)
211 sihv
= POWER6_MMCRA_SIHV
;
213 return !!(regs
->dsisr
& sihv
);
216 static bool regs_sipr(struct pt_regs
*regs
)
218 unsigned long sipr
= MMCRA_SIPR
;
220 if (ppmu
->flags
& PPMU_HAS_SIER
)
221 return !!(regs
->dar
& SIER_SIPR
);
223 if (ppmu
->flags
& PPMU_ALT_SIPR
)
224 sipr
= POWER6_MMCRA_SIPR
;
226 return !!(regs
->dsisr
& sipr
);
229 static inline u32
perf_flags_from_msr(struct pt_regs
*regs
)
231 if (regs
->msr
& MSR_PR
)
232 return PERF_RECORD_MISC_USER
;
233 if ((regs
->msr
& MSR_HV
) && freeze_events_kernel
!= MMCR0_FCHV
)
234 return PERF_RECORD_MISC_HYPERVISOR
;
235 return PERF_RECORD_MISC_KERNEL
;
238 static inline u32
perf_get_misc_flags(struct pt_regs
*regs
)
240 bool use_siar
= regs_use_siar(regs
);
243 return perf_flags_from_msr(regs
);
246 * If we don't have flags in MMCRA, rather than using
247 * the MSR, we intuit the flags from the address in
248 * SIAR which should give slightly more reliable
251 if (ppmu
->flags
& PPMU_NO_SIPR
) {
252 unsigned long siar
= mfspr(SPRN_SIAR
);
253 if (is_kernel_addr(siar
))
254 return PERF_RECORD_MISC_KERNEL
;
255 return PERF_RECORD_MISC_USER
;
258 /* PR has priority over HV, so order below is important */
260 return PERF_RECORD_MISC_USER
;
262 if (regs_sihv(regs
) && (freeze_events_kernel
!= MMCR0_FCHV
))
263 return PERF_RECORD_MISC_HYPERVISOR
;
265 return PERF_RECORD_MISC_KERNEL
;
269 * Overload regs->dsisr to store MMCRA so we only need to read it once
271 * Overload regs->dar to store SIER if we have it.
272 * Overload regs->result to specify whether we should use the MSR (result
273 * is zero) or the SIAR (result is non zero).
275 static inline void perf_read_regs(struct pt_regs
*regs
)
277 unsigned long mmcra
= mfspr(SPRN_MMCRA
);
278 int marked
= mmcra
& MMCRA_SAMPLE_ENABLE
;
283 if (ppmu
->flags
& PPMU_HAS_SIER
)
284 regs
->dar
= mfspr(SPRN_SIER
);
287 * If this isn't a PMU exception (eg a software event) the SIAR is
288 * not valid. Use pt_regs.
290 * If it is a marked event use the SIAR.
292 * If the PMU doesn't update the SIAR for non marked events use
295 * If the PMU has HV/PR flags then check to see if they
296 * place the exception in userspace. If so, use pt_regs. In
297 * continuous sampling mode the SIAR and the PMU exception are
298 * not synchronised, so they may be many instructions apart.
299 * This can result in confusing backtraces. We still want
300 * hypervisor samples as well as samples in the kernel with
301 * interrupts off hence the userspace check.
303 if (TRAP(regs
) != 0xf00)
305 else if ((ppmu
->flags
& PPMU_NO_SIAR
))
309 else if ((ppmu
->flags
& PPMU_NO_CONT_SAMPLING
))
311 else if (!(ppmu
->flags
& PPMU_NO_SIPR
) && regs_sipr(regs
))
316 regs
->result
= use_siar
;
320 * If interrupts were soft-disabled when a PMU interrupt occurs, treat
323 static inline int perf_intr_is_nmi(struct pt_regs
*regs
)
329 * On processors like P7+ that have the SIAR-Valid bit, marked instructions
330 * must be sampled only if the SIAR-valid bit is set.
332 * For unmarked instructions and for processors that don't have the SIAR-Valid
333 * bit, assume that SIAR is valid.
335 static inline int siar_valid(struct pt_regs
*regs
)
337 unsigned long mmcra
= regs
->dsisr
;
338 int marked
= mmcra
& MMCRA_SAMPLE_ENABLE
;
341 if (ppmu
->flags
& PPMU_HAS_SIER
)
342 return regs
->dar
& SIER_SIAR_VALID
;
344 if (ppmu
->flags
& PPMU_SIAR_VALID
)
345 return mmcra
& POWER7P_MMCRA_SIAR_VALID
;
352 /* Reset all possible BHRB entries */
353 static void power_pmu_bhrb_reset(void)
355 asm volatile(PPC_CLRBHRB
);
358 static void power_pmu_bhrb_enable(struct perf_event
*event
)
360 struct cpu_hw_events
*cpuhw
= this_cpu_ptr(&cpu_hw_events
);
365 /* Clear BHRB if we changed task context to avoid data leaks */
366 if (event
->ctx
->task
&& cpuhw
->bhrb_context
!= event
->ctx
) {
367 power_pmu_bhrb_reset();
368 cpuhw
->bhrb_context
= event
->ctx
;
371 perf_sched_cb_inc(event
->ctx
->pmu
);
374 static void power_pmu_bhrb_disable(struct perf_event
*event
)
376 struct cpu_hw_events
*cpuhw
= this_cpu_ptr(&cpu_hw_events
);
381 WARN_ON_ONCE(!cpuhw
->bhrb_users
);
383 perf_sched_cb_dec(event
->ctx
->pmu
);
385 if (!cpuhw
->disabled
&& !cpuhw
->bhrb_users
) {
386 /* BHRB cannot be turned off when other
387 * events are active on the PMU.
390 /* avoid stale pointer */
391 cpuhw
->bhrb_context
= NULL
;
395 /* Called from ctxsw to prevent one process's branch entries to
396 * mingle with the other process's entries during context switch.
398 static void power_pmu_sched_task(struct perf_event_context
*ctx
, bool sched_in
)
404 power_pmu_bhrb_reset();
406 /* Calculate the to address for a branch */
407 static __u64
power_pmu_bhrb_to(u64 addr
)
413 if (is_kernel_addr(addr
))
414 return branch_target((unsigned int *)addr
);
416 /* Userspace: need copy instruction here then translate it */
418 ret
= __get_user_inatomic(instr
, (unsigned int __user
*)addr
);
425 target
= branch_target(&instr
);
426 if ((!target
) || (instr
& BRANCH_ABSOLUTE
))
429 /* Translate relative branch target from kernel to user address */
430 return target
- (unsigned long)&instr
+ addr
;
433 /* Processing BHRB entries */
434 static void power_pmu_bhrb_read(struct cpu_hw_events
*cpuhw
)
438 int r_index
, u_index
, pred
;
442 while (r_index
< ppmu
->bhrb_nr
) {
443 /* Assembly read function */
444 val
= read_bhrb(r_index
++);
446 /* Terminal marker: End of valid BHRB entries */
449 addr
= val
& BHRB_EA
;
450 pred
= val
& BHRB_PREDICTION
;
456 /* Branches are read most recent first (ie. mfbhrb 0 is
457 * the most recent branch).
458 * There are two types of valid entries:
459 * 1) a target entry which is the to address of a
460 * computed goto like a blr,bctr,btar. The next
461 * entry read from the bhrb will be branch
462 * corresponding to this target (ie. the actual
463 * blr/bctr/btar instruction).
464 * 2) a from address which is an actual branch. If a
465 * target entry proceeds this, then this is the
466 * matching branch for that target. If this is not
467 * following a target entry, then this is a branch
468 * where the target is given as an immediate field
469 * in the instruction (ie. an i or b form branch).
470 * In this case we need to read the instruction from
471 * memory to determine the target/to address.
474 if (val
& BHRB_TARGET
) {
475 /* Target branches use two entries
476 * (ie. computed gotos/XL form)
478 cpuhw
->bhrb_entries
[u_index
].to
= addr
;
479 cpuhw
->bhrb_entries
[u_index
].mispred
= pred
;
480 cpuhw
->bhrb_entries
[u_index
].predicted
= ~pred
;
482 /* Get from address in next entry */
483 val
= read_bhrb(r_index
++);
484 addr
= val
& BHRB_EA
;
485 if (val
& BHRB_TARGET
) {
486 /* Shouldn't have two targets in a
487 row.. Reset index and try again */
491 cpuhw
->bhrb_entries
[u_index
].from
= addr
;
493 /* Branches to immediate field
495 cpuhw
->bhrb_entries
[u_index
].from
= addr
;
496 cpuhw
->bhrb_entries
[u_index
].to
=
497 power_pmu_bhrb_to(addr
);
498 cpuhw
->bhrb_entries
[u_index
].mispred
= pred
;
499 cpuhw
->bhrb_entries
[u_index
].predicted
= ~pred
;
505 cpuhw
->bhrb_stack
.nr
= u_index
;
509 static bool is_ebb_event(struct perf_event
*event
)
512 * This could be a per-PMU callback, but we'd rather avoid the cost. We
513 * check that the PMU supports EBB, meaning those that don't can still
514 * use bit 63 of the event code for something else if they wish.
516 return (ppmu
->flags
& PPMU_ARCH_207S
) &&
517 ((event
->attr
.config
>> PERF_EVENT_CONFIG_EBB_SHIFT
) & 1);
520 static int ebb_event_check(struct perf_event
*event
)
522 struct perf_event
*leader
= event
->group_leader
;
524 /* Event and group leader must agree on EBB */
525 if (is_ebb_event(leader
) != is_ebb_event(event
))
528 if (is_ebb_event(event
)) {
529 if (!(event
->attach_state
& PERF_ATTACH_TASK
))
532 if (!leader
->attr
.pinned
|| !leader
->attr
.exclusive
)
535 if (event
->attr
.freq
||
536 event
->attr
.inherit
||
537 event
->attr
.sample_type
||
538 event
->attr
.sample_period
||
539 event
->attr
.enable_on_exec
)
546 static void ebb_event_add(struct perf_event
*event
)
548 if (!is_ebb_event(event
) || current
->thread
.used_ebb
)
552 * IFF this is the first time we've added an EBB event, set
553 * PMXE in the user MMCR0 so we can detect when it's cleared by
554 * userspace. We need this so that we can context switch while
555 * userspace is in the EBB handler (where PMXE is 0).
557 current
->thread
.used_ebb
= 1;
558 current
->thread
.mmcr0
|= MMCR0_PMXE
;
561 static void ebb_switch_out(unsigned long mmcr0
)
563 if (!(mmcr0
& MMCR0_EBE
))
566 current
->thread
.siar
= mfspr(SPRN_SIAR
);
567 current
->thread
.sier
= mfspr(SPRN_SIER
);
568 current
->thread
.sdar
= mfspr(SPRN_SDAR
);
569 current
->thread
.mmcr0
= mmcr0
& MMCR0_USER_MASK
;
570 current
->thread
.mmcr2
= mfspr(SPRN_MMCR2
) & MMCR2_USER_MASK
;
573 static unsigned long ebb_switch_in(bool ebb
, struct cpu_hw_events
*cpuhw
)
575 unsigned long mmcr0
= cpuhw
->mmcr
[0];
580 /* Enable EBB and read/write to all 6 PMCs and BHRB for userspace */
581 mmcr0
|= MMCR0_EBE
| MMCR0_BHRBA
| MMCR0_PMCC_U6
;
584 * Add any bits from the user MMCR0, FC or PMAO. This is compatible
585 * with pmao_restore_workaround() because we may add PMAO but we never
588 mmcr0
|= current
->thread
.mmcr0
;
591 * Be careful not to set PMXE if userspace had it cleared. This is also
592 * compatible with pmao_restore_workaround() because it has already
593 * cleared PMXE and we leave PMAO alone.
595 if (!(current
->thread
.mmcr0
& MMCR0_PMXE
))
596 mmcr0
&= ~MMCR0_PMXE
;
598 mtspr(SPRN_SIAR
, current
->thread
.siar
);
599 mtspr(SPRN_SIER
, current
->thread
.sier
);
600 mtspr(SPRN_SDAR
, current
->thread
.sdar
);
603 * Merge the kernel & user values of MMCR2. The semantics we implement
604 * are that the user MMCR2 can set bits, ie. cause counters to freeze,
605 * but not clear bits. If a task wants to be able to clear bits, ie.
606 * unfreeze counters, it should not set exclude_xxx in its events and
607 * instead manage the MMCR2 entirely by itself.
609 mtspr(SPRN_MMCR2
, cpuhw
->mmcr
[3] | current
->thread
.mmcr2
);
614 static void pmao_restore_workaround(bool ebb
)
618 if (!cpu_has_feature(CPU_FTR_PMAO_BUG
))
622 * On POWER8E there is a hardware defect which affects the PMU context
623 * switch logic, ie. power_pmu_disable/enable().
625 * When a counter overflows PMXE is cleared and FC/PMAO is set in MMCR0
626 * by the hardware. Sometime later the actual PMU exception is
629 * If we context switch, or simply disable/enable, the PMU prior to the
630 * exception arriving, the exception will be lost when we clear PMAO.
632 * When we reenable the PMU, we will write the saved MMCR0 with PMAO
633 * set, and this _should_ generate an exception. However because of the
634 * defect no exception is generated when we write PMAO, and we get
635 * stuck with no counters counting but no exception delivered.
637 * The workaround is to detect this case and tweak the hardware to
638 * create another pending PMU exception.
640 * We do that by setting up PMC6 (cycles) for an imminent overflow and
641 * enabling the PMU. That causes a new exception to be generated in the
642 * chip, but we don't take it yet because we have interrupts hard
643 * disabled. We then write back the PMU state as we want it to be seen
644 * by the exception handler. When we reenable interrupts the exception
645 * handler will be called and see the correct state.
647 * The logic is the same for EBB, except that the exception is gated by
648 * us having interrupts hard disabled as well as the fact that we are
649 * not in userspace. The exception is finally delivered when we return
653 /* Only if PMAO is set and PMAO_SYNC is clear */
654 if ((current
->thread
.mmcr0
& (MMCR0_PMAO
| MMCR0_PMAO_SYNC
)) != MMCR0_PMAO
)
657 /* If we're doing EBB, only if BESCR[GE] is set */
658 if (ebb
&& !(current
->thread
.bescr
& BESCR_GE
))
662 * We are already soft-disabled in power_pmu_enable(). We need to hard
663 * disable to actually prevent the PMU exception from firing.
668 * This is a bit gross, but we know we're on POWER8E and have 6 PMCs.
669 * Using read/write_pmc() in a for loop adds 12 function calls and
670 * almost doubles our code size.
672 pmcs
[0] = mfspr(SPRN_PMC1
);
673 pmcs
[1] = mfspr(SPRN_PMC2
);
674 pmcs
[2] = mfspr(SPRN_PMC3
);
675 pmcs
[3] = mfspr(SPRN_PMC4
);
676 pmcs
[4] = mfspr(SPRN_PMC5
);
677 pmcs
[5] = mfspr(SPRN_PMC6
);
679 /* Ensure all freeze bits are unset */
680 mtspr(SPRN_MMCR2
, 0);
682 /* Set up PMC6 to overflow in one cycle */
683 mtspr(SPRN_PMC6
, 0x7FFFFFFE);
685 /* Enable exceptions and unfreeze PMC6 */
686 mtspr(SPRN_MMCR0
, MMCR0_PMXE
| MMCR0_PMCjCE
| MMCR0_PMAO
);
688 /* Now we need to refreeze and restore the PMCs */
689 mtspr(SPRN_MMCR0
, MMCR0_FC
| MMCR0_PMAO
);
691 mtspr(SPRN_PMC1
, pmcs
[0]);
692 mtspr(SPRN_PMC2
, pmcs
[1]);
693 mtspr(SPRN_PMC3
, pmcs
[2]);
694 mtspr(SPRN_PMC4
, pmcs
[3]);
695 mtspr(SPRN_PMC5
, pmcs
[4]);
696 mtspr(SPRN_PMC6
, pmcs
[5]);
699 static bool use_ic(u64 event
)
701 if (cpu_has_feature(CPU_FTR_POWER9_DD1
) &&
702 (event
== 0x200f2 || event
== 0x300f2))
707 #endif /* CONFIG_PPC64 */
709 static void perf_event_interrupt(struct pt_regs
*regs
);
712 * Read one performance monitor counter (PMC).
714 static unsigned long read_pmc(int idx
)
720 val
= mfspr(SPRN_PMC1
);
723 val
= mfspr(SPRN_PMC2
);
726 val
= mfspr(SPRN_PMC3
);
729 val
= mfspr(SPRN_PMC4
);
732 val
= mfspr(SPRN_PMC5
);
735 val
= mfspr(SPRN_PMC6
);
739 val
= mfspr(SPRN_PMC7
);
742 val
= mfspr(SPRN_PMC8
);
744 #endif /* CONFIG_PPC64 */
746 printk(KERN_ERR
"oops trying to read PMC%d\n", idx
);
755 static void write_pmc(int idx
, unsigned long val
)
759 mtspr(SPRN_PMC1
, val
);
762 mtspr(SPRN_PMC2
, val
);
765 mtspr(SPRN_PMC3
, val
);
768 mtspr(SPRN_PMC4
, val
);
771 mtspr(SPRN_PMC5
, val
);
774 mtspr(SPRN_PMC6
, val
);
778 mtspr(SPRN_PMC7
, val
);
781 mtspr(SPRN_PMC8
, val
);
783 #endif /* CONFIG_PPC64 */
785 printk(KERN_ERR
"oops trying to write PMC%d\n", idx
);
789 /* Called from sysrq_handle_showregs() */
790 void perf_event_print_debug(void)
792 unsigned long sdar
, sier
, flags
;
793 u32 pmcs
[MAX_HWEVENTS
];
796 if (!ppmu
->n_counter
)
799 local_irq_save(flags
);
801 pr_info("CPU: %d PMU registers, ppmu = %s n_counters = %d",
802 smp_processor_id(), ppmu
->name
, ppmu
->n_counter
);
804 for (i
= 0; i
< ppmu
->n_counter
; i
++)
805 pmcs
[i
] = read_pmc(i
+ 1);
807 for (; i
< MAX_HWEVENTS
; i
++)
808 pmcs
[i
] = 0xdeadbeef;
810 pr_info("PMC1: %08x PMC2: %08x PMC3: %08x PMC4: %08x\n",
811 pmcs
[0], pmcs
[1], pmcs
[2], pmcs
[3]);
813 if (ppmu
->n_counter
> 4)
814 pr_info("PMC5: %08x PMC6: %08x PMC7: %08x PMC8: %08x\n",
815 pmcs
[4], pmcs
[5], pmcs
[6], pmcs
[7]);
817 pr_info("MMCR0: %016lx MMCR1: %016lx MMCRA: %016lx\n",
818 mfspr(SPRN_MMCR0
), mfspr(SPRN_MMCR1
), mfspr(SPRN_MMCRA
));
822 sdar
= mfspr(SPRN_SDAR
);
824 if (ppmu
->flags
& PPMU_HAS_SIER
)
825 sier
= mfspr(SPRN_SIER
);
827 if (ppmu
->flags
& PPMU_ARCH_207S
) {
828 pr_info("MMCR2: %016lx EBBHR: %016lx\n",
829 mfspr(SPRN_MMCR2
), mfspr(SPRN_EBBHR
));
830 pr_info("EBBRR: %016lx BESCR: %016lx\n",
831 mfspr(SPRN_EBBRR
), mfspr(SPRN_BESCR
));
834 pr_info("SIAR: %016lx SDAR: %016lx SIER: %016lx\n",
835 mfspr(SPRN_SIAR
), sdar
, sier
);
837 local_irq_restore(flags
);
841 * Check if a set of events can all go on the PMU at once.
842 * If they can't, this will look at alternative codes for the events
843 * and see if any combination of alternative codes is feasible.
844 * The feasible set is returned in event_id[].
846 static int power_check_constraints(struct cpu_hw_events
*cpuhw
,
847 u64 event_id
[], unsigned int cflags
[],
850 unsigned long mask
, value
, nv
;
851 unsigned long smasks
[MAX_HWEVENTS
], svalues
[MAX_HWEVENTS
];
852 int n_alt
[MAX_HWEVENTS
], choice
[MAX_HWEVENTS
];
854 unsigned long addf
= ppmu
->add_fields
;
855 unsigned long tadd
= ppmu
->test_adder
;
857 if (n_ev
> ppmu
->n_counter
)
860 /* First see if the events will go on as-is */
861 for (i
= 0; i
< n_ev
; ++i
) {
862 if ((cflags
[i
] & PPMU_LIMITED_PMC_REQD
)
863 && !ppmu
->limited_pmc_event(event_id
[i
])) {
864 ppmu
->get_alternatives(event_id
[i
], cflags
[i
],
865 cpuhw
->alternatives
[i
]);
866 event_id
[i
] = cpuhw
->alternatives
[i
][0];
868 if (ppmu
->get_constraint(event_id
[i
], &cpuhw
->amasks
[i
][0],
869 &cpuhw
->avalues
[i
][0]))
873 for (i
= 0; i
< n_ev
; ++i
) {
874 nv
= (value
| cpuhw
->avalues
[i
][0]) +
875 (value
& cpuhw
->avalues
[i
][0] & addf
);
876 if ((((nv
+ tadd
) ^ value
) & mask
) != 0 ||
877 (((nv
+ tadd
) ^ cpuhw
->avalues
[i
][0]) &
878 cpuhw
->amasks
[i
][0]) != 0)
881 mask
|= cpuhw
->amasks
[i
][0];
884 return 0; /* all OK */
886 /* doesn't work, gather alternatives... */
887 if (!ppmu
->get_alternatives
)
889 for (i
= 0; i
< n_ev
; ++i
) {
891 n_alt
[i
] = ppmu
->get_alternatives(event_id
[i
], cflags
[i
],
892 cpuhw
->alternatives
[i
]);
893 for (j
= 1; j
< n_alt
[i
]; ++j
)
894 ppmu
->get_constraint(cpuhw
->alternatives
[i
][j
],
895 &cpuhw
->amasks
[i
][j
],
896 &cpuhw
->avalues
[i
][j
]);
899 /* enumerate all possibilities and see if any will work */
902 value
= mask
= nv
= 0;
905 /* we're backtracking, restore context */
911 * See if any alternative k for event_id i,
912 * where k > j, will satisfy the constraints.
914 while (++j
< n_alt
[i
]) {
915 nv
= (value
| cpuhw
->avalues
[i
][j
]) +
916 (value
& cpuhw
->avalues
[i
][j
] & addf
);
917 if ((((nv
+ tadd
) ^ value
) & mask
) == 0 &&
918 (((nv
+ tadd
) ^ cpuhw
->avalues
[i
][j
])
919 & cpuhw
->amasks
[i
][j
]) == 0)
924 * No feasible alternative, backtrack
925 * to event_id i-1 and continue enumerating its
926 * alternatives from where we got up to.
932 * Found a feasible alternative for event_id i,
933 * remember where we got up to with this event_id,
934 * go on to the next event_id, and start with
935 * the first alternative for it.
941 mask
|= cpuhw
->amasks
[i
][j
];
947 /* OK, we have a feasible combination, tell the caller the solution */
948 for (i
= 0; i
< n_ev
; ++i
)
949 event_id
[i
] = cpuhw
->alternatives
[i
][choice
[i
]];
954 * Check if newly-added events have consistent settings for
955 * exclude_{user,kernel,hv} with each other and any previously
958 static int check_excludes(struct perf_event
**ctrs
, unsigned int cflags
[],
959 int n_prev
, int n_new
)
961 int eu
= 0, ek
= 0, eh
= 0;
963 struct perf_event
*event
;
966 * If the PMU we're on supports per event exclude settings then we
967 * don't need to do any of this logic. NB. This assumes no PMU has both
968 * per event exclude and limited PMCs.
970 if (ppmu
->flags
& PPMU_ARCH_207S
)
978 for (i
= 0; i
< n
; ++i
) {
979 if (cflags
[i
] & PPMU_LIMITED_PMC_OK
) {
980 cflags
[i
] &= ~PPMU_LIMITED_PMC_REQD
;
985 eu
= event
->attr
.exclude_user
;
986 ek
= event
->attr
.exclude_kernel
;
987 eh
= event
->attr
.exclude_hv
;
989 } else if (event
->attr
.exclude_user
!= eu
||
990 event
->attr
.exclude_kernel
!= ek
||
991 event
->attr
.exclude_hv
!= eh
) {
997 for (i
= 0; i
< n
; ++i
)
998 if (cflags
[i
] & PPMU_LIMITED_PMC_OK
)
999 cflags
[i
] |= PPMU_LIMITED_PMC_REQD
;
1004 static u64
check_and_compute_delta(u64 prev
, u64 val
)
1006 u64 delta
= (val
- prev
) & 0xfffffffful
;
1009 * POWER7 can roll back counter values, if the new value is smaller
1010 * than the previous value it will cause the delta and the counter to
1011 * have bogus values unless we rolled a counter over. If a coutner is
1012 * rolled back, it will be smaller, but within 256, which is the maximum
1013 * number of events to rollback at once. If we detect a rollback
1014 * return 0. This can lead to a small lack of precision in the
1017 if (prev
> val
&& (prev
- val
) < 256)
1023 static void power_pmu_read(struct perf_event
*event
)
1025 s64 val
, delta
, prev
;
1026 struct cpu_hw_events
*cpuhw
= this_cpu_ptr(&cpu_hw_events
);
1028 if (event
->hw
.state
& PERF_HES_STOPPED
)
1034 if (is_ebb_event(event
)) {
1035 val
= read_pmc(event
->hw
.idx
);
1036 if (use_ic(event
->attr
.config
)) {
1037 val
= mfspr(SPRN_IC
);
1038 if (val
> cpuhw
->ic_init
)
1039 val
= val
- cpuhw
->ic_init
;
1041 val
= val
+ (0 - cpuhw
->ic_init
);
1043 local64_set(&event
->hw
.prev_count
, val
);
1048 * Performance monitor interrupts come even when interrupts
1049 * are soft-disabled, as long as interrupts are hard-enabled.
1050 * Therefore we treat them like NMIs.
1053 prev
= local64_read(&event
->hw
.prev_count
);
1055 val
= read_pmc(event
->hw
.idx
);
1056 if (use_ic(event
->attr
.config
)) {
1057 val
= mfspr(SPRN_IC
);
1058 if (val
> cpuhw
->ic_init
)
1059 val
= val
- cpuhw
->ic_init
;
1061 val
= val
+ (0 - cpuhw
->ic_init
);
1063 delta
= check_and_compute_delta(prev
, val
);
1066 } while (local64_cmpxchg(&event
->hw
.prev_count
, prev
, val
) != prev
);
1068 local64_add(delta
, &event
->count
);
1071 * A number of places program the PMC with (0x80000000 - period_left).
1072 * We never want period_left to be less than 1 because we will program
1073 * the PMC with a value >= 0x800000000 and an edge detected PMC will
1074 * roll around to 0 before taking an exception. We have seen this
1077 * To fix this, clamp the minimum value of period_left to 1.
1080 prev
= local64_read(&event
->hw
.period_left
);
1084 } while (local64_cmpxchg(&event
->hw
.period_left
, prev
, val
) != prev
);
1088 * On some machines, PMC5 and PMC6 can't be written, don't respect
1089 * the freeze conditions, and don't generate interrupts. This tells
1090 * us if `event' is using such a PMC.
1092 static int is_limited_pmc(int pmcnum
)
1094 return (ppmu
->flags
& PPMU_LIMITED_PMC5_6
)
1095 && (pmcnum
== 5 || pmcnum
== 6);
1098 static void freeze_limited_counters(struct cpu_hw_events
*cpuhw
,
1099 unsigned long pmc5
, unsigned long pmc6
)
1101 struct perf_event
*event
;
1102 u64 val
, prev
, delta
;
1105 for (i
= 0; i
< cpuhw
->n_limited
; ++i
) {
1106 event
= cpuhw
->limited_counter
[i
];
1109 val
= (event
->hw
.idx
== 5) ? pmc5
: pmc6
;
1110 prev
= local64_read(&event
->hw
.prev_count
);
1112 delta
= check_and_compute_delta(prev
, val
);
1114 local64_add(delta
, &event
->count
);
1118 static void thaw_limited_counters(struct cpu_hw_events
*cpuhw
,
1119 unsigned long pmc5
, unsigned long pmc6
)
1121 struct perf_event
*event
;
1125 for (i
= 0; i
< cpuhw
->n_limited
; ++i
) {
1126 event
= cpuhw
->limited_counter
[i
];
1127 event
->hw
.idx
= cpuhw
->limited_hwidx
[i
];
1128 val
= (event
->hw
.idx
== 5) ? pmc5
: pmc6
;
1129 prev
= local64_read(&event
->hw
.prev_count
);
1130 if (check_and_compute_delta(prev
, val
))
1131 local64_set(&event
->hw
.prev_count
, val
);
1132 perf_event_update_userpage(event
);
1137 * Since limited events don't respect the freeze conditions, we
1138 * have to read them immediately after freezing or unfreezing the
1139 * other events. We try to keep the values from the limited
1140 * events as consistent as possible by keeping the delay (in
1141 * cycles and instructions) between freezing/unfreezing and reading
1142 * the limited events as small and consistent as possible.
1143 * Therefore, if any limited events are in use, we read them
1144 * both, and always in the same order, to minimize variability,
1145 * and do it inside the same asm that writes MMCR0.
1147 static void write_mmcr0(struct cpu_hw_events
*cpuhw
, unsigned long mmcr0
)
1149 unsigned long pmc5
, pmc6
;
1151 if (!cpuhw
->n_limited
) {
1152 mtspr(SPRN_MMCR0
, mmcr0
);
1157 * Write MMCR0, then read PMC5 and PMC6 immediately.
1158 * To ensure we don't get a performance monitor interrupt
1159 * between writing MMCR0 and freezing/thawing the limited
1160 * events, we first write MMCR0 with the event overflow
1161 * interrupt enable bits turned off.
1163 asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5"
1164 : "=&r" (pmc5
), "=&r" (pmc6
)
1165 : "r" (mmcr0
& ~(MMCR0_PMC1CE
| MMCR0_PMCjCE
)),
1167 "i" (SPRN_PMC5
), "i" (SPRN_PMC6
));
1169 if (mmcr0
& MMCR0_FC
)
1170 freeze_limited_counters(cpuhw
, pmc5
, pmc6
);
1172 thaw_limited_counters(cpuhw
, pmc5
, pmc6
);
1175 * Write the full MMCR0 including the event overflow interrupt
1176 * enable bits, if necessary.
1178 if (mmcr0
& (MMCR0_PMC1CE
| MMCR0_PMCjCE
))
1179 mtspr(SPRN_MMCR0
, mmcr0
);
1183 * Disable all events to prevent PMU interrupts and to allow
1184 * events to be added or removed.
1186 static void power_pmu_disable(struct pmu
*pmu
)
1188 struct cpu_hw_events
*cpuhw
;
1189 unsigned long flags
, mmcr0
, val
;
1193 local_irq_save(flags
);
1194 cpuhw
= this_cpu_ptr(&cpu_hw_events
);
1196 if (!cpuhw
->disabled
) {
1198 * Check if we ever enabled the PMU on this cpu.
1200 if (!cpuhw
->pmcs_enabled
) {
1202 cpuhw
->pmcs_enabled
= 1;
1206 * Set the 'freeze counters' bit, clear EBE/BHRBA/PMCC/PMAO/FC56
1208 val
= mmcr0
= mfspr(SPRN_MMCR0
);
1210 val
&= ~(MMCR0_EBE
| MMCR0_BHRBA
| MMCR0_PMCC
| MMCR0_PMAO
|
1214 * The barrier is to make sure the mtspr has been
1215 * executed and the PMU has frozen the events etc.
1218 write_mmcr0(cpuhw
, val
);
1222 * Disable instruction sampling if it was enabled
1224 if (cpuhw
->mmcr
[2] & MMCRA_SAMPLE_ENABLE
) {
1226 cpuhw
->mmcr
[2] & ~MMCRA_SAMPLE_ENABLE
);
1230 cpuhw
->disabled
= 1;
1233 ebb_switch_out(mmcr0
);
1236 local_irq_restore(flags
);
1240 * Re-enable all events if disable == 0.
1241 * If we were previously disabled and events were added, then
1242 * put the new config on the PMU.
1244 static void power_pmu_enable(struct pmu
*pmu
)
1246 struct perf_event
*event
;
1247 struct cpu_hw_events
*cpuhw
;
1248 unsigned long flags
;
1250 unsigned long val
, mmcr0
;
1252 unsigned int hwc_index
[MAX_HWEVENTS
];
1259 local_irq_save(flags
);
1261 cpuhw
= this_cpu_ptr(&cpu_hw_events
);
1262 if (!cpuhw
->disabled
)
1265 if (cpuhw
->n_events
== 0) {
1266 ppc_set_pmu_inuse(0);
1270 cpuhw
->disabled
= 0;
1273 * EBB requires an exclusive group and all events must have the EBB
1274 * flag set, or not set, so we can just check a single event. Also we
1275 * know we have at least one event.
1277 ebb
= is_ebb_event(cpuhw
->event
[0]);
1280 * If we didn't change anything, or only removed events,
1281 * no need to recalculate MMCR* settings and reset the PMCs.
1282 * Just reenable the PMU with the current MMCR* settings
1283 * (possibly updated for removal of events).
1285 if (!cpuhw
->n_added
) {
1286 mtspr(SPRN_MMCRA
, cpuhw
->mmcr
[2] & ~MMCRA_SAMPLE_ENABLE
);
1287 mtspr(SPRN_MMCR1
, cpuhw
->mmcr
[1]);
1292 * Clear all MMCR settings and recompute them for the new set of events.
1294 memset(cpuhw
->mmcr
, 0, sizeof(cpuhw
->mmcr
));
1296 if (ppmu
->compute_mmcr(cpuhw
->events
, cpuhw
->n_events
, hwc_index
,
1297 cpuhw
->mmcr
, cpuhw
->event
)) {
1298 /* shouldn't ever get here */
1299 printk(KERN_ERR
"oops compute_mmcr failed\n");
1303 if (!(ppmu
->flags
& PPMU_ARCH_207S
)) {
1305 * Add in MMCR0 freeze bits corresponding to the attr.exclude_*
1306 * bits for the first event. We have already checked that all
1307 * events have the same value for these bits as the first event.
1309 event
= cpuhw
->event
[0];
1310 if (event
->attr
.exclude_user
)
1311 cpuhw
->mmcr
[0] |= MMCR0_FCP
;
1312 if (event
->attr
.exclude_kernel
)
1313 cpuhw
->mmcr
[0] |= freeze_events_kernel
;
1314 if (event
->attr
.exclude_hv
)
1315 cpuhw
->mmcr
[0] |= MMCR0_FCHV
;
1319 * Write the new configuration to MMCR* with the freeze
1320 * bit set and set the hardware events to their initial values.
1321 * Then unfreeze the events.
1323 ppc_set_pmu_inuse(1);
1324 mtspr(SPRN_MMCRA
, cpuhw
->mmcr
[2] & ~MMCRA_SAMPLE_ENABLE
);
1325 mtspr(SPRN_MMCR1
, cpuhw
->mmcr
[1]);
1326 mtspr(SPRN_MMCR0
, (cpuhw
->mmcr
[0] & ~(MMCR0_PMC1CE
| MMCR0_PMCjCE
))
1328 if (ppmu
->flags
& PPMU_ARCH_207S
)
1329 mtspr(SPRN_MMCR2
, cpuhw
->mmcr
[3]);
1332 * Read off any pre-existing events that need to move
1335 for (i
= 0; i
< cpuhw
->n_events
; ++i
) {
1336 event
= cpuhw
->event
[i
];
1337 if (event
->hw
.idx
&& event
->hw
.idx
!= hwc_index
[i
] + 1) {
1338 power_pmu_read(event
);
1339 write_pmc(event
->hw
.idx
, 0);
1345 * Initialize the PMCs for all the new and moved events.
1347 cpuhw
->n_limited
= n_lim
= 0;
1348 for (i
= 0; i
< cpuhw
->n_events
; ++i
) {
1349 event
= cpuhw
->event
[i
];
1352 idx
= hwc_index
[i
] + 1;
1353 if (is_limited_pmc(idx
)) {
1354 cpuhw
->limited_counter
[n_lim
] = event
;
1355 cpuhw
->limited_hwidx
[n_lim
] = idx
;
1361 val
= local64_read(&event
->hw
.prev_count
);
1364 if (event
->hw
.sample_period
) {
1365 left
= local64_read(&event
->hw
.period_left
);
1366 if (left
< 0x80000000L
)
1367 val
= 0x80000000L
- left
;
1369 local64_set(&event
->hw
.prev_count
, val
);
1372 event
->hw
.idx
= idx
;
1373 if (event
->hw
.state
& PERF_HES_STOPPED
)
1375 write_pmc(idx
, val
);
1377 perf_event_update_userpage(event
);
1379 cpuhw
->n_limited
= n_lim
;
1380 cpuhw
->mmcr
[0] |= MMCR0_PMXE
| MMCR0_FCECE
;
1383 pmao_restore_workaround(ebb
);
1385 mmcr0
= ebb_switch_in(ebb
, cpuhw
);
1388 if (cpuhw
->bhrb_users
)
1389 ppmu
->config_bhrb(cpuhw
->bhrb_filter
);
1391 write_mmcr0(cpuhw
, mmcr0
);
1394 * Enable instruction sampling if necessary
1396 if (cpuhw
->mmcr
[2] & MMCRA_SAMPLE_ENABLE
) {
1398 mtspr(SPRN_MMCRA
, cpuhw
->mmcr
[2]);
1403 local_irq_restore(flags
);
1406 static int collect_events(struct perf_event
*group
, int max_count
,
1407 struct perf_event
*ctrs
[], u64
*events
,
1408 unsigned int *flags
)
1411 struct perf_event
*event
;
1413 if (!is_software_event(group
)) {
1417 flags
[n
] = group
->hw
.event_base
;
1418 events
[n
++] = group
->hw
.config
;
1420 list_for_each_entry(event
, &group
->sibling_list
, group_entry
) {
1421 if (!is_software_event(event
) &&
1422 event
->state
!= PERF_EVENT_STATE_OFF
) {
1426 flags
[n
] = event
->hw
.event_base
;
1427 events
[n
++] = event
->hw
.config
;
1434 * Add a event to the PMU.
1435 * If all events are not already frozen, then we disable and
1436 * re-enable the PMU in order to get hw_perf_enable to do the
1437 * actual work of reconfiguring the PMU.
1439 static int power_pmu_add(struct perf_event
*event
, int ef_flags
)
1441 struct cpu_hw_events
*cpuhw
;
1442 unsigned long flags
;
1446 local_irq_save(flags
);
1447 perf_pmu_disable(event
->pmu
);
1450 * Add the event to the list (if there is room)
1451 * and check whether the total set is still feasible.
1453 cpuhw
= this_cpu_ptr(&cpu_hw_events
);
1454 n0
= cpuhw
->n_events
;
1455 if (n0
>= ppmu
->n_counter
)
1457 cpuhw
->event
[n0
] = event
;
1458 cpuhw
->events
[n0
] = event
->hw
.config
;
1459 cpuhw
->flags
[n0
] = event
->hw
.event_base
;
1462 * This event may have been disabled/stopped in record_and_restart()
1463 * because we exceeded the ->event_limit. If re-starting the event,
1464 * clear the ->hw.state (STOPPED and UPTODATE flags), so the user
1465 * notification is re-enabled.
1467 if (!(ef_flags
& PERF_EF_START
))
1468 event
->hw
.state
= PERF_HES_STOPPED
| PERF_HES_UPTODATE
;
1470 event
->hw
.state
= 0;
1473 * If group events scheduling transaction was started,
1474 * skip the schedulability test here, it will be performed
1475 * at commit time(->commit_txn) as a whole
1477 if (cpuhw
->txn_flags
& PERF_PMU_TXN_ADD
)
1480 if (check_excludes(cpuhw
->event
, cpuhw
->flags
, n0
, 1))
1482 if (power_check_constraints(cpuhw
, cpuhw
->events
, cpuhw
->flags
, n0
+ 1))
1484 event
->hw
.config
= cpuhw
->events
[n0
];
1487 ebb_event_add(event
);
1494 if (has_branch_stack(event
)) {
1495 power_pmu_bhrb_enable(event
);
1496 cpuhw
->bhrb_filter
= ppmu
->bhrb_filter_map(
1497 event
->attr
.branch_sample_type
);
1501 * Workaround for POWER9 DD1 to use the Instruction Counter
1502 * register value for instruction counting
1504 if (use_ic(event
->attr
.config
))
1505 cpuhw
->ic_init
= mfspr(SPRN_IC
);
1507 perf_pmu_enable(event
->pmu
);
1508 local_irq_restore(flags
);
1513 * Remove a event from the PMU.
1515 static void power_pmu_del(struct perf_event
*event
, int ef_flags
)
1517 struct cpu_hw_events
*cpuhw
;
1519 unsigned long flags
;
1521 local_irq_save(flags
);
1522 perf_pmu_disable(event
->pmu
);
1524 power_pmu_read(event
);
1526 cpuhw
= this_cpu_ptr(&cpu_hw_events
);
1527 for (i
= 0; i
< cpuhw
->n_events
; ++i
) {
1528 if (event
== cpuhw
->event
[i
]) {
1529 while (++i
< cpuhw
->n_events
) {
1530 cpuhw
->event
[i
-1] = cpuhw
->event
[i
];
1531 cpuhw
->events
[i
-1] = cpuhw
->events
[i
];
1532 cpuhw
->flags
[i
-1] = cpuhw
->flags
[i
];
1535 ppmu
->disable_pmc(event
->hw
.idx
- 1, cpuhw
->mmcr
);
1536 if (event
->hw
.idx
) {
1537 write_pmc(event
->hw
.idx
, 0);
1540 perf_event_update_userpage(event
);
1544 for (i
= 0; i
< cpuhw
->n_limited
; ++i
)
1545 if (event
== cpuhw
->limited_counter
[i
])
1547 if (i
< cpuhw
->n_limited
) {
1548 while (++i
< cpuhw
->n_limited
) {
1549 cpuhw
->limited_counter
[i
-1] = cpuhw
->limited_counter
[i
];
1550 cpuhw
->limited_hwidx
[i
-1] = cpuhw
->limited_hwidx
[i
];
1554 if (cpuhw
->n_events
== 0) {
1555 /* disable exceptions if no events are running */
1556 cpuhw
->mmcr
[0] &= ~(MMCR0_PMXE
| MMCR0_FCECE
);
1559 if (has_branch_stack(event
))
1560 power_pmu_bhrb_disable(event
);
1562 perf_pmu_enable(event
->pmu
);
1563 local_irq_restore(flags
);
1567 * POWER-PMU does not support disabling individual counters, hence
1568 * program their cycle counter to their max value and ignore the interrupts.
1571 static void power_pmu_start(struct perf_event
*event
, int ef_flags
)
1573 unsigned long flags
;
1577 if (!event
->hw
.idx
|| !event
->hw
.sample_period
)
1580 if (!(event
->hw
.state
& PERF_HES_STOPPED
))
1583 if (ef_flags
& PERF_EF_RELOAD
)
1584 WARN_ON_ONCE(!(event
->hw
.state
& PERF_HES_UPTODATE
));
1586 local_irq_save(flags
);
1587 perf_pmu_disable(event
->pmu
);
1589 event
->hw
.state
= 0;
1590 left
= local64_read(&event
->hw
.period_left
);
1593 if (left
< 0x80000000L
)
1594 val
= 0x80000000L
- left
;
1596 write_pmc(event
->hw
.idx
, val
);
1598 perf_event_update_userpage(event
);
1599 perf_pmu_enable(event
->pmu
);
1600 local_irq_restore(flags
);
1603 static void power_pmu_stop(struct perf_event
*event
, int ef_flags
)
1605 unsigned long flags
;
1607 if (!event
->hw
.idx
|| !event
->hw
.sample_period
)
1610 if (event
->hw
.state
& PERF_HES_STOPPED
)
1613 local_irq_save(flags
);
1614 perf_pmu_disable(event
->pmu
);
1616 power_pmu_read(event
);
1617 event
->hw
.state
|= PERF_HES_STOPPED
| PERF_HES_UPTODATE
;
1618 write_pmc(event
->hw
.idx
, 0);
1620 perf_event_update_userpage(event
);
1621 perf_pmu_enable(event
->pmu
);
1622 local_irq_restore(flags
);
1626 * Start group events scheduling transaction
1627 * Set the flag to make pmu::enable() not perform the
1628 * schedulability test, it will be performed at commit time
1630 * We only support PERF_PMU_TXN_ADD transactions. Save the
1631 * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
1634 static void power_pmu_start_txn(struct pmu
*pmu
, unsigned int txn_flags
)
1636 struct cpu_hw_events
*cpuhw
= this_cpu_ptr(&cpu_hw_events
);
1638 WARN_ON_ONCE(cpuhw
->txn_flags
); /* txn already in flight */
1640 cpuhw
->txn_flags
= txn_flags
;
1641 if (txn_flags
& ~PERF_PMU_TXN_ADD
)
1644 perf_pmu_disable(pmu
);
1645 cpuhw
->n_txn_start
= cpuhw
->n_events
;
1649 * Stop group events scheduling transaction
1650 * Clear the flag and pmu::enable() will perform the
1651 * schedulability test.
1653 static void power_pmu_cancel_txn(struct pmu
*pmu
)
1655 struct cpu_hw_events
*cpuhw
= this_cpu_ptr(&cpu_hw_events
);
1656 unsigned int txn_flags
;
1658 WARN_ON_ONCE(!cpuhw
->txn_flags
); /* no txn in flight */
1660 txn_flags
= cpuhw
->txn_flags
;
1661 cpuhw
->txn_flags
= 0;
1662 if (txn_flags
& ~PERF_PMU_TXN_ADD
)
1665 perf_pmu_enable(pmu
);
1669 * Commit group events scheduling transaction
1670 * Perform the group schedulability test as a whole
1671 * Return 0 if success
1673 static int power_pmu_commit_txn(struct pmu
*pmu
)
1675 struct cpu_hw_events
*cpuhw
;
1681 cpuhw
= this_cpu_ptr(&cpu_hw_events
);
1682 WARN_ON_ONCE(!cpuhw
->txn_flags
); /* no txn in flight */
1684 if (cpuhw
->txn_flags
& ~PERF_PMU_TXN_ADD
) {
1685 cpuhw
->txn_flags
= 0;
1689 n
= cpuhw
->n_events
;
1690 if (check_excludes(cpuhw
->event
, cpuhw
->flags
, 0, n
))
1692 i
= power_check_constraints(cpuhw
, cpuhw
->events
, cpuhw
->flags
, n
);
1696 for (i
= cpuhw
->n_txn_start
; i
< n
; ++i
)
1697 cpuhw
->event
[i
]->hw
.config
= cpuhw
->events
[i
];
1699 cpuhw
->txn_flags
= 0;
1700 perf_pmu_enable(pmu
);
1705 * Return 1 if we might be able to put event on a limited PMC,
1707 * A event can only go on a limited PMC if it counts something
1708 * that a limited PMC can count, doesn't require interrupts, and
1709 * doesn't exclude any processor mode.
1711 static int can_go_on_limited_pmc(struct perf_event
*event
, u64 ev
,
1715 u64 alt
[MAX_EVENT_ALTERNATIVES
];
1717 if (event
->attr
.exclude_user
1718 || event
->attr
.exclude_kernel
1719 || event
->attr
.exclude_hv
1720 || event
->attr
.sample_period
)
1723 if (ppmu
->limited_pmc_event(ev
))
1727 * The requested event_id isn't on a limited PMC already;
1728 * see if any alternative code goes on a limited PMC.
1730 if (!ppmu
->get_alternatives
)
1733 flags
|= PPMU_LIMITED_PMC_OK
| PPMU_LIMITED_PMC_REQD
;
1734 n
= ppmu
->get_alternatives(ev
, flags
, alt
);
1740 * Find an alternative event_id that goes on a normal PMC, if possible,
1741 * and return the event_id code, or 0 if there is no such alternative.
1742 * (Note: event_id code 0 is "don't count" on all machines.)
1744 static u64
normal_pmc_alternative(u64 ev
, unsigned long flags
)
1746 u64 alt
[MAX_EVENT_ALTERNATIVES
];
1749 flags
&= ~(PPMU_LIMITED_PMC_OK
| PPMU_LIMITED_PMC_REQD
);
1750 n
= ppmu
->get_alternatives(ev
, flags
, alt
);
1756 /* Number of perf_events counting hardware events */
1757 static atomic_t num_events
;
1758 /* Used to avoid races in calling reserve/release_pmc_hardware */
1759 static DEFINE_MUTEX(pmc_reserve_mutex
);
1762 * Release the PMU if this is the last perf_event.
1764 static void hw_perf_event_destroy(struct perf_event
*event
)
1766 if (!atomic_add_unless(&num_events
, -1, 1)) {
1767 mutex_lock(&pmc_reserve_mutex
);
1768 if (atomic_dec_return(&num_events
) == 0)
1769 release_pmc_hardware();
1770 mutex_unlock(&pmc_reserve_mutex
);
1775 * Translate a generic cache event_id config to a raw event_id code.
1777 static int hw_perf_cache_event(u64 config
, u64
*eventp
)
1779 unsigned long type
, op
, result
;
1782 if (!ppmu
->cache_events
)
1786 type
= config
& 0xff;
1787 op
= (config
>> 8) & 0xff;
1788 result
= (config
>> 16) & 0xff;
1790 if (type
>= PERF_COUNT_HW_CACHE_MAX
||
1791 op
>= PERF_COUNT_HW_CACHE_OP_MAX
||
1792 result
>= PERF_COUNT_HW_CACHE_RESULT_MAX
)
1795 ev
= (*ppmu
->cache_events
)[type
][op
][result
];
1804 static int power_pmu_event_init(struct perf_event
*event
)
1807 unsigned long flags
;
1808 struct perf_event
*ctrs
[MAX_HWEVENTS
];
1809 u64 events
[MAX_HWEVENTS
];
1810 unsigned int cflags
[MAX_HWEVENTS
];
1813 struct cpu_hw_events
*cpuhw
;
1818 if (has_branch_stack(event
)) {
1819 /* PMU has BHRB enabled */
1820 if (!(ppmu
->flags
& PPMU_ARCH_207S
))
1824 switch (event
->attr
.type
) {
1825 case PERF_TYPE_HARDWARE
:
1826 ev
= event
->attr
.config
;
1827 if (ev
>= ppmu
->n_generic
|| ppmu
->generic_events
[ev
] == 0)
1829 ev
= ppmu
->generic_events
[ev
];
1831 case PERF_TYPE_HW_CACHE
:
1832 err
= hw_perf_cache_event(event
->attr
.config
, &ev
);
1837 ev
= event
->attr
.config
;
1843 event
->hw
.config_base
= ev
;
1847 * If we are not running on a hypervisor, force the
1848 * exclude_hv bit to 0 so that we don't care what
1849 * the user set it to.
1851 if (!firmware_has_feature(FW_FEATURE_LPAR
))
1852 event
->attr
.exclude_hv
= 0;
1855 * If this is a per-task event, then we can use
1856 * PM_RUN_* events interchangeably with their non RUN_*
1857 * equivalents, e.g. PM_RUN_CYC instead of PM_CYC.
1858 * XXX we should check if the task is an idle task.
1861 if (event
->attach_state
& PERF_ATTACH_TASK
)
1862 flags
|= PPMU_ONLY_COUNT_RUN
;
1865 * If this machine has limited events, check whether this
1866 * event_id could go on a limited event.
1868 if (ppmu
->flags
& PPMU_LIMITED_PMC5_6
) {
1869 if (can_go_on_limited_pmc(event
, ev
, flags
)) {
1870 flags
|= PPMU_LIMITED_PMC_OK
;
1871 } else if (ppmu
->limited_pmc_event(ev
)) {
1873 * The requested event_id is on a limited PMC,
1874 * but we can't use a limited PMC; see if any
1875 * alternative goes on a normal PMC.
1877 ev
= normal_pmc_alternative(ev
, flags
);
1883 /* Extra checks for EBB */
1884 err
= ebb_event_check(event
);
1889 * If this is in a group, check if it can go on with all the
1890 * other hardware events in the group. We assume the event
1891 * hasn't been linked into its leader's sibling list at this point.
1894 if (event
->group_leader
!= event
) {
1895 n
= collect_events(event
->group_leader
, ppmu
->n_counter
- 1,
1896 ctrs
, events
, cflags
);
1903 if (check_excludes(ctrs
, cflags
, n
, 1))
1906 cpuhw
= &get_cpu_var(cpu_hw_events
);
1907 err
= power_check_constraints(cpuhw
, events
, cflags
, n
+ 1);
1909 if (has_branch_stack(event
)) {
1910 cpuhw
->bhrb_filter
= ppmu
->bhrb_filter_map(
1911 event
->attr
.branch_sample_type
);
1913 if (cpuhw
->bhrb_filter
== -1) {
1914 put_cpu_var(cpu_hw_events
);
1919 put_cpu_var(cpu_hw_events
);
1923 event
->hw
.config
= events
[n
];
1924 event
->hw
.event_base
= cflags
[n
];
1925 event
->hw
.last_period
= event
->hw
.sample_period
;
1926 local64_set(&event
->hw
.period_left
, event
->hw
.last_period
);
1929 * For EBB events we just context switch the PMC value, we don't do any
1930 * of the sample_period logic. We use hw.prev_count for this.
1932 if (is_ebb_event(event
))
1933 local64_set(&event
->hw
.prev_count
, 0);
1936 * See if we need to reserve the PMU.
1937 * If no events are currently in use, then we have to take a
1938 * mutex to ensure that we don't race with another task doing
1939 * reserve_pmc_hardware or release_pmc_hardware.
1942 if (!atomic_inc_not_zero(&num_events
)) {
1943 mutex_lock(&pmc_reserve_mutex
);
1944 if (atomic_read(&num_events
) == 0 &&
1945 reserve_pmc_hardware(perf_event_interrupt
))
1948 atomic_inc(&num_events
);
1949 mutex_unlock(&pmc_reserve_mutex
);
1951 event
->destroy
= hw_perf_event_destroy
;
1956 static int power_pmu_event_idx(struct perf_event
*event
)
1958 return event
->hw
.idx
;
1961 ssize_t
power_events_sysfs_show(struct device
*dev
,
1962 struct device_attribute
*attr
, char *page
)
1964 struct perf_pmu_events_attr
*pmu_attr
;
1966 pmu_attr
= container_of(attr
, struct perf_pmu_events_attr
, attr
);
1968 return sprintf(page
, "event=0x%02llx\n", pmu_attr
->id
);
1971 static struct pmu power_pmu
= {
1972 .pmu_enable
= power_pmu_enable
,
1973 .pmu_disable
= power_pmu_disable
,
1974 .event_init
= power_pmu_event_init
,
1975 .add
= power_pmu_add
,
1976 .del
= power_pmu_del
,
1977 .start
= power_pmu_start
,
1978 .stop
= power_pmu_stop
,
1979 .read
= power_pmu_read
,
1980 .start_txn
= power_pmu_start_txn
,
1981 .cancel_txn
= power_pmu_cancel_txn
,
1982 .commit_txn
= power_pmu_commit_txn
,
1983 .event_idx
= power_pmu_event_idx
,
1984 .sched_task
= power_pmu_sched_task
,
1988 * A counter has overflowed; update its count and record
1989 * things if requested. Note that interrupts are hard-disabled
1990 * here so there is no possibility of being interrupted.
1992 static void record_and_restart(struct perf_event
*event
, unsigned long val
,
1993 struct pt_regs
*regs
)
1995 u64 period
= event
->hw
.sample_period
;
1996 s64 prev
, delta
, left
;
1999 if (event
->hw
.state
& PERF_HES_STOPPED
) {
2000 write_pmc(event
->hw
.idx
, 0);
2004 /* we don't have to worry about interrupts here */
2005 prev
= local64_read(&event
->hw
.prev_count
);
2006 delta
= check_and_compute_delta(prev
, val
);
2007 local64_add(delta
, &event
->count
);
2010 * See if the total period for this event has expired,
2011 * and update for the next period.
2014 left
= local64_read(&event
->hw
.period_left
) - delta
;
2022 record
= siar_valid(regs
);
2023 event
->hw
.last_period
= event
->hw
.sample_period
;
2025 if (left
< 0x80000000LL
)
2026 val
= 0x80000000LL
- left
;
2029 write_pmc(event
->hw
.idx
, val
);
2030 local64_set(&event
->hw
.prev_count
, val
);
2031 local64_set(&event
->hw
.period_left
, left
);
2032 perf_event_update_userpage(event
);
2035 * Finally record data if requested.
2038 struct perf_sample_data data
;
2040 perf_sample_data_init(&data
, ~0ULL, event
->hw
.last_period
);
2042 if (event
->attr
.sample_type
& PERF_SAMPLE_ADDR
)
2043 perf_get_data_addr(regs
, &data
.addr
);
2045 if (event
->attr
.sample_type
& PERF_SAMPLE_BRANCH_STACK
) {
2046 struct cpu_hw_events
*cpuhw
;
2047 cpuhw
= this_cpu_ptr(&cpu_hw_events
);
2048 power_pmu_bhrb_read(cpuhw
);
2049 data
.br_stack
= &cpuhw
->bhrb_stack
;
2052 if (perf_event_overflow(event
, &data
, regs
))
2053 power_pmu_stop(event
, 0);
2058 * Called from generic code to get the misc flags (i.e. processor mode)
2061 unsigned long perf_misc_flags(struct pt_regs
*regs
)
2063 u32 flags
= perf_get_misc_flags(regs
);
2067 return user_mode(regs
) ? PERF_RECORD_MISC_USER
:
2068 PERF_RECORD_MISC_KERNEL
;
2072 * Called from generic code to get the instruction pointer
2075 unsigned long perf_instruction_pointer(struct pt_regs
*regs
)
2077 bool use_siar
= regs_use_siar(regs
);
2079 if (use_siar
&& siar_valid(regs
))
2080 return mfspr(SPRN_SIAR
) + perf_ip_adjust(regs
);
2082 return 0; // no valid instruction pointer
2087 static bool pmc_overflow_power7(unsigned long val
)
2090 * Events on POWER7 can roll back if a speculative event doesn't
2091 * eventually complete. Unfortunately in some rare cases they will
2092 * raise a performance monitor exception. We need to catch this to
2093 * ensure we reset the PMC. In all cases the PMC will be 256 or less
2094 * cycles from overflow.
2096 * We only do this if the first pass fails to find any overflowing
2097 * PMCs because a user might set a period of less than 256 and we
2098 * don't want to mistakenly reset them.
2100 if ((0x80000000 - val
) <= 256)
2106 static bool pmc_overflow(unsigned long val
)
2115 * Performance monitor interrupt stuff
2117 static void perf_event_interrupt(struct pt_regs
*regs
)
2120 struct cpu_hw_events
*cpuhw
= this_cpu_ptr(&cpu_hw_events
);
2121 struct perf_event
*event
;
2122 unsigned long val
[8];
2126 if (cpuhw
->n_limited
)
2127 freeze_limited_counters(cpuhw
, mfspr(SPRN_PMC5
),
2130 perf_read_regs(regs
);
2132 nmi
= perf_intr_is_nmi(regs
);
2138 /* Read all the PMCs since we'll need them a bunch of times */
2139 for (i
= 0; i
< ppmu
->n_counter
; ++i
)
2140 val
[i
] = read_pmc(i
+ 1);
2142 /* Try to find what caused the IRQ */
2144 for (i
= 0; i
< ppmu
->n_counter
; ++i
) {
2145 if (!pmc_overflow(val
[i
]))
2147 if (is_limited_pmc(i
+ 1))
2148 continue; /* these won't generate IRQs */
2150 * We've found one that's overflowed. For active
2151 * counters we need to log this. For inactive
2152 * counters, we need to reset it anyway
2156 for (j
= 0; j
< cpuhw
->n_events
; ++j
) {
2157 event
= cpuhw
->event
[j
];
2158 if (event
->hw
.idx
== (i
+ 1)) {
2160 record_and_restart(event
, val
[i
], regs
);
2165 /* reset non active counters that have overflowed */
2166 write_pmc(i
+ 1, 0);
2168 if (!found
&& pvr_version_is(PVR_POWER7
)) {
2169 /* check active counters for special buggy p7 overflow */
2170 for (i
= 0; i
< cpuhw
->n_events
; ++i
) {
2171 event
= cpuhw
->event
[i
];
2172 if (!event
->hw
.idx
|| is_limited_pmc(event
->hw
.idx
))
2174 if (pmc_overflow_power7(val
[event
->hw
.idx
- 1])) {
2175 /* event has overflowed in a buggy way*/
2177 record_and_restart(event
,
2178 val
[event
->hw
.idx
- 1],
2183 if (!found
&& !nmi
&& printk_ratelimit())
2184 printk(KERN_WARNING
"Can't find PMC that caused IRQ\n");
2187 * Reset MMCR0 to its normal value. This will set PMXE and
2188 * clear FC (freeze counters) and PMAO (perf mon alert occurred)
2189 * and thus allow interrupts to occur again.
2190 * XXX might want to use MSR.PM to keep the events frozen until
2191 * we get back out of this interrupt.
2193 write_mmcr0(cpuhw
, cpuhw
->mmcr
[0]);
2201 static int power_pmu_prepare_cpu(unsigned int cpu
)
2203 struct cpu_hw_events
*cpuhw
= &per_cpu(cpu_hw_events
, cpu
);
2206 memset(cpuhw
, 0, sizeof(*cpuhw
));
2207 cpuhw
->mmcr
[0] = MMCR0_FC
;
2212 int register_power_pmu(struct power_pmu
*pmu
)
2215 return -EBUSY
; /* something's already registered */
2218 pr_info("%s performance monitor hardware support registered\n",
2221 power_pmu
.attr_groups
= ppmu
->attr_groups
;
2225 * Use FCHV to ignore kernel events if MSR.HV is set.
2227 if (mfmsr() & MSR_HV
)
2228 freeze_events_kernel
= MMCR0_FCHV
;
2229 #endif /* CONFIG_PPC64 */
2231 perf_pmu_register(&power_pmu
, "cpu", PERF_TYPE_RAW
);
2232 cpuhp_setup_state(CPUHP_PERF_POWER
, "perf/powerpc:prepare",
2233 power_pmu_prepare_cpu
, NULL
);