| blob | e9af89ad039c6f0e227878b9de85ea7819cd19d9 |
1 /* Intel PRO/1000 Linux driver
2 * Copyright(c) 1999 - 2015 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
15 *
16 * Contact Information:
17 * Linux NICS <linux.nics@intel.com>
18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
20 */
24 #include <linux/module.h>
25 #include <linux/types.h>
26 #include <linux/init.h>
27 #include <linux/pci.h>
28 #include <linux/vmalloc.h>
29 #include <linux/pagemap.h>
30 #include <linux/delay.h>
31 #include <linux/netdevice.h>
32 #include <linux/interrupt.h>
33 #include <linux/tcp.h>
34 #include <linux/ipv6.h>
35 #include <linux/slab.h>
36 #include <net/checksum.h>
37 #include <net/ip6_checksum.h>
38 #include <linux/ethtool.h>
39 #include <linux/if_vlan.h>
40 #include <linux/cpu.h>
41 #include <linux/smp.h>
42 #include <linux/pm_qos.h>
43 #include <linux/pm_runtime.h>
44 #include <linux/aer.h>
45 #include <linux/prefetch.h>
55 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
74 };
77 u32 ofs;
79 };
82 /* General Registers */
87 /* Interrupt Registers */
90 /* Rx Registers */
106 /* Tx Registers */
123 /* List Terminator */
125 };
127 /**
128 * __ew32_prepare - prepare to write to MAC CSR register on certain parts
129 * @hw: pointer to the HW structure
130 *
131 * When updating the MAC CSR registers, the Manageability Engine (ME) could
132 * be accessing the registers at the same time. Normally, this is handled in
133 * h/w by an arbiter but on some parts there is a bug that acknowledges Host
134 * accesses later than it should which could result in the register to have
135 * an incorrect value. Workaround this by checking the FWSM register which
136 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set
137 * and try again a number of times.
138 **/
140 {
147 }
150 {
155 }
157 /**
158 * e1000_regdump - register printout routine
159 * @hw: pointer to the HW structure
160 * @reginfo: pointer to the register info table
161 **/
163 {
185 }
189 }
193 {
205 }
206 }
207 }
209 /**
210 * e1000e_dump - Print registers, Tx-ring and Rx-ring
211 * @adapter: board private structure
212 **/
214 {
221 __le64 a;
222 __le64 b;
229 __le64 a;
230 __le64 b;
231 __le64 c;
232 __le64 d;
234 u32 staterr;
240 /* Print netdevice Info */
246 }
248 /* Print Registers */
254 }
256 /* Print Tx Ring Summary */
270 /* Print Tx Ring */
276 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
277 *
278 * Legacy Transmit Descriptor
279 * +--------------------------------------------------------------+
280 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
281 * +--------------------------------------------------------------+
282 * 8 | Special | CSS | Status | CMD | CSO | Length |
283 * +--------------------------------------------------------------+
284 * 63 48 47 36 35 32 31 24 23 16 15 0
285 *
286 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
287 * 63 48 47 40 39 32 31 16 15 8 7 0
288 * +----------------------------------------------------------------+
289 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
290 * +----------------------------------------------------------------+
291 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
292 * +----------------------------------------------------------------+
293 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
294 *
295 * Extended Data Descriptor (DTYP=0x1)
296 * +----------------------------------------------------------------+
297 * 0 | Buffer Address [63:0] |
298 * +----------------------------------------------------------------+
299 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
300 * +----------------------------------------------------------------+
301 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
302 */
303 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
304 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
305 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
317 else
322 i,
334 }
336 /* Print Rx Ring Summary */
337 rx_ring_summary:
343 /* Print Rx Ring */
352 /* [Extended] Packet Split Receive Descriptor Format
353 *
354 * +-----------------------------------------------------+
355 * 0 | Buffer Address 0 [63:0] |
356 * +-----------------------------------------------------+
357 * 8 | Buffer Address 1 [63:0] |
358 * +-----------------------------------------------------+
359 * 16 | Buffer Address 2 [63:0] |
360 * +-----------------------------------------------------+
361 * 24 | Buffer Address 3 [63:0] |
362 * +-----------------------------------------------------+
363 */
364 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
365 /* [Extended] Receive Descriptor (Write-Back) Format
366 *
367 * 63 48 47 32 31 13 12 8 7 4 3 0
368 * +------------------------------------------------------+
369 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
370 * | Checksum | Ident | | Queue | | Type |
371 * +------------------------------------------------------+
372 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
373 * +------------------------------------------------------+
374 * 63 48 47 32 31 20 19 0
375 */
376 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
382 staterr =
389 else
393 /* Descriptor Done */
413 buffer_info);
414 }
415 }
419 /* Extended Receive Descriptor (Read) Format
420 *
421 * +-----------------------------------------------------+
422 * 0 | Buffer Address [63:0] |
423 * +-----------------------------------------------------+
424 * 8 | Reserved |
425 * +-----------------------------------------------------+
426 */
427 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
428 /* Extended Receive Descriptor (Write-Back) Format
429 *
430 * 63 48 47 32 31 24 23 4 3 0
431 * +------------------------------------------------------+
432 * | RSS Hash | | | |
433 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
434 * | Packet | IP | | | Type |
435 * | Checksum | Ident | | | |
436 * +------------------------------------------------------+
437 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
438 * +------------------------------------------------------+
439 * 63 48 47 32 31 20 19 0
440 */
455 else
459 /* Descriptor Done */
481 }
482 }
483 }
484 }
486 /**
487 * e1000_desc_unused - calculate if we have unused descriptors
488 **/
490 {
495 }
497 /**
498 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp
499 * @adapter: board private structure
500 * @hwtstamps: time stamp structure to update
501 * @systim: unsigned 64bit system time value.
502 *
503 * Convert the system time value stored in the RX/TXSTMP registers into a
504 * hwtstamp which can be used by the upper level time stamping functions.
505 *
506 * The 'systim_lock' spinlock is used to protect the consistency of the
507 * system time value. This is needed because reading the 64 bit time
508 * value involves reading two 32 bit registers. The first read latches the
509 * value.
510 **/
513 u64 systim)
514 {
515 u64 ns;
524 }
526 /**
527 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp
528 * @adapter: board private structure
529 * @status: descriptor extended error and status field
530 * @skb: particular skb to include time stamp
531 *
532 * If the time stamp is valid, convert it into the timecounter ns value
533 * and store that result into the shhwtstamps structure which is passed
534 * up the network stack.
535 **/
538 {
540 u64 rxstmp;
547 /* The Rx time stamp registers contain the time stamp. No other
548 * received packet will be time stamped until the Rx time stamp
549 * registers are read. Because only one packet can be time stamped
550 * at a time, the register values must belong to this packet and
551 * therefore none of the other additional attributes need to be
552 * compared.
553 */
559 }
561 /**
562 * e1000_receive_skb - helper function to handle Rx indications
563 * @adapter: board private structure
564 * @staterr: descriptor extended error and status field as written by hardware
565 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
566 * @skb: pointer to sk_buff to be indicated to stack
567 **/
571 {
582 }
584 /**
585 * e1000_rx_checksum - Receive Checksum Offload
586 * @adapter: board private structure
587 * @status_err: receive descriptor status and error fields
588 * @csum: receive descriptor csum field
589 * @sk_buff: socket buffer with received data
590 **/
593 {
599 /* Rx checksum disabled */
603 /* Ignore Checksum bit is set */
607 /* TCP/UDP checksum error bit or IP checksum error bit is set */
609 /* let the stack verify checksum errors */
612 }
614 /* TCP/UDP Checksum has not been calculated */
618 /* It must be a TCP or UDP packet with a valid checksum */
621 }
624 {
637 }
638 }
641 {
654 }
655 }
657 /**
658 * e1000_alloc_rx_buffers - Replace used receive buffers
659 * @rx_ring: Rx descriptor ring
660 **/
663 {
681 }
685 /* Better luck next round */
688 }
691 map_skb:
694 DMA_FROM_DEVICE);
699 }
705 /* Force memory writes to complete before letting h/w
706 * know there are new descriptors to fetch. (Only
707 * applicable for weak-ordered memory model archs,
708 * such as IA-64).
709 */
713 else
715 }
716 i++;
720 }
723 }
725 /**
726 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
727 * @rx_ring: Rx descriptor ring
728 **/
731 {
750 /* all unused desc entries get hw null ptr */
754 }
760 }
764 DMA_FROM_DEVICE);
771 }
772 }
773 /* Refresh the desc even if buffer_addrs
774 * didn't change because each write-back
775 * erases this info.
776 */
779 }
782 gfp);
787 }
792 DMA_FROM_DEVICE);
796 /* cleanup skb */
800 }
805 /* Force memory writes to complete before letting h/w
806 * know there are new descriptors to fetch. (Only
807 * applicable for weak-ordered memory model archs,
808 * such as IA-64).
809 */
813 else
815 }
817 i++;
821 }
823 no_buffers:
825 }
827 /**
828 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
829 * @rx_ring: Rx descriptor ring
830 * @cleaned_count: number of buffers to allocate this pass
831 **/
835 {
853 }
857 /* Better luck next round */
860 }
863 check_page:
864 /* allocate a new page if necessary */
870 }
871 }
876 PAGE_SIZE,
877 DMA_FROM_DEVICE);
881 }
882 }
890 }
897 /* Force memory writes to complete before letting h/w
898 * know there are new descriptors to fetch. (Only
899 * applicable for weak-ordered memory model archs,
900 * such as IA-64).
901 */
905 else
907 }
908 }
912 {
915 }
917 /**
918 * e1000_clean_rx_irq - Send received data up the network stack
919 * @rx_ring: Rx descriptor ring
920 *
921 * the return value indicates whether actual cleaning was done, there
922 * is no guarantee that everything was cleaned
923 **/
926 {
957 i++;
966 cleaned_count++;
973 /* !EOP means multiple descriptors were used to store a single
974 * packet, if that's the case we need to toss it. In fact, we
975 * need to toss every packet with the EOP bit clear and the
976 * next frame that _does_ have the EOP bit set, as it is by
977 * definition only a frame fragment
978 */
983 /* All receives must fit into a single buffer */
985 /* recycle */
990 }
994 /* recycle */
997 }
999 /* adjust length to remove Ethernet CRC */
1001 /* If configured to store CRC, don't subtract FCS,
1002 * but keep the FCS bytes out of the total_rx_bytes
1003 * counter
1004 */
1007 else
1009 }
1012 total_rx_packets++;
1014 /* code added for copybreak, this should improve
1015 * performance for small packets with large amounts
1016 * of reassembly being done in the stack
1017 */
1025 NET_IP_ALIGN),
1027 NET_IP_ALIGN));
1028 /* save the skb in buffer_info as good */
1031 }
1032 /* else just continue with the old one */
1033 }
1034 /* end copybreak code */
1037 /* Receive Checksum Offload */
1045 next_desc:
1048 /* return some buffers to hardware, one at a time is too slow */
1051 GFP_ATOMIC);
1053 }
1055 /* use prefetched values */
1060 }
1070 }
1074 {
1081 else
1085 }
1089 }
1091 }
1094 {
1097 print_hang_task);
1105 u16 pci_status;
1111 /* May be block on write-back, flush and detect again
1112 * flush pending descriptor writebacks to memory
1113 */
1115 /* execute the writes immediately */
1117 /* Due to rare timing issues, write to TIDV again to ensure
1118 * the write is successful
1119 */
1121 /* execute the writes immediately */
1125 }
1131 }
1133 /* Real hang detected */
1142 /* detected Hardware unit hang */
1165 /* Suggest workaround for known h/w issue */
1168 }
1170 /**
1171 * e1000e_tx_hwtstamp_work - check for Tx time stamp
1172 * @work: pointer to work struct
1173 *
1174 * This work function polls the TSYNCTXCTL valid bit to determine when a
1175 * timestamp has been taken for the current stored skb. The timestamp must
1176 * be for this skb because only one such packet is allowed in the queue.
1177 */
1179 {
1181 tx_hwtstamp_work);
1186 u64 txstmp;
1203 /* reschedule to check later */
1205 }
1206 }
1208 /**
1209 * e1000_clean_tx_irq - Reclaim resources after transmit completes
1210 * @tx_ring: Tx descriptor ring
1211 *
1212 * the return value indicates whether actual cleaning was done, there
1213 * is no guarantee that everything was cleaned
1214 **/
1216 {
1246 pkts_compl++;
1247 }
1248 }
1253 i++;
1256 }
1262 }
1268 #define TX_WAKE_THRESHOLD 32
1271 /* Make sure that anybody stopping the queue after this
1272 * sees the new next_to_clean.
1273 */
1280 }
1281 }
1284 /* Detect a transmit hang in hardware, this serializes the
1285 * check with the clearing of time_stamp and movement of i
1286 */
1293 else
1295 }
1299 }
1301 /**
1302 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
1303 * @rx_ring: Rx descriptor ring
1304 *
1305 * the return value indicates whether actual cleaning was done, there
1306 * is no guarantee that everything was cleaned
1307 **/
1310 {
1337 /* in the packet split case this is header only */
1340 i++;
1349 cleaned_count++;
1354 /* see !EOP comment in other Rx routine */
1364 }
1370 }
1378 }
1380 /* Good Receive */
1383 {
1384 /* this looks ugly, but it seems compiler issues make
1385 * it more efficient than reusing j
1386 */
1389 /* page alloc/put takes too long and effects small
1390 * packet throughput, so unsplit small packets and
1391 * save the alloc/put only valid in softirq (napi)
1392 * context to call kmap_*
1393 */
1400 /* there is no documentation about how to call
1401 * kmap_atomic, so we can't hold the mapping
1402 * very long
1403 */
1406 PAGE_SIZE,
1407 DMA_FROM_DEVICE);
1413 PAGE_SIZE,
1414 DMA_FROM_DEVICE);
1416 /* remove the CRC */
1420 }
1425 }
1434 DMA_FROM_DEVICE);
1441 }
1443 /* strip the ethernet crc, problem is we're using pages now so
1444 * this whole operation can get a little cpu intensive
1445 */
1449 }
1451 copydone:
1453 total_rx_packets++;
1466 next_desc:
1470 /* return some buffers to hardware, one at a time is too slow */
1473 GFP_ATOMIC);
1475 }
1477 /* use prefetched values */
1482 }
1492 }
1494 /**
1495 * e1000_consume_page - helper function
1496 **/
1498 u16 length)
1499 {
1504 }
1506 /**
1507 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1508 * @adapter: board private structure
1509 *
1510 * the return value indicates whether actual cleaning was done, there
1511 * is no guarantee that everything was cleaned
1512 **/
1515 {
1553 cleaned_count++;
1555 DMA_FROM_DEVICE);
1560 /* errors is only valid for DD + EOP descriptors */
1564 /* recycle both page and skb */
1566 /* an error means any chain goes out the window too */
1571 }
1572 #define rxtop (rx_ring->rx_skb_top)
1574 /* this descriptor is only the beginning (or middle) */
1576 /* this is the beginning of a chain */
1581 /* this is the middle of a chain */
1585 length);
1586 /* re-use the skb, only consumed the page */
1588 }
1593 /* end of the chain */
1597 length);
1598 /* re-use the current skb, we only consumed the
1599 * page
1600 */
1606 /* no chain, got EOP, this buf is the packet
1607 * copybreak to save the put_page/alloc_page
1608 */
1614 length);
1616 /* re-use the page, so don't erase
1617 * buffer_info->page
1618 */
1623 length);
1625 length);
1626 }
1627 }
1628 }
1630 /* Receive Checksum Offload */
1635 /* probably a little skewed due to removing CRC */
1637 total_rx_packets++;
1639 /* eth type trans needs skb->data to point to something */
1644 }
1649 next_desc:
1652 /* return some buffers to hardware, one at a time is too slow */
1655 GFP_ATOMIC);
1657 }
1659 /* use prefetched values */
1664 }
1674 }
1676 /**
1677 * e1000_clean_rx_ring - Free Rx Buffers per Queue
1678 * @rx_ring: Rx descriptor ring
1679 **/
1681 {
1688 /* Free all the Rx ring sk_buffs */
1695 DMA_FROM_DEVICE);
1702 DMA_FROM_DEVICE);
1704 }
1709 }
1714 }
1721 DMA_FROM_DEVICE);
1725 }
1726 }
1728 /* there also may be some cached data from a chained receive */
1732 }
1734 /* Zero out the descriptor ring */
1740 }
1743 {
1746 downshift_task);
1752 }
1754 /**
1755 * e1000_intr_msi - Interrupt Handler
1756 * @irq: interrupt number
1757 * @data: pointer to a network interface device structure
1758 **/
1760 {
1766 /* read ICR disables interrupts using IAM */
1769 /* ICH8 workaround-- Call gig speed drop workaround on cable
1770 * disconnect (LSC) before accessing any PHY registers
1771 */
1776 /* 80003ES2LAN workaround-- For packet buffer work-around on
1777 * link down event; disable receives here in the ISR and reset
1778 * adapter in watchdog
1779 */
1782 /* disable receives */
1787 }
1788 /* guard against interrupt when we're going down */
1791 }
1793 /* Reset on uncorrectable ECC error */
1802 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1804 /* Do the reset outside of interrupt context */
1807 /* return immediately since reset is imminent */
1809 }
1817 }
1820 }
1822 /**
1823 * e1000_intr - Interrupt Handler
1824 * @irq: interrupt number
1825 * @data: pointer to a network interface device structure
1826 **/
1828 {
1837 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
1838 * not set, then the adapter didn't send an interrupt
1839 */
1843 /* Interrupt Auto-Mask...upon reading ICR,
1844 * interrupts are masked. No need for the
1845 * IMC write
1846 */
1850 /* ICH8 workaround-- Call gig speed drop workaround on cable
1851 * disconnect (LSC) before accessing any PHY registers
1852 */
1857 /* 80003ES2LAN workaround--
1858 * For packet buffer work-around on link down event;
1859 * disable receives here in the ISR and
1860 * reset adapter in watchdog
1861 */
1864 /* disable receives */
1868 }
1869 /* guard against interrupt when we're going down */
1872 }
1874 /* Reset on uncorrectable ECC error */
1883 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1885 /* Do the reset outside of interrupt context */
1888 /* return immediately since reset is imminent */
1890 }
1898 }
1901 }
1904 {
1911 /* guard against interrupt when we're going down */
1915 }
1918 }
1921 {
1931 /* Ring was not completely cleaned, so fire another interrupt */
1938 }
1941 {
1946 /* Write the ITR value calculated at the end of the
1947 * previous interrupt.
1948 */
1955 }
1961 }
1963 }
1965 /**
1966 * e1000_configure_msix - Configure MSI-X hardware
1967 *
1968 * e1000_configure_msix sets up the hardware to properly
1969 * generate MSI-X interrupts.
1970 **/
1972 {
1981 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1987 }
1989 /* Configure Rx vector */
1995 else
1999 /* Configure Tx vector */
2001 vector++;
2005 else
2010 /* set vector for Other Causes, e.g. link changes */
2011 vector++;
2016 else
2020 /* Cause Tx interrupts on every write back */
2025 /* enable MSI-X PBA support */
2030 }
2033 {
2041 }
2042 }
2044 /**
2045 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
2046 *
2047 * Attempt to configure interrupts using the best available
2048 * capabilities of the hardware and kernel.
2049 **/
2051 {
2061 msix_entry),
2062 GFP_KERNEL);
2075 }
2076 /* MSI-X failed, so fall through and try MSI */
2079 }
2081 /* Fall through */
2088 }
2089 /* Fall through */
2091 /* Don't do anything; this is the system default */
2093 }
2095 /* store the number of vectors being used */
2097 }
2099 /**
2100 * e1000_request_msix - Initialize MSI-X interrupts
2101 *
2102 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
2103 * kernel.
2104 **/
2106 {
2114 else
2118 netdev);
2124 vector++;
2130 else
2134 netdev);
2140 vector++;
2150 }
2152 /**
2153 * e1000_request_irq - initialize interrupts
2154 *
2155 * Attempts to configure interrupts using the best available
2156 * capabilities of the hardware and kernel.
2157 **/
2159 {
2167 /* fall back to MSI */
2171 }
2178 /* fall back to legacy interrupt */
2181 }
2189 }
2192 {
2199 vector++;
2202 vector++;
2204 /* Other Causes interrupt vector */
2207 }
2210 }
2212 /**
2213 * e1000_irq_disable - Mask off interrupt generation on the NIC
2214 **/
2216 {
2231 }
2232 }
2234 /**
2235 * e1000_irq_enable - Enable default interrupt generation settings
2236 **/
2238 {
2249 }
2251 }
2253 /**
2254 * e1000e_get_hw_control - get control of the h/w from f/w
2255 * @adapter: address of board private structure
2256 *
2257 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2258 * For ASF and Pass Through versions of f/w this means that
2259 * the driver is loaded. For AMT version (only with 82573)
2260 * of the f/w this means that the network i/f is open.
2261 **/
2263 {
2265 u32 ctrl_ext;
2266 u32 swsm;
2268 /* Let firmware know the driver has taken over */
2275 }
2276 }
2278 /**
2279 * e1000e_release_hw_control - release control of the h/w to f/w
2280 * @adapter: address of board private structure
2281 *
2282 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2283 * For ASF and Pass Through versions of f/w this means that the
2284 * driver is no longer loaded. For AMT version (only with 82573) i
2285 * of the f/w this means that the network i/f is closed.
2286 *
2287 **/
2289 {
2291 u32 ctrl_ext;
2292 u32 swsm;
2294 /* Let firmware taken over control of h/w */
2301 }
2302 }
2304 /**
2305 * e1000_alloc_ring_dma - allocate memory for a ring structure
2306 **/
2309 {
2313 GFP_KERNEL);
2318 }
2320 /**
2321 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
2322 * @tx_ring: Tx descriptor ring
2323 *
2324 * Return 0 on success, negative on failure
2325 **/
2327 {
2336 /* round up to nearest 4K */
2348 err:
2352 }
2354 /**
2355 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
2356 * @rx_ring: Rx descriptor ring
2357 *
2358 * Returns 0 on success, negative on failure
2359 **/
2361 {
2375 GFP_KERNEL);
2378 }
2382 /* Round up to nearest 4K */
2396 err_pages:
2400 }
2401 err:
2405 }
2407 /**
2408 * e1000_clean_tx_ring - Free Tx Buffers
2409 * @tx_ring: Tx descriptor ring
2410 **/
2412 {
2421 }
2431 }
2433 /**
2434 * e1000e_free_tx_resources - Free Tx Resources per Queue
2435 * @tx_ring: Tx descriptor ring
2436 *
2437 * Free all transmit software resources
2438 **/
2440 {
2452 }
2454 /**
2455 * e1000e_free_rx_resources - Free Rx Resources
2456 * @rx_ring: Rx descriptor ring
2457 *
2458 * Free all receive software resources
2459 **/
2461 {
2477 }
2479 /**
2480 * e1000_update_itr - update the dynamic ITR value based on statistics
2481 * @adapter: pointer to adapter
2482 * @itr_setting: current adapter->itr
2483 * @packets: the number of packets during this measurement interval
2484 * @bytes: the number of bytes during this measurement interval
2485 *
2486 * Stores a new ITR value based on packets and byte
2487 * counts during the last interrupt. The advantage of per interrupt
2488 * computation is faster updates and more accurate ITR for the current
2489 * traffic pattern. Constants in this function were computed
2490 * based on theoretical maximum wire speed and thresholds were set based
2491 * on testing data as well as attempting to minimize response time
2492 * while increasing bulk throughput. This functionality is controlled
2493 * by the InterruptThrottleRate module parameter.
2494 **/
2496 {
2504 /* handle TSO and jumbo frames */
2512 /* this if handles the TSO accounting */
2523 }
2531 }
2533 }
2536 }
2539 {
2540 u16 current_itr;
2543 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2548 }
2553 }
2558 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2565 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2571 /* counts and packets in update_itr are dependent on these numbers */
2584 }
2586 set_itr_now:
2588 /* this attempts to bias the interrupt rate towards Bulk
2589 * by adding intermediate steps when interrupt rate is
2590 * increasing
2591 */
2598 else
2600 }
2601 }
2603 /**
2604 * e1000e_write_itr - write the ITR value to the appropriate registers
2605 * @adapter: address of board private structure
2606 * @itr: new ITR value to program
2607 *
2608 * e1000e_write_itr determines if the adapter is in MSI-X mode
2609 * and, if so, writes the EITR registers with the ITR value.
2610 * Otherwise, it writes the ITR value into the ITR register.
2611 **/
2613 {
2624 }
2625 }
2627 /**
2628 * e1000_alloc_queues - Allocate memory for all rings
2629 * @adapter: board private structure to initialize
2630 **/
2632 {
2648 err:
2653 }
2655 /**
2656 * e1000e_poll - NAPI Rx polling callback
2657 * @napi: struct associated with this polling callback
2658 * @weight: number of packets driver is allowed to process this poll
2659 **/
2661 {
2663 napi);
2679 /* If weight not fully consumed, exit the polling mode */
2687 else
2689 }
2690 }
2693 }
2697 {
2702 /* don't update vlan cookie if already programmed */
2704 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2708 /* add VID to filter table */
2714 }
2719 }
2723 {
2729 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2731 /* release control to f/w */
2734 }
2736 /* remove VID from filter table */
2742 }
2747 }
2749 /**
2750 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2751 * @adapter: board private structure to initialize
2752 **/
2754 {
2757 u32 rctl;
2760 /* disable VLAN receive filtering */
2769 }
2770 }
2771 }
2773 /**
2774 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2775 * @adapter: board private structure to initialize
2776 **/
2778 {
2780 u32 rctl;
2783 /* enable VLAN receive filtering */
2788 }
2789 }
2791 /**
2792 * e1000e_vlan_strip_disable - helper to disable HW VLAN stripping
2793 * @adapter: board private structure to initialize
2794 **/
2796 {
2798 u32 ctrl;
2800 /* disable VLAN tag insert/strip */
2804 }
2806 /**
2807 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2808 * @adapter: board private structure to initialize
2809 **/
2811 {
2813 u32 ctrl;
2815 /* enable VLAN tag insert/strip */
2819 }
2822 {
2830 }
2834 }
2837 {
2838 u16 vid;
2844 }
2847 {
2856 /* enable receiving management packets to the host. this will probably
2857 * generate destination unreachable messages from the host OS, but
2858 * the packets will be handled on SMBUS
2859 */
2869 /* Check if IPMI pass-through decision filter already exists;
2870 * if so, enable it.
2871 */
2875 /* Ignore filters with anything other than IPMI ports */
2879 /* Enable this decision filter in MANC2H */
2884 }
2889 /* Create new decision filter in an empty filter */
2893 E1000_MDEF_PORT_664));
2895 j++;
2897 }
2902 }
2906 }
2908 /**
2909 * e1000_configure_tx - Configure Transmit Unit after Reset
2910 * @adapter: board private structure
2911 *
2912 * Configure the Tx unit of the MAC after a reset.
2913 **/
2915 {
2918 u64 tdba;
2921 /* Setup the HW Tx Head and Tail descriptor pointers */
2935 else
2938 /* Set the Tx Interrupt Delay register */
2940 /* Tx irq moderation */
2947 E1000_TXDCTL_WTHRESH);
2948 /* set up some performance related parameters to encourage the
2949 * hardware to use the bus more efficiently in bursts, depends
2950 * on the tx_int_delay to be enabled,
2951 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls
2952 * hthresh = 1 ==> prefetch when one or more available
2953 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2954 * BEWARE: this seems to work but should be considered first if
2955 * there are Tx hangs or other Tx related bugs
2956 */
2959 }
2960 /* erratum work around: set txdctl the same for both queues */
2963 /* Program the Transmit Control Register */
2971 /* set the speed mode bit, we'll clear it if we're not at
2972 * gigabit link later
2973 */
2974 #define SPEED_MODE_BIT BIT(21)
2977 }
2979 /* errata: program both queues to unweighted RR */
2987 }
2989 /* Setup Transmit Descriptor Settings for eop descriptor */
2992 /* only set IDE if we are delaying interrupts using the timers */
2996 /* enable Report Status bit */
3003 /* SPT Si errata workaround to avoid data corruption */
3005 u32 reg_val;
3014 }
3015 }
3017 /**
3018 * e1000_setup_rctl - configure the receive control registers
3019 * @adapter: Board private structure
3020 **/
3021 #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
3022 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
3024 {
3029 /* Workaround Si errata on PCHx - configure jumbo frame flow.
3030 * If jumbo frames not set, program related MAC/PHY registers
3031 * to h/w defaults
3032 */
3034 s32 ret_val;
3038 else
3043 }
3045 /* Program MC offset vector base */
3052 /* Do not Store bad packets */
3055 /* Enable Long Packet receive */
3058 else
3061 /* Some systems expect that the CRC is included in SMBUS traffic. The
3062 * hardware strips the CRC before sending to both SMBUS (BMC) and to
3063 * host memory when this is enabled
3064 */
3068 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
3070 u16 phy_data;
3083 }
3085 /* Setup buffer sizes */
3103 }
3105 /* Enable Extended Status in all Receive Descriptors */
3110 /* 82571 and greater support packet-split where the protocol
3111 * header is placed in skb->data and the packet data is
3112 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
3113 * In the case of a non-split, skb->data is linearly filled,
3114 * followed by the page buffers. Therefore, skb->data is
3115 * sized to hold the largest protocol header.
3116 *
3117 * allocations using alloc_page take too long for regular MTU
3118 * so only enable packet split for jumbo frames
3119 *
3120 * Using pages when the page size is greater than 16k wastes
3121 * a lot of memory, since we allocate 3 pages at all times
3122 * per packet.
3123 */
3127 else
3133 /* Enable Packet split descriptors */
3141 /* fall-through */
3144 /* fall-through */
3148 }
3151 }
3153 /* This is useful for sniffing bad packets. */
3155 /* UPE and MPE will be handled by normal PROMISC logic
3156 * in e1000e_set_rx_mode
3157 */
3165 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3166 * and that breaks VLANs.
3167 */
3168 }
3171 /* just started the receive unit, no need to restart */
3173 }
3175 /**
3176 * e1000_configure_rx - Configure Receive Unit after Reset
3177 * @adapter: board private structure
3178 *
3179 * Configure the Rx unit of the MAC after a reset.
3180 **/
3182 {
3185 u64 rdba;
3189 /* this is a 32 byte descriptor */
3202 }
3204 /* disable receives while setting up the descriptors */
3212 /* set the writeback threshold (only takes effect if the RDTR
3213 * is set). set GRAN=1 and write back up to 0x4 worth, and
3214 * enable prefetching of 0x20 Rx descriptors
3215 * granularity = 01
3216 * wthresh = 04,
3217 * hthresh = 04,
3218 * pthresh = 0x20
3219 */
3223 /* override the delay timers for enabling bursting, only if
3224 * the value was not set by the user via module options
3225 */
3230 }
3232 /* set the Receive Delay Timer Register */
3235 /* irq moderation */
3241 /* Auto-Mask interrupts upon ICR access */
3247 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3248 * the Base and Length of the Rx Descriptor Ring
3249 */
3262 else
3265 /* Enable Receive Checksum Offload for TCP and UDP */
3269 else
3273 /* With jumbo frames, excessive C-state transition latencies result
3274 * in dropped transactions.
3275 */
3277 u32 lat =
3285 }
3290 PM_QOS_DEFAULT_VALUE);
3291 }
3293 /* Enable Receives */
3295 }
3297 /**
3298 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3299 * @netdev: network interface device structure
3300 *
3301 * Writes multicast address list to the MTA hash table.
3302 * Returns: -ENOMEM on failure
3303 * 0 on no addresses written
3304 * X on writing X addresses to MTA
3305 */
3307 {
3315 /* nothing to program, so clear mc list */
3318 }
3324 /* update_mc_addr_list expects a packed array of only addresses. */
3333 }
3335 /**
3336 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3337 * @netdev: network interface device structure
3338 *
3339 * Writes unicast address list to the RAR table.
3340 * Returns: -ENOMEM on failure/insufficient address space
3341 * 0 on no addresses written
3342 * X on writing X addresses to the RAR table
3343 **/
3345 {
3353 /* save a rar entry for our hardware address */
3354 rar_entries--;
3356 /* save a rar entry for the LAA workaround */
3358 rar_entries--;
3360 /* return ENOMEM indicating insufficient memory for addresses */
3367 /* write the addresses in reverse order to avoid write
3368 * combining
3369 */
3378 count++;
3379 }
3380 }
3382 /* zero out the remaining RAR entries not used above */
3386 }
3390 }
3392 /**
3393 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
3394 * @netdev: network interface device structure
3395 *
3396 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3397 * address list or the network interface flags are updated. This routine is
3398 * responsible for configuring the hardware for proper unicast, multicast,
3399 * promiscuous mode, and all-multi behavior.
3400 **/
3402 {
3405 u32 rctl;
3410 /* Check for Promiscuous and All Multicast modes */
3413 /* clear the affected bits */
3418 /* Do not hardware filter VLANs in promisc mode */
3426 /* Write addresses to the MTA, if the attempt fails
3427 * then we should just turn on promiscuous mode so
3428 * that we can at least receive multicast traffic
3429 */
3433 }
3435 /* Write addresses to available RAR registers, if there is not
3436 * sufficient space to store all the addresses then enable
3437 * unicast promiscuous mode
3438 */
3442 }
3448 else
3450 }
3453 {
3463 /* Direct all traffic to queue 0 */
3467 /* Disable raw packet checksumming so that RSS hash is placed in
3468 * descriptor on writeback.
3469 */
3476 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3477 E1000_MRQC_RSS_FIELD_IPV6 |
3478 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3479 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3482 }
3484 /**
3485 * e1000e_get_base_timinca - get default SYSTIM time increment attributes
3486 * @adapter: board private structure
3487 * @timinca: pointer to returned time increment attributes
3488 *
3489 * Get attributes for incrementing the System Time Register SYSTIML/H at
3490 * the default base frequency, and set the cyclecounter shift value.
3491 **/
3493 {
3497 /* Make sure clock is enabled on I217/I218/I219 before checking
3498 * the frequency
3499 */
3509 }
3510 }
3516 /* Stable 96MHz frequency */
3522 /* Stable 25MHz frequency */
3527 }
3531 /* Stable 24MHz frequency */
3537 }
3541 /* Stable 25MHz frequency */
3549 }
3555 }
3557 /**
3558 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable
3559 * @adapter: board private structure
3560 *
3561 * Outgoing time stamping can be enabled and disabled. Play nice and
3562 * disable it when requested, although it shouldn't cause any overhead
3563 * when no packet needs it. At most one packet in the queue may be
3564 * marked for time stamping, otherwise it would be impossible to tell
3565 * for sure to which packet the hardware time stamp belongs.
3566 *
3567 * Incoming time stamping has to be configured via the hardware filters.
3568 * Not all combinations are supported, in particular event type has to be
3569 * specified. Matching the kind of event packet is not supported, with the
3570 * exception of "all V2 events regardless of level 2 or 4".
3571 **/
3574 {
3582 u32 regval;
3587 /* flags reserved for future extensions - must be zero */
3599 }
3616 /* Also time stamps V2 L2 Path Delay Request/Response */
3622 /* Also time stamps V2 L2 Path Delay Request/Response. */
3628 /* Hardware cannot filter just V2 L4 Sync messages;
3629 * fall-through to V2 (both L2 and L4) Sync.
3630 */
3632 /* Also time stamps V2 Path Delay Request/Response. */
3639 /* Hardware cannot filter just V2 L4 Delay Request messages;
3640 * fall-through to V2 (both L2 and L4) Delay Request.
3641 */
3643 /* Also time stamps V2 Path Delay Request/Response. */
3651 /* Hardware cannot filter just V2 L4 or L2 Event messages;
3652 * fall-through to all V2 (both L2 and L4) Events.
3653 */
3661 /* For V1, the hardware can only filter Sync messages or
3662 * Delay Request messages but not both so fall-through to
3663 * time stamp all packets.
3664 */
3673 }
3677 /* enable/disable Tx h/w time stamping */
3686 }
3688 /* enable/disable Rx h/w time stamping */
3694 E1000_TSYNCRXCTL_TYPE_MASK)) !=
3696 E1000_TSYNCRXCTL_TYPE_MASK))) {
3699 }
3701 /* L2: define ethertype filter for time stamped packets */
3705 /* define which PTP packets get time stamped */
3708 /* Filter by destination port */
3712 }
3717 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */
3722 }
3724 /**
3725 * e1000_configure - configure the hardware for Rx and Tx
3726 * @adapter: private board structure
3727 **/
3729 {
3744 }
3746 /**
3747 * e1000e_power_up_phy - restore link in case the phy was powered down
3748 * @adapter: address of board private structure
3749 *
3750 * The phy may be powered down to save power and turn off link when the
3751 * driver is unloaded and wake on lan is not enabled (among others)
3752 * *** this routine MUST be followed by a call to e1000e_reset ***
3753 **/
3755 {
3760 }
3762 /**
3763 * e1000_power_down_phy - Power down the PHY
3764 *
3765 * Power down the PHY so no link is implied when interface is down.
3766 * The PHY cannot be powered down if management or WoL is active.
3767 */
3769 {
3772 }
3774 /**
3775 * e1000_flush_tx_ring - remove all descriptors from the tx_ring
3776 *
3777 * We want to clear all pending descriptors from the TX ring.
3778 * zeroing happens when the HW reads the regs. We assign the ring itself as
3779 * the data of the next descriptor. We don't care about the data we are about
3780 * to reset the HW.
3781 */
3783 {
3799 /* flush descriptors to memory before notifying the HW */
3807 }
3809 /**
3810 * e1000_flush_rx_ring - remove all descriptors from the rx_ring
3811 *
3812 * Mark all descriptors in the RX ring as consumed and disable the rx ring
3813 */
3815 {
3825 /* zero the lower 14 bits (prefetch and host thresholds) */
3828 /* update thresholds: prefetch threshold to 31, host threshold to 1
3829 * and make sure the granularity is "descriptors" and not "cache lines"
3830 */
3834 /* momentarily enable the RX ring for the changes to take effect */
3839 }
3841 /**
3842 * e1000_flush_desc_rings - remove all descriptors from the descriptor rings
3843 *
3844 * In i219, the descriptor rings must be emptied before resetting the HW
3845 * or before changing the device state to D3 during runtime (runtime PM).
3846 *
3847 * Failure to do this will cause the HW to enter a unit hang state which can
3848 * only be released by PCI reset on the device
3849 *
3850 */
3853 {
3854 u16 hang_state;
3858 /* First, disable MULR fix in FEXTNVM11 */
3862 /* do nothing if we're not in faulty state, or if the queue is empty */
3869 /* recheck, maybe the fault is caused by the rx ring */
3874 }
3876 /**
3877 * e1000e_systim_reset - reset the timesync registers after a hardware reset
3878 * @adapter: board private structure
3879 *
3880 * When the MAC is reset, all hardware bits for timesync will be reset to the
3881 * default values. This function will restore the settings last in place.
3882 * Since the clock SYSTIME registers are reset, we will simply restore the
3883 * cyclecounter to the kernel real clock time.
3884 **/
3886 {
3890 u32 timinca;
3891 s32 ret_val;
3897 /* restore the previous ptp frequency delta */
3900 /* set the default base frequency if no adjustment possible */
3904 }
3909 ret_val);
3911 }
3913 /* reset the systim ns time counter */
3919 /* restore the previous hwtstamp configuration settings */
3921 }
3923 /**
3924 * e1000e_reset - bring the hardware into a known good state
3925 *
3926 * This function boots the hardware and enables some settings that
3927 * require a configuration cycle of the hardware - those cannot be
3928 * set/changed during runtime. After reset the device needs to be
3929 * properly configured for Rx, Tx etc.
3930 */
3932 {
3938 u16 hwm;
3940 /* reset Packet Buffer Allocation to default */
3944 /* To maintain wire speed transmits, the Tx FIFO should be
3945 * large enough to accommodate two full transmit packets,
3946 * rounded up to the next 1KB and expressed in KB. Likewise,
3947 * the Rx FIFO should be large enough to accommodate at least
3948 * one full receive packet and is similarly rounded up and
3949 * expressed in KB.
3950 */
3952 /* upper 16 bits has Tx packet buffer allocation size in KB */
3954 /* lower 16 bits has Rx packet buffer allocation size in KB */
3956 /* the Tx fifo also stores 16 bytes of information about the Tx
3957 * but don't include ethernet FCS because hardware appends it
3958 */
3963 /* software strips receive CRC, so leave room for it */
3968 /* If current Tx allocation is less than the min Tx FIFO size,
3969 * and the min Tx FIFO size is less than the current Rx FIFO
3970 * allocation, take space away from current Rx allocation
3971 */
3976 /* if short on Rx space, Rx wins and must trump Tx
3977 * adjustment
3978 */
3981 }
3984 }
3986 /* flow control settings
3987 *
3988 * The high water mark must be low enough to fit one full frame
3989 * (or the size used for early receive) above it in the Rx FIFO.
3990 * Set it to the lower of:
3991 * - 90% of the Rx FIFO size, and
3992 * - the full Rx FIFO size minus one full frame
3993 */
3996 else
4010 }
4011 /* fall-through */
4020 /* Workaround PCH LOM adapter hangs with certain network
4021 * loads. If hangs persist, try disabling Tx flow control.
4022 */
4029 }
4042 }
4049 }
4051 /* Alignment of Tx data is on an arbitrary byte boundary with the
4052 * maximum size per Tx descriptor limited only to the transmit
4053 * allocation of the packet buffer minus 96 bytes with an upper
4054 * limit of 24KB due to receive synchronization limitations.
4055 */
4059 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot
4060 * fit in receive buffer.
4061 */
4069 }
4076 }
4077 }
4081 /* Allow time for pending master requests to run */
4084 /* For parts with AMT enabled, let the firmware know
4085 * that the network interface is in control
4086 */
4097 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
4102 /* restore systim and hwtstamp settings */
4105 /* Set EEE advertisement as appropriate */
4107 s32 ret_val;
4108 u16 adv_addr;
4121 }
4128 }
4135 }
4146 /* speed up time to link by disabling smart power down, ignore
4147 * the return value of this function because there is nothing
4148 * different we would do if it failed
4149 */
4153 }
4155 u32 reg;
4157 /* Fextnvm7 @ 0xe4[2] = 1 */
4161 /* Fextnvm9 @ 0x5bb4[13:12] = 11 */
4164 E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS;
4166 }
4168 }
4170 /**
4171 * e1000e_trigger_lsc - trigger an LSC interrupt
4172 * @adapter:
4173 *
4174 * Fire a link status change interrupt to start the watchdog.
4175 **/
4177 {
4182 else
4184 }
4187 {
4188 /* hardware has been reset, we need to reload some things */
4200 }
4203 {
4209 /* flush pending descriptor writebacks to memory */
4213 /* execute the writes immediately */
4216 /* due to rare timing issues, write to TIDV/RDTR again to ensure the
4217 * write is successful
4218 */
4222 /* execute the writes immediately */
4224 }
4228 /**
4229 * e1000e_down - quiesce the device and optionally reset the hardware
4230 * @adapter: board private structure
4231 * @reset: boolean flag to reset the hardware or not
4232 */
4234 {
4239 /* signal that we're down so the interrupt handler does not
4240 * reschedule our watchdog timer
4241 */
4246 /* disable receives in the hardware */
4250 /* flush and sleep below */
4254 /* disable transmits in the hardware */
4259 /* flush both disables and wait for them to finish */
4279 /* Disable Si errata workaround on PCHx for jumbo frame flow */
4290 }
4293 }
4296 {
4303 }
4305 /**
4306 * e1000e_sanitize_systim - sanitize raw cycle counter reads
4307 * @hw: pointer to the HW structure
4308 * @systim: time value read, sanitized and returned
4309 *
4310 * Errata for 82574/82583 possible bad bits read from SYSTIMH/L:
4311 * check to see that the time is incrementing at a reasonable
4312 * rate and is a multiple of incvalue.
4313 **/
4315 {
4317 u64 systim_next;
4318 u32 incvalue;
4323 /* latch SYSTIMH on read of SYSTIML */
4329 /* VMWare users have seen incvalue of zero, don't div / 0 */
4336 }
4339 }
4341 /**
4342 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter)
4343 * @cc: cyclecounter structure
4344 **/
4346 {
4348 cc);
4351 u64 systim;
4352 /* SYSTIMH latching upon SYSTIML read does not work well.
4353 * This means that if SYSTIML overflows after we read it but before
4354 * we read SYSTIMH, the value of SYSTIMH has been incremented and we
4355 * will experience a huge non linear increment in the systime value
4356 * to fix that we test for overflow and if true, we re-read systime.
4357 */
4360 /* Is systimel is so large that overflow is possible? */
4364 /* There was an overflow, read again SYSTIMH, and use
4365 * systimel_2
4366 */
4369 }
4370 }
4378 }
4380 /**
4381 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4382 * @adapter: board private structure to initialize
4383 *
4384 * e1000_sw_init initializes the Adapter private data structure.
4385 * Fields are initialized based on PCI device information and
4386 * OS network device settings (MTU size).
4387 **/
4389 {
4406 /* Setup hardware time stamping cyclecounter */
4411 /* cc.shift set in e1000e_get_base_tininca() */
4415 }
4417 /* Explicitly disable IRQ since the NIC can be in any state. */
4422 }
4424 /**
4425 * e1000_intr_msi_test - Interrupt Handler
4426 * @irq: interrupt number
4427 * @data: pointer to a network interface device structure
4428 **/
4430 {
4439 /* Force memory writes to complete before acknowledging the
4440 * interrupt is handled.
4441 */
4443 }
4446 }
4448 /**
4449 * e1000_test_msi_interrupt - Returns 0 for successful test
4450 * @adapter: board private struct
4451 *
4452 * code flow taken from tg3.c
4453 **/
4455 {
4460 /* poll_enable hasn't been called yet, so don't need disable */
4461 /* clear any pending events */
4464 /* free the real vector and request a test handler */
4468 /* Assume that the test fails, if it succeeds then the test
4469 * MSI irq handler will unset this flag
4470 */
4482 }
4484 /* Force memory writes to complete before enabling and firing an
4485 * interrupt.
4486 */
4491 /* fire an unusual interrupt on the test handler */
4505 }
4510 msi_test_failed:
4513 }
4515 /**
4516 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
4517 * @adapter: board private struct
4518 *
4519 * code flow taken from tg3.c, called with e1000 interrupts disabled.
4520 **/
4522 {
4524 u16 pci_cmd;
4529 /* disable SERR in case the MSI write causes a master abort */
4537 /* re-enable SERR */
4542 }
4545 }
4547 /**
4548 * e1000e_open - Called when a network interface is made active
4549 * @netdev: network interface device structure
4550 *
4551 * Returns 0 on success, negative value on failure
4552 *
4553 * The open entry point is called when a network interface is made
4554 * active by the system (IFF_UP). At this point all resources needed
4555 * for transmit and receive operations are allocated, the interrupt
4556 * handler is registered with the OS, the watchdog timer is started,
4557 * and the stack is notified that the interface is ready.
4558 **/
4560 {
4566 /* disallow open during test */
4574 /* allocate transmit descriptors */
4579 /* allocate receive descriptors */
4584 /* If AMT is enabled, let the firmware know that the network
4585 * interface is now open and reset the part to a known state.
4586 */
4590 }
4598 /* DMA latency requirement to workaround jumbo issue */
4600 PM_QOS_DEFAULT_VALUE);
4602 /* before we allocate an interrupt, we must be ready to handle it.
4603 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4604 * as soon as we call pci_request_irq, so we have to setup our
4605 * clean_rx handler before we do so.
4606 */
4613 /* Work around PCIe errata with MSI interrupts causing some chipsets to
4614 * ignore e1000e MSI messages, which means we need to test our MSI
4615 * interrupt now
4616 */
4622 }
4623 }
4625 /* From here on the code is the same as e1000e_up() */
4642 err_req_irq:
4647 err_setup_rx:
4649 err_setup_tx:
4654 }
4656 /**
4657 * e1000e_close - Disables a network interface
4658 * @netdev: network interface device structure
4659 *
4660 * Returns 0, this is not allowed to fail
4661 *
4662 * The close entry point is called when an interface is de-activated
4663 * by the OS. The hardware is still under the drivers control, but
4664 * needs to be disabled. A global MAC reset is issued to stop the
4665 * hardware, and all transmit and receive resources are freed.
4666 **/
4668 {
4684 /* Link status message must follow this format */
4686 }
4693 /* kill manageability vlan ID if supported, but not if a vlan with
4694 * the same ID is registered on the host OS (let 8021q kill it)
4695 */
4700 /* If AMT is enabled, let the firmware know that the network
4701 * interface is now closed
4702 */
4712 }
4714 /**
4715 * e1000_set_mac - Change the Ethernet Address of the NIC
4716 * @netdev: network interface device structure
4717 * @p: pointer to an address structure
4718 *
4719 * Returns 0 on success, negative on failure
4720 **/
4722 {
4736 /* activate the work around */
4739 /* Hold a copy of the LAA in RAR[14] This is done so that
4740 * between the time RAR[0] gets clobbered and the time it
4741 * gets fixed (in e1000_watchdog), the actual LAA is in one
4742 * of the RARs and no incoming packets directed to this port
4743 * are dropped. Eventually the LAA will be in RAR[0] and
4744 * RAR[14]
4745 */
4748 }
4751 }
4753 /**
4754 * e1000e_update_phy_task - work thread to update phy
4755 * @work: pointer to our work struct
4756 *
4757 * this worker thread exists because we must acquire a
4758 * semaphore to read the phy, which we could msleep while
4759 * waiting for it, and we can't msleep in a timer.
4760 **/
4762 {
4765 update_phy_task);
4773 /* Enable EEE on 82579 after link up */
4776 }
4778 /**
4779 * e1000_update_phy_info - timre call-back to update PHY info
4780 * @data: pointer to adapter cast into an unsigned long
4781 *
4782 * Need to wait a few seconds after link up to get diagnostic information from
4783 * the phy
4784 **/
4786 {
4793 }
4795 /**
4796 * e1000e_update_phy_stats - Update the PHY statistics counters
4797 * @adapter: board private structure
4798 *
4799 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
4800 **/
4802 {
4804 s32 ret_val;
4805 u16 phy_data;
4811 /* A page set is expensive so check if already on desired page.
4812 * If not, set to the page with the PHY status registers.
4813 */
4824 }
4826 /* Single Collision Count */
4832 /* Excessive Collision Count */
4838 /* Multiple Collision Count */
4844 /* Late Collision Count */
4850 /* Collision Count - also used for adaptive IFS */
4856 /* Defer Count */
4862 /* Transmit with no CRS */
4868 release:
4870 }
4872 /**
4873 * e1000e_update_stats - Update the board statistics counters
4874 * @adapter: board private structure
4875 **/
4877 {
4882 /* Prevent stats update while adapter is being reset, or if the pci
4883 * connection is down.
4884 */
4900 /* Half-duplex statistics */
4916 }
4918 }
4933 /* used for adaptive IFS */
4944 /* Fill out the OS statistics structure */
4948 /* Rx Errors */
4950 /* RLEC on some newer hardware can be incorrect so build
4951 * our own version based on RUC and ROC
4952 */
4962 /* Tx Errors */
4968 /* Tx Dropped needs to be maintained elsewhere */
4970 /* Management Stats */
4975 /* Correctable ECC Errors */
4984 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
4985 }
4986 }
4988 /**
4989 * e1000_phy_read_status - Update the PHY register status snapshot
4990 * @adapter: board private structure
4991 **/
4993 {
5013 /* Do not read PHY registers if link is not up
5014 * Set values to typical power-on defaults
5015 */
5019 BMSR_ERCAP);
5027 }
5028 }
5031 {
5035 /* Link status message must follow this format for user tools */
5042 }
5045 {
5050 /* get_link_status is set on LSC (link status) interrupt or
5051 * Rx sequence error interrupt. get_link_status will stay
5052 * false until the check_for_link establishes link
5053 * for copper adapters ONLY
5054 */
5062 }
5075 }
5079 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
5081 }
5084 }
5087 {
5088 /* make sure the receive unit is started */
5096 }
5097 }
5100 {
5103 /* With 82574 controllers, PHY needs to be checked periodically
5104 * for hung state and reset, if two calls return true
5105 */
5108 else
5115 }
5116 }
5118 /**
5119 * e1000_watchdog - Timer Call-back
5120 * @data: pointer to adapter cast into an unsigned long
5121 **/
5123 {
5126 /* Do the rest outside of interrupt context */
5129 /* TODO: make this use queue_delayed_work() */
5130 }
5133 {
5136 watchdog_task);
5149 /* Cancel scheduled suspend requests. */
5154 }
5164 /* Cancel scheduled suspend requests. */
5167 /* update snapshot of PHY registers on LSC */
5174 /* check if SmartSpeed worked */
5180 /* On supported PHYs, check for duplex mismatch only
5181 * if link has autonegotiated at 10/100 half
5182 */
5189 u16 autoneg_exp;
5194 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
5195 }
5197 /* adjust timeout factor according to speed/duplex */
5208 }
5210 /* workaround: re-program speed mode bit after
5211 * link-up event
5212 */
5215 u32 tarc0;
5220 }
5222 /* disable TSO for pcie and 10/100 speeds, to avoid
5223 * some hardware issues
5224 */
5238 /* oops */
5240 }
5241 }
5243 /* enable transmits in the hardware, need to do this
5244 * after setting TARC(0)
5245 */
5250 /* Perform any post-link-up configuration before
5251 * reporting link up.
5252 */
5261 }
5266 /* Link status message must follow this format */
5273 /* 8000ES2LAN requires a Rx packet buffer work-around
5274 * on link down event; reset the controller to flush
5275 * the Rx packet buffer.
5276 */
5279 else
5281 LINK_TIMEOUT);
5282 }
5283 }
5285 link_up:
5300 /* If the link is lost the controller stops DMA, but
5301 * if there is queued Tx work it cannot be done. So
5302 * reset the controller to flush the Tx packet buffers.
5303 */
5308 /* If reset is necessary, do it outside of interrupt context. */
5311 /* return immediately since reset is imminent */
5313 }
5317 /* Simple mode for Interrupt Throttle Rate (ITR) */
5319 /* Symmetric Tx/Rx gets a reduced ITR=2000;
5320 * Total asymmetrical Tx or Rx gets ITR=8000;
5321 * everyone else is between 2000-8000.
5322 */
5330 }
5332 /* Cause software interrupt to ensure Rx ring is cleaned */
5335 else
5338 /* flush pending descriptors to memory before detecting Tx hang */
5341 /* Force detection of hung controller every watchdog period */
5344 /* With 82571 controllers, LAA may be overwritten due to controller
5345 * reset from the other port. Set the appropriate LAA in RAR[0]
5346 */
5353 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */
5361 }
5362 }
5364 /* Reset the timer */
5368 }
5370 #define E1000_TX_FLAGS_CSUM 0x00000001
5371 #define E1000_TX_FLAGS_VLAN 0x00000002
5372 #define E1000_TX_FLAGS_TSO 0x00000004
5373 #define E1000_TX_FLAGS_IPV4 0x00000008
5374 #define E1000_TX_FLAGS_NO_FCS 0x00000010
5375 #define E1000_TX_FLAGS_HWTSTAMP 0x00000020
5376 #define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
5377 #define E1000_TX_FLAGS_VLAN_SHIFT 16
5380 __be16 protocol)
5381 {
5413 }
5439 i++;
5445 }
5448 __be16 protocol)
5449 {
5454 u8 css;
5466 /* XXX not handling all IPV6 headers */
5475 }
5493 i++;
5499 }
5504 {
5530 count++;
5533 i++;
5536 }
5537 }
5547 i++;
5559 DMA_TO_DEVICE);
5566 count++;
5567 }
5568 }
5571 /* multiply data chunks by size of headers */
5581 dma_error:
5585 count--;
5590 i--;
5593 }
5596 }
5599 {
5608 E1000_TXD_CMD_TSE;
5613 }
5618 }
5623 }
5631 }
5643 i++;
5650 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
5654 /* Force memory writes to complete before letting h/w
5655 * know there are new descriptors to fetch. (Only
5656 * applicable for weak-ordered memory model archs,
5657 * such as IA-64).
5658 */
5662 }
5664 #define MINIMUM_DHCP_PACKET_SIZE 282
5667 {
5674 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
5683 {
5697 }
5700 }
5703 {
5707 /* Herbert's original patch had:
5708 * smp_mb__after_netif_stop_queue();
5709 * but since that doesn't exist yet, just open code it.
5710 */
5713 /* We need to check again in a case another CPU has just
5714 * made room available.
5715 */
5719 /* A reprieve! */
5723 }
5726 {
5732 }
5736 {
5752 }
5757 }
5759 /* The minimum packet size with TCTL.PSP set is 17 bytes so
5760 * pad skb in order to meet this minimum size requirement
5761 */
5767 u8 hdr_len;
5769 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
5770 * points to just header, pull a few bytes of payload from
5771 * frags into skb->data
5772 */
5774 /* we do this workaround for ES2LAN, but it is un-necessary,
5775 * avoiding it could save a lot of cycles
5776 */
5785 }
5787 }
5788 }
5790 /* reserve a descriptor for the offload context */
5792 count++;
5793 count++;
5805 /* need: count + 2 desc gap to keep tail from touching
5806 * head, otherwise try next time
5807 */
5814 E1000_TX_FLAGS_VLAN_SHIFT);
5815 }
5823 }
5830 /* Old method was to assume IPv4 packet by default if TSO was enabled.
5831 * 82571 hardware supports TSO capabilities for IPv6 as well...
5832 * no longer assume, we must.
5833 */
5840 /* if count is 0 then mapping error has occurred */
5842 nr_frags);
5854 }
5858 /* Make sure there is space in the ring for the next send. */
5869 else
5872 /* we need this if more than one processor can write
5873 * to our tail at a time, it synchronizes IO on
5874 *IA64/Altix systems
5875 */
5877 }
5882 }
5885 }
5887 /**
5888 * e1000_tx_timeout - Respond to a Tx Hang
5889 * @netdev: network interface device structure
5890 **/
5892 {
5895 /* Do the reset outside of interrupt context */
5898 }
5901 {
5905 /* don't run the task if already down */
5912 }
5914 }
5916 /**
5917 * e1000_get_stats64 - Get System Network Statistics
5918 * @netdev: network interface device structure
5919 * @stats: rtnl_link_stats64 pointer
5920 *
5921 * Returns the address of the device statistics structure.
5922 **/
5925 {
5930 /* Fill out the OS statistics structure */
5938 /* Rx Errors */
5940 /* RLEC on some newer hardware can be incorrect so build
5941 * our own version based on RUC and ROC
5942 */
5951 /* Tx Errors */
5957 /* Tx Dropped needs to be maintained elsewhere */
5960 }
5962 /**
5963 * e1000_change_mtu - Change the Maximum Transfer Unit
5964 * @netdev: network interface device structure
5965 * @new_mtu: new value for maximum frame size
5966 *
5967 * Returns 0 on success, negative on failure
5968 **/
5970 {
5974 /* Jumbo frame support */
5979 }
5981 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
5987 }
5991 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
6001 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
6002 * means we reserve 2 more, this pushes us to allocate from the next
6003 * larger slab size.
6004 * i.e. RXBUFFER_2048 --> size-4096 slab
6005 * However with the new *_jumbo_rx* routines, jumbo receives will use
6006 * fragmented skbs
6007 */
6011 else
6014 /* adjust allocation if LPE protects us, and we aren't using SBP */
6020 else
6028 }
6032 {
6079 }
6084 }
6086 }
6088 /**
6089 * e1000e_hwtstamp_ioctl - control hardware time stamping
6090 * @netdev: network interface device structure
6091 * @ifreq: interface request
6092 *
6093 * Outgoing time stamping can be enabled and disabled. Play nice and
6094 * disable it when requested, although it shouldn't cause any overhead
6095 * when no packet needs it. At most one packet in the queue may be
6096 * marked for time stamping, otherwise it would be impossible to tell
6097 * for sure to which packet the hardware time stamp belongs.
6098 *
6099 * Incoming time stamping has to be configured via the hardware filters.
6100 * Not all combinations are supported, in particular event type has to be
6101 * specified. Matching the kind of event packet is not supported, with the
6102 * exception of "all V2 events regardless of level 2 or 4".
6103 **/
6105 {
6124 /* With V2 type filters which specify a Sync or Delay Request,
6125 * Path Delay Request/Response messages are also time stamped
6126 * by hardware so notify the caller the requested packets plus
6127 * some others are time stamped.
6128 */
6133 }
6137 }
6140 {
6145 }
6148 {
6160 }
6161 }
6164 {
6170 /* copy MAC RARs to PHY RARs */
6177 }
6179 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
6184 /* copy MAC MTA to PHY MTA - only needed for pchlan */
6191 }
6193 /* configure PHY Rx Control register */
6217 /* enable PHY wakeup in MAC register */
6222 /* configure and enable PHY wakeup in PHY registers */
6226 /* activate PHY wakeup */
6231 release:
6235 }
6238 {
6242 u32 ret_val;
6255 fl_out:
6257 }
6260 {
6274 /* Quiesce the device without resetting the hardware */
6277 }
6280 /* Allow time for pending master requests to run */
6284 }
6287 {
6292 /* Runtime suspend should only enable wakeup for link changes */
6304 /* turn on all-multi mode if wake on multicast is enabled */
6309 }
6319 e1000_media_type_internal_serdes) {
6320 /* keep the laser running in D3 */
6324 }
6333 /* enable wakeup by the PHY */
6338 /* enable wakeup by the MAC */
6341 }
6347 }
6354 /* ULP does not support wake from unicast, multicast
6355 * or broadcast.
6356 */
6361 }
6363 /* Ensure that the appropriate bits are set in LPI_CTRL
6364 * for EEE in Sx
6365 */
6377 I82579_EEE_100_SUPPORTED)
6381 I82579_EEE_1000_SUPPORTED)
6385 lpi_ctrl);
6386 }
6387 }
6389 }
6391 /* Release control of h/w to f/w. If f/w is AMT enabled, this
6392 * would have already happened in close and is redundant.
6393 */
6398 /* The pci-e switch on some quad port adapters will report a
6399 * correctable error when the MAC transitions from D0 to D3. To
6400 * prevent this we need to mask off the correctable errors on the
6401 * downstream port of the pci-e switch.
6402 *
6403 * We don't have the associated upstream bridge while assigning
6404 * the PCI device into guest. For example, the KVM on power is
6405 * one of the cases.
6406 */
6409 u16 devctl;
6422 }
6425 }
6427 /**
6428 * __e1000e_disable_aspm - Disable ASPM states
6429 * @pdev: pointer to PCI device struct
6430 * @state: bit-mask of ASPM states to disable
6431 * @locked: indication if this context holds pci_bus_sem locked.
6432 *
6433 * Some devices *must* have certain ASPM states disabled per hardware errata.
6434 **/
6436 {
6445 /* fall-through - can't have L1 without L0s */
6451 }
6460 }
6462 /* Nothing to do if the ASPM states to be disabled already are */
6473 #ifdef CONFIG_PCIEASPM
6476 else
6479 /* Double-check ASPM control. If not disabled by the above, the
6480 * BIOS is preventing that from happening (or CONFIG_PCIEASPM is
6481 * not enabled); override by writing PCI config space directly.
6482 */
6488 #endif
6490 /* Both device and parent should have the same ASPM setting.
6491 * Disable ASPM in downstream component first and then upstream.
6492 */
6497 aspm_dis_mask);
6498 }
6500 /**
6501 * e1000e_disable_aspm - Disable ASPM states.
6502 * @pdev: pointer to PCI device struct
6503 * @state: bit-mask of ASPM states to disable
6504 *
6505 * This function acquires the pci_bus_sem!
6506 * Some devices *must* have certain ASPM states disabled per hardware errata.
6507 **/
6509 {
6511 }
6513 /**
6514 * e1000e_disable_aspm_locked Disable ASPM states.
6515 * @pdev: pointer to PCI device struct
6516 * @state: bit-mask of ASPM states to disable
6517 *
6518 * This function must be called with pci_bus_sem acquired!
6519 * Some devices *must* have certain ASPM states disabled per hardware errata.
6520 **/
6522 {
6524 }
6526 #ifdef CONFIG_PM
6528 {
6548 /* report the system wakeup cause from S3/S4 */
6550 u16 phy_data;
6561 }
6574 }
6576 }
6582 /* If the controller has AMT, do not set DRV_LOAD until the interface
6583 * is up. For all other cases, let the f/w know that the h/w is now
6584 * under the control of the driver.
6585 */
6590 }
6592 #ifdef CONFIG_PM_SLEEP
6594 {
6606 }
6611 }
6614 {
6622 }
6625 {
6634 }
6638 {
6642 u16 eee_lp;
6649 }
6652 }
6655 {
6669 }
6672 {
6685 /* Down the device without resetting the hardware */
6687 }
6692 }
6695 }
6699 {
6705 }
6707 #ifdef CONFIG_NET_POLL_CONTROLLER
6710 {
6723 vector++;
6729 vector++;
6734 }
6737 }
6739 /**
6740 * e1000_netpoll
6741 * @netdev: network interface device structure
6742 *
6743 * Polling 'interrupt' - used by things like netconsole to send skbs
6744 * without having to re-enable interrupts. It's not called while
6745 * the interrupt routine is executing.
6746 */
6748 {
6765 }
6766 }
6767 #endif
6769 /**
6770 * e1000_io_error_detected - called when PCI error is detected
6771 * @pdev: Pointer to PCI device
6772 * @state: The current pci connection state
6773 *
6774 * This function is called after a PCI bus error affecting
6775 * this device has been detected.
6776 */
6778 pci_channel_state_t state)
6779 {
6792 /* Request a slot slot reset. */
6794 }
6796 /**
6797 * e1000_io_slot_reset - called after the pci bus has been reset.
6798 * @pdev: Pointer to PCI device
6799 *
6800 * Restart the card from scratch, as if from a cold-boot. Implementation
6801 * resembles the first-half of the e1000e_pm_resume routine.
6802 */
6804 {
6810 pci_ers_result_t result;
6835 }
6840 }
6842 /**
6843 * e1000_io_resume - called when traffic can start flowing again.
6844 * @pdev: Pointer to PCI device
6845 *
6846 * This callback is called when the error recovery driver tells us that
6847 * its OK to resume normal operation. Implementation resembles the
6848 * second-half of the e1000e_pm_resume routine.
6849 */
6851 {
6862 /* If the controller has AMT, do not set DRV_LOAD until the interface
6863 * is up. For all other cases, let the f/w know that the h/w is now
6864 * under the control of the driver.
6865 */
6868 }
6871 {
6874 u32 ret_val;
6877 /* print bus type/speed/width info */
6879 /* bus width */
6882 /* MAC address */
6887 E1000_PBANUM_LENGTH);
6892 }
6895 {
6906 /* Deep Smart Power Down (DSPD) */
6909 }
6910 }
6913 netdev_features_t features)
6914 {
6918 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
6922 /* Since there is no support for separate Rx/Tx vlan accel
6923 * enable/disable make sure Tx flag is always in same state as Rx.
6924 */
6927 else
6931 }
6934 netdev_features_t features)
6935 {
6944 NETIF_F_RXALL)))
6951 /* We need to take it back to defaults, which might mean
6952 * stripping is still disabled at the adapter level.
6953 */
6956 else
6958 }
6959 }
6965 else
6969 }
6985 #ifdef CONFIG_NET_POLL_CONTROLLER
6987 #endif
6991 };
6993 /**
6994 * e1000_probe - Device Initialization Routine
6995 * @pdev: PCI device information struct
6996 * @ent: entry in e1000_pci_tbl
6997 *
6998 * Returns 0 on success, negative on failure
6999 *
7000 * e1000_probe initializes an adapter identified by a pci_dev structure.
7001 * The OS initialization, configuring of the adapter private structure,
7002 * and a hardware reset occur.
7003 **/
7005 {
7040 }
7041 }
7045 e1000e_driver_name);
7049 /* AER (Advanced Error Reporting) hooks */
7053 /* PCI config space info */
7097 }
7099 /* Set default EEE advertisement */
7103 /* construct the net_device struct */
7117 /* setup adapter struct */
7139 /* Copper options */
7144 }
7150 /* Set initial default active device features */
7152 NETIF_F_HW_VLAN_CTAG_RX |
7153 NETIF_F_HW_VLAN_CTAG_TX |
7154 NETIF_F_TSO |
7155 NETIF_F_TSO6 |
7156 NETIF_F_RXHASH |
7157 NETIF_F_RXCSUM |
7158 NETIF_F_HW_CSUM);
7160 /* Set user-changeable features (subset of all device features) */
7170 NETIF_F_TSO |
7171 NETIF_F_TSO6 |
7172 NETIF_F_HW_CSUM);
7179 }
7181 /* MTU range: 68 - max_hw_frame_size */
7189 /* before reading the NVM, reset the controller to
7190 * put the device in a known good starting state
7191 */
7194 /* systems with ASPM and others may see the checksum fail on the first
7195 * attempt. Let's give it a few tries
7196 */
7204 }
7205 }
7209 /* copy the MAC address */
7221 }
7237 /* Initialize link parameters. User can change them with ethtool */
7244 /* Initial Wake on LAN setting - If APM wake is enabled in
7245 * the EEPROM, enable the ACPI Magic Packet filter
7246 */
7248 /* APME bit in EEPROM is mapped to WUC.APME */
7258 NVM_INIT_CONTROL3_PORT_B,
7260 else
7262 NVM_INIT_CONTROL3_PORT_A,
7264 }
7266 /* fetch WoL from EEPROM */
7272 /* now that we have the eeprom settings, apply the special cases
7273 * where the eeprom may be wrong or the board simply won't support
7274 * wake on lan on a particular port
7275 */
7279 /* initialize the wol settings based on the eeprom settings */
7282 /* make sure adapter isn't asleep if manageability is enabled */
7287 /* save off EEPROM version number */
7293 }
7295 /* init PTP hardware clock */
7298 /* reset the hardware with the new settings */
7301 /* If the controller has AMT, do not set DRV_LOAD until the interface
7302 * is up. For all other cases, let the f/w know that the h/w is now
7303 * under the control of the driver.
7304 */
7313 /* carrier off reporting is important to ethtool even BEFORE open */
7323 err_register:
7326 err_eeprom:
7329 err_hw_init:
7332 err_sw_init:
7336 err_flashmap:
7338 err_ioremap:
7340 err_alloc_etherdev:
7342 err_pci_reg:
7343 err_dma:
7346 }
7348 /**
7349 * e1000_remove - Device Removal Routine
7350 * @pdev: PCI device information struct
7351 *
7352 * e1000_remove is called by the PCI subsystem to alert the driver
7353 * that it should release a PCI device. The could be caused by a
7354 * Hot-Plug event, or because the driver is going to be removed from
7355 * memory.
7356 **/
7358 {
7365 /* The timers may be rescheduled, so explicitly disable them
7366 * from being rescheduled.
7367 */
7384 }
7385 }
7387 /* Don't lie to e1000_close() down the road. */
7395 /* Release control of h/w to f/w. If f/w is AMT enabled, this
7396 * would have already happened in close and is redundant.
7397 */
7412 /* AER disable */
7416 }
7418 /* PCI Error Recovery (ERS) */
7423 };
7430 board_82571 },
7451 board_80003es2lan },
7453 board_80003es2lan },
7455 board_80003es2lan },
7457 board_80003es2lan },
7513 };
7517 #ifdef CONFIG_PM_SLEEP
7524 #endif
7526 e1000e_pm_runtime_idle)
7527 };
7529 /* PCI Device API Driver */
7537 },
7540 };
7542 /**
7543 * e1000_init_module - Driver Registration Routine
7544 *
7545 * e1000_init_module is the first routine called when the driver is
7546 * loaded. All it does is register with the PCI subsystem.
7547 **/
7549 {
7551 e1000e_driver_version);
7555 }
7558 /**
7559 * e1000_exit_module - Driver Exit Cleanup Routine
7560 *
7561 * e1000_exit_module is called just before the driver is removed
7562 * from memory.
7563 **/
7565 {
7567 }
7575 /* netdev.c */