drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c

   1 /*
   2  * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
   3  * DWC Ether MAC version 4.00  has been used for developing this code.
   4  *
   5  * This only implements the mac core functions for this chip.
   6  *
   7  * Copyright (C) 2015  STMicroelectronics Ltd
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms and conditions of the GNU General Public License,
  11  * version 2, as published by the Free Software Foundation.
  12  *
  13  * Author: Alexandre Torgue <alexandre.torgue@st.com>
  14  */
  15
  16 #include <linux/crc32.h>
  17 #include <linux/slab.h>
  18 #include <linux/ethtool.h>
  19 #include <linux/io.h>
  20 #include "stmmac_pcs.h"
  21 #include "dwmac4.h"
  22
  23 static void dwmac4_core_init(struct mac_device_info *hw, int mtu)
  24 {
  25         void __iomem *ioaddr = hw->pcsr;
  26         u32 value = readl(ioaddr + GMAC_CONFIG);
  27
  28         value |= GMAC_CORE_INIT;
  29
  30         if (mtu > 1500)
  31                 value |= GMAC_CONFIG_2K;
  32         if (mtu > 2000)
  33                 value |= GMAC_CONFIG_JE;
  34
  35         if (hw->ps) {
  36                 value |= GMAC_CONFIG_TE;
  37
  38                 if (hw->ps == SPEED_1000) {
  39                         value &= ~GMAC_CONFIG_PS;
  40                 } else {
  41                         value |= GMAC_CONFIG_PS;
  42
  43                         if (hw->ps == SPEED_10)
  44                                 value &= ~GMAC_CONFIG_FES;
  45                         else
  46                                 value |= GMAC_CONFIG_FES;
  47                 }
  48         }
  49
  50         writel(value, ioaddr + GMAC_CONFIG);
  51
  52         /* Mask GMAC interrupts */
  53         value = GMAC_INT_DEFAULT_MASK;
  54         if (hw->pmt)
  55                 value |= GMAC_INT_PMT_EN;
  56         if (hw->pcs)
  57                 value |= GMAC_PCS_IRQ_DEFAULT;
  58
  59         writel(value, ioaddr + GMAC_INT_EN);
  60 }
  61
  62 static void dwmac4_rx_queue_enable(struct mac_device_info *hw, u32 queue)
  63 {
  64         void __iomem *ioaddr = hw->pcsr;
  65         u32 value = readl(ioaddr + GMAC_RXQ_CTRL0);
  66
  67         value &= GMAC_RX_QUEUE_CLEAR(queue);
  68         value |= GMAC_RX_AV_QUEUE_ENABLE(queue);
  69
  70         writel(value, ioaddr + GMAC_RXQ_CTRL0);
  71 }
  72
  73 static void dwmac4_dump_regs(struct mac_device_info *hw, u32 *reg_space)
  74 {
  75         void __iomem *ioaddr = hw->pcsr;
  76         int i;
  77
  78         for (i = 0; i < GMAC_REG_NUM; i++)
  79                 reg_space[i] = readl(ioaddr + i * 4);
  80 }
  81
  82 static int dwmac4_rx_ipc_enable(struct mac_device_info *hw)
  83 {
  84         void __iomem *ioaddr = hw->pcsr;
  85         u32 value = readl(ioaddr + GMAC_CONFIG);
  86
  87         if (hw->rx_csum)
  88                 value |= GMAC_CONFIG_IPC;
  89         else
  90                 value &= ~GMAC_CONFIG_IPC;
  91
  92         writel(value, ioaddr + GMAC_CONFIG);
  93
  94         value = readl(ioaddr + GMAC_CONFIG);
  95
  96         return !!(value & GMAC_CONFIG_IPC);
  97 }
  98
  99 static void dwmac4_pmt(struct mac_device_info *hw, unsigned long mode)
 100 {
 101         void __iomem *ioaddr = hw->pcsr;
 102         unsigned int pmt = 0;
 103
 104         if (mode & WAKE_MAGIC) {
 105                 pr_debug("GMAC: WOL Magic frame\n");
 106                 pmt |= power_down | magic_pkt_en;
 107         }
 108         if (mode & WAKE_UCAST) {
 109                 pr_debug("GMAC: WOL on global unicast\n");
 110                 pmt |= power_down | global_unicast | wake_up_frame_en;
 111         }
 112
 113         writel(pmt, ioaddr + GMAC_PMT);
 114 }
 115
 116 static void dwmac4_set_umac_addr(struct mac_device_info *hw,
 117                                  unsigned char *addr, unsigned int reg_n)
 118 {
 119         void __iomem *ioaddr = hw->pcsr;
 120
 121         stmmac_dwmac4_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
 122                                    GMAC_ADDR_LOW(reg_n));
 123 }
 124
 125 static void dwmac4_get_umac_addr(struct mac_device_info *hw,
 126                                  unsigned char *addr, unsigned int reg_n)
 127 {
 128         void __iomem *ioaddr = hw->pcsr;
 129
 130         stmmac_dwmac4_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
 131                                    GMAC_ADDR_LOW(reg_n));
 132 }
 133
 134 static void dwmac4_set_eee_mode(struct mac_device_info *hw,
 135                                 bool en_tx_lpi_clockgating)
 136 {
 137         void __iomem *ioaddr = hw->pcsr;
 138         u32 value;
 139
 140         /* Enable the link status receive on RGMII, SGMII ore SMII
 141          * receive path and instruct the transmit to enter in LPI
 142          * state.
 143          */
 144         value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 145         value |= GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA;
 146
 147         if (en_tx_lpi_clockgating)
 148                 value |= GMAC4_LPI_CTRL_STATUS_LPITCSE;
 149
 150         writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 151 }
 152
 153 static void dwmac4_reset_eee_mode(struct mac_device_info *hw)
 154 {
 155         void __iomem *ioaddr = hw->pcsr;
 156         u32 value;
 157
 158         value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 159         value &= ~(GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA);
 160         writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 161 }
 162
 163 static void dwmac4_set_eee_pls(struct mac_device_info *hw, int link)
 164 {
 165         void __iomem *ioaddr = hw->pcsr;
 166         u32 value;
 167
 168         value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 169
 170         if (link)
 171                 value |= GMAC4_LPI_CTRL_STATUS_PLS;
 172         else
 173                 value &= ~GMAC4_LPI_CTRL_STATUS_PLS;
 174
 175         writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 176 }
 177
 178 static void dwmac4_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
 179 {
 180         void __iomem *ioaddr = hw->pcsr;
 181         int value = ((tw & 0xffff)) | ((ls & 0x3ff) << 16);
 182
 183         /* Program the timers in the LPI timer control register:
 184          * LS: minimum time (ms) for which the link
 185          *  status from PHY should be ok before transmitting
 186          *  the LPI pattern.
 187          * TW: minimum time (us) for which the core waits
 188          *  after it has stopped transmitting the LPI pattern.
 189          */
 190         writel(value, ioaddr + GMAC4_LPI_TIMER_CTRL);
 191 }
 192
 193 static void dwmac4_set_filter(struct mac_device_info *hw,
 194                               struct net_device *dev)
 195 {
 196         void __iomem *ioaddr = (void __iomem *)dev->base_addr;
 197         unsigned int value = 0;
 198
 199         if (dev->flags & IFF_PROMISC) {
 200                 value = GMAC_PACKET_FILTER_PR;
 201         } else if ((dev->flags & IFF_ALLMULTI) ||
 202                         (netdev_mc_count(dev) > HASH_TABLE_SIZE)) {
 203                 /* Pass all multi */
 204                 value = GMAC_PACKET_FILTER_PM;
 205                 /* Set the 64 bits of the HASH tab. To be updated if taller
 206                  * hash table is used
 207                  */
 208                 writel(0xffffffff, ioaddr + GMAC_HASH_TAB_0_31);
 209                 writel(0xffffffff, ioaddr + GMAC_HASH_TAB_32_63);
 210         } else if (!netdev_mc_empty(dev)) {
 211                 u32 mc_filter[2];
 212                 struct netdev_hw_addr *ha;
 213
 214                 /* Hash filter for multicast */
 215                 value = GMAC_PACKET_FILTER_HMC;
 216
 217                 memset(mc_filter, 0, sizeof(mc_filter));
 218                 netdev_for_each_mc_addr(ha, dev) {
 219                         /* The upper 6 bits of the calculated CRC are used to
 220                          * index the content of the Hash Table Reg 0 and 1.
 221                          */
 222                         int bit_nr =
 223                                 (bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26);
 224                         /* The most significant bit determines the register
 225                          * to use while the other 5 bits determines the bit
 226                          * within the selected register
 227                          */
 228                         mc_filter[bit_nr >> 5] |= (1 << (bit_nr & 0x1F));
 229                 }
 230                 writel(mc_filter[0], ioaddr + GMAC_HASH_TAB_0_31);
 231                 writel(mc_filter[1], ioaddr + GMAC_HASH_TAB_32_63);
 232         }
 233
 234         /* Handle multiple unicast addresses */
 235         if (netdev_uc_count(dev) > GMAC_MAX_PERFECT_ADDRESSES) {
 236                 /* Switch to promiscuous mode if more than 128 addrs
 237                  * are required
 238                  */
 239                 value |= GMAC_PACKET_FILTER_PR;
 240         } else if (!netdev_uc_empty(dev)) {
 241                 int reg = 1;
 242                 struct netdev_hw_addr *ha;
 243
 244                 netdev_for_each_uc_addr(ha, dev) {
 245                         dwmac4_set_umac_addr(hw, ha->addr, reg);
 246                         reg++;
 247                 }
 248         }
 249
 250         writel(value, ioaddr + GMAC_PACKET_FILTER);
 251 }
 252
 253 static void dwmac4_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
 254                              unsigned int fc, unsigned int pause_time)
 255 {
 256         void __iomem *ioaddr = hw->pcsr;
 257         u32 channel = STMMAC_CHAN0;     /* FIXME */
 258         unsigned int flow = 0;
 259
 260         pr_debug("GMAC Flow-Control:\n");
 261         if (fc & FLOW_RX) {
 262                 pr_debug("\tReceive Flow-Control ON\n");
 263                 flow |= GMAC_RX_FLOW_CTRL_RFE;
 264                 writel(flow, ioaddr + GMAC_RX_FLOW_CTRL);
 265         }
 266         if (fc & FLOW_TX) {
 267                 pr_debug("\tTransmit Flow-Control ON\n");
 268                 flow |= GMAC_TX_FLOW_CTRL_TFE;
 269                 writel(flow, ioaddr + GMAC_QX_TX_FLOW_CTRL(channel));
 270
 271                 if (duplex) {
 272                         pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
 273                         flow |= (pause_time << GMAC_TX_FLOW_CTRL_PT_SHIFT);
 274                         writel(flow, ioaddr + GMAC_QX_TX_FLOW_CTRL(channel));
 275                 }
 276         }
 277 }
 278
 279 static void dwmac4_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
 280                             bool loopback)
 281 {
 282         dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
 283 }
 284
 285 static void dwmac4_rane(void __iomem *ioaddr, bool restart)
 286 {
 287         dwmac_rane(ioaddr, GMAC_PCS_BASE, restart);
 288 }
 289
 290 static void dwmac4_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
 291 {
 292         dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
 293 }
 294
 295 /* RGMII or SMII interface */
 296 static void dwmac4_phystatus(void __iomem *ioaddr, struct stmmac_extra_stats *x)
 297 {
 298         u32 status;
 299
 300         status = readl(ioaddr + GMAC_PHYIF_CONTROL_STATUS);
 301         x->irq_rgmii_n++;
 302
 303         /* Check the link status */
 304         if (status & GMAC_PHYIF_CTRLSTATUS_LNKSTS) {
 305                 int speed_value;
 306
 307                 x->pcs_link = 1;
 308
 309                 speed_value = ((status & GMAC_PHYIF_CTRLSTATUS_SPEED) >>
 310                                GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT);
 311                 if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_125)
 312                         x->pcs_speed = SPEED_1000;
 313                 else if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_25)
 314                         x->pcs_speed = SPEED_100;
 315                 else
 316                         x->pcs_speed = SPEED_10;
 317
 318                 x->pcs_duplex = (status & GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK);
 319
 320                 pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
 321                         x->pcs_duplex ? "Full" : "Half");
 322         } else {
 323                 x->pcs_link = 0;
 324                 pr_info("Link is Down\n");
 325         }
 326 }
 327
 328 static int dwmac4_irq_status(struct mac_device_info *hw,
 329                              struct stmmac_extra_stats *x)
 330 {
 331         void __iomem *ioaddr = hw->pcsr;
 332         u32 mtl_int_qx_status;
 333         u32 intr_status;
 334         int ret = 0;
 335
 336         intr_status = readl(ioaddr + GMAC_INT_STATUS);
 337
 338         /* Not used events (e.g. MMC interrupts) are not handled. */
 339         if ((intr_status & mmc_tx_irq))
 340                 x->mmc_tx_irq_n++;
 341         if (unlikely(intr_status & mmc_rx_irq))
 342                 x->mmc_rx_irq_n++;
 343         if (unlikely(intr_status & mmc_rx_csum_offload_irq))
 344                 x->mmc_rx_csum_offload_irq_n++;
 345         /* Clear the PMT bits 5 and 6 by reading the PMT status reg */
 346         if (unlikely(intr_status & pmt_irq)) {
 347                 readl(ioaddr + GMAC_PMT);
 348                 x->irq_receive_pmt_irq_n++;
 349         }
 350
 351         mtl_int_qx_status = readl(ioaddr + MTL_INT_STATUS);
 352         /* Check MTL Interrupt: Currently only one queue is used: Q0. */
 353         if (mtl_int_qx_status & MTL_INT_Q0) {
 354                 /* read Queue 0 Interrupt status */
 355                 u32 status = readl(ioaddr + MTL_CHAN_INT_CTRL(STMMAC_CHAN0));
 356
 357                 if (status & MTL_RX_OVERFLOW_INT) {
 358                         /*  clear Interrupt */
 359                         writel(status | MTL_RX_OVERFLOW_INT,
 360                                ioaddr + MTL_CHAN_INT_CTRL(STMMAC_CHAN0));
 361                         ret = CORE_IRQ_MTL_RX_OVERFLOW;
 362                 }
 363         }
 364
 365         dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
 366         if (intr_status & PCS_RGSMIIIS_IRQ)
 367                 dwmac4_phystatus(ioaddr, x);
 368
 369         return ret;
 370 }
 371
 372 static void dwmac4_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x)
 373 {
 374         u32 value;
 375
 376         /*  Currently only channel 0 is supported */
 377         value = readl(ioaddr + MTL_CHAN_TX_DEBUG(STMMAC_CHAN0));
 378
 379         if (value & MTL_DEBUG_TXSTSFSTS)
 380                 x->mtl_tx_status_fifo_full++;
 381         if (value & MTL_DEBUG_TXFSTS)
 382                 x->mtl_tx_fifo_not_empty++;
 383         if (value & MTL_DEBUG_TWCSTS)
 384                 x->mmtl_fifo_ctrl++;
 385         if (value & MTL_DEBUG_TRCSTS_MASK) {
 386                 u32 trcsts = (value & MTL_DEBUG_TRCSTS_MASK)
 387                              >> MTL_DEBUG_TRCSTS_SHIFT;
 388                 if (trcsts == MTL_DEBUG_TRCSTS_WRITE)
 389                         x->mtl_tx_fifo_read_ctrl_write++;
 390                 else if (trcsts == MTL_DEBUG_TRCSTS_TXW)
 391                         x->mtl_tx_fifo_read_ctrl_wait++;
 392                 else if (trcsts == MTL_DEBUG_TRCSTS_READ)
 393                         x->mtl_tx_fifo_read_ctrl_read++;
 394                 else
 395                         x->mtl_tx_fifo_read_ctrl_idle++;
 396         }
 397         if (value & MTL_DEBUG_TXPAUSED)
 398                 x->mac_tx_in_pause++;
 399
 400         value = readl(ioaddr + MTL_CHAN_RX_DEBUG(STMMAC_CHAN0));
 401
 402         if (value & MTL_DEBUG_RXFSTS_MASK) {
 403                 u32 rxfsts = (value & MTL_DEBUG_RXFSTS_MASK)
 404                              >> MTL_DEBUG_RRCSTS_SHIFT;
 405
 406                 if (rxfsts == MTL_DEBUG_RXFSTS_FULL)
 407                         x->mtl_rx_fifo_fill_level_full++;
 408                 else if (rxfsts == MTL_DEBUG_RXFSTS_AT)
 409                         x->mtl_rx_fifo_fill_above_thresh++;
 410                 else if (rxfsts == MTL_DEBUG_RXFSTS_BT)
 411                         x->mtl_rx_fifo_fill_below_thresh++;
 412                 else
 413                         x->mtl_rx_fifo_fill_level_empty++;
 414         }
 415         if (value & MTL_DEBUG_RRCSTS_MASK) {
 416                 u32 rrcsts = (value & MTL_DEBUG_RRCSTS_MASK) >>
 417                              MTL_DEBUG_RRCSTS_SHIFT;
 418
 419                 if (rrcsts == MTL_DEBUG_RRCSTS_FLUSH)
 420                         x->mtl_rx_fifo_read_ctrl_flush++;
 421                 else if (rrcsts == MTL_DEBUG_RRCSTS_RSTAT)
 422                         x->mtl_rx_fifo_read_ctrl_read_data++;
 423                 else if (rrcsts == MTL_DEBUG_RRCSTS_RDATA)
 424                         x->mtl_rx_fifo_read_ctrl_status++;
 425                 else
 426                         x->mtl_rx_fifo_read_ctrl_idle++;
 427         }
 428         if (value & MTL_DEBUG_RWCSTS)
 429                 x->mtl_rx_fifo_ctrl_active++;
 430
 431         /* GMAC debug */
 432         value = readl(ioaddr + GMAC_DEBUG);
 433
 434         if (value & GMAC_DEBUG_TFCSTS_MASK) {
 435                 u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
 436                               >> GMAC_DEBUG_TFCSTS_SHIFT;
 437
 438                 if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
 439                         x->mac_tx_frame_ctrl_xfer++;
 440                 else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
 441                         x->mac_tx_frame_ctrl_pause++;
 442                 else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
 443                         x->mac_tx_frame_ctrl_wait++;
 444                 else
 445                         x->mac_tx_frame_ctrl_idle++;
 446         }
 447         if (value & GMAC_DEBUG_TPESTS)
 448                 x->mac_gmii_tx_proto_engine++;
 449         if (value & GMAC_DEBUG_RFCFCSTS_MASK)
 450                 x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
 451                                             >> GMAC_DEBUG_RFCFCSTS_SHIFT;
 452         if (value & GMAC_DEBUG_RPESTS)
 453                 x->mac_gmii_rx_proto_engine++;
 454 }
 455
 456 static const struct stmmac_ops dwmac4_ops = {
 457         .core_init = dwmac4_core_init,
 458         .rx_ipc = dwmac4_rx_ipc_enable,
 459         .rx_queue_enable = dwmac4_rx_queue_enable,
 460         .dump_regs = dwmac4_dump_regs,
 461         .host_irq_status = dwmac4_irq_status,
 462         .flow_ctrl = dwmac4_flow_ctrl,
 463         .pmt = dwmac4_pmt,
 464         .set_umac_addr = dwmac4_set_umac_addr,
 465         .get_umac_addr = dwmac4_get_umac_addr,
 466         .set_eee_mode = dwmac4_set_eee_mode,
 467         .reset_eee_mode = dwmac4_reset_eee_mode,
 468         .set_eee_timer = dwmac4_set_eee_timer,
 469         .set_eee_pls = dwmac4_set_eee_pls,
 470         .pcs_ctrl_ane = dwmac4_ctrl_ane,
 471         .pcs_rane = dwmac4_rane,
 472         .pcs_get_adv_lp = dwmac4_get_adv_lp,
 473         .debug = dwmac4_debug,
 474         .set_filter = dwmac4_set_filter,
 475 };
 476
 477 struct mac_device_info *dwmac4_setup(void __iomem *ioaddr, int mcbins,
 478                                      int perfect_uc_entries, int *synopsys_id)
 479 {
 480         struct mac_device_info *mac;
 481         u32 hwid = readl(ioaddr + GMAC_VERSION);
 482
 483         mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
 484         if (!mac)
 485                 return NULL;
 486
 487         mac->pcsr = ioaddr;
 488         mac->multicast_filter_bins = mcbins;
 489         mac->unicast_filter_entries = perfect_uc_entries;
 490         mac->mcast_bits_log2 = 0;
 491
 492         if (mac->multicast_filter_bins)
 493                 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
 494
 495         mac->mac = &dwmac4_ops;
 496
 497         mac->link.port = GMAC_CONFIG_PS;
 498         mac->link.duplex = GMAC_CONFIG_DM;
 499         mac->link.speed = GMAC_CONFIG_FES;
 500         mac->mii.addr = GMAC_MDIO_ADDR;
 501         mac->mii.data = GMAC_MDIO_DATA;
 502         mac->mii.addr_shift = 21;
 503         mac->mii.addr_mask = GENMASK(25, 21);
 504         mac->mii.reg_shift = 16;
 505         mac->mii.reg_mask = GENMASK(20, 16);
 506         mac->mii.clk_csr_shift = 8;
 507         mac->mii.clk_csr_mask = GENMASK(11, 8);
 508
 509         /* Get and dump the chip ID */
 510         *synopsys_id = stmmac_get_synopsys_id(hwid);
 511
 512         if (*synopsys_id > DWMAC_CORE_4_00)
 513                 mac->dma = &dwmac410_dma_ops;
 514         else
 515                 mac->dma = &dwmac4_dma_ops;
 516
 517         return mac;
 518 }