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Staging: strip: delete the driver
[linux/fpc-iii.git] / drivers / i2c / busses / i2c-pxa.c
blob14d249f5ed3f3db236b6c8664df152fc583a5003
1 /*
2 * i2c_adap_pxa.c
3 *
4 * I2C adapter for the PXA I2C bus access.
5 *
6 * Copyright (C) 2002 Intrinsyc Software Inc.
7 * Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * History:
14 * Apr 2002: Initial version [CS]
15 * Jun 2002: Properly separated algo/adap [FB]
16 * Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
17 * Jan 2003: added limited signal handling [Kai-Uwe Bloem]
18 * Sep 2004: Major rework to ensure efficient bus handling [RMK]
19 * Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood]
20 * Feb 2005: Rework slave mode handling [RMK]
21 */
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/i2c.h>
25 #include <linux/i2c-id.h>
26 #include <linux/init.h>
27 #include <linux/time.h>
28 #include <linux/sched.h>
29 #include <linux/delay.h>
30 #include <linux/errno.h>
31 #include <linux/interrupt.h>
32 #include <linux/i2c-pxa.h>
33 #include <linux/platform_device.h>
34 #include <linux/err.h>
35 #include <linux/clk.h>
36 #include <linux/slab.h>
37
38 #include <asm/irq.h>
39 #include <asm/io.h>
40 #include <plat/i2c.h>
41
42 /*
43 * I2C register offsets will be shifted 0 or 1 bit left, depending on
44 * different SoCs
45 */
46 #define REG_SHIFT_0 (0 << 0)
47 #define REG_SHIFT_1 (1 << 0)
48 #define REG_SHIFT(d) ((d) & 0x1)
49
50 static const struct platform_device_id i2c_pxa_id_table[] = {
51 { "pxa2xx-i2c", REG_SHIFT_1 },
52 { "pxa3xx-pwri2c", REG_SHIFT_0 },
53 { },
54 };
55 MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table);
56
57 /*
58 * I2C registers and bit definitions
59 */
60 #define IBMR (0x00)
61 #define IDBR (0x08)
62 #define ICR (0x10)
63 #define ISR (0x18)
64 #define ISAR (0x20)
65
66 #define ICR_START (1 << 0) /* start bit */
67 #define ICR_STOP (1 << 1) /* stop bit */
68 #define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */
69 #define ICR_TB (1 << 3) /* transfer byte bit */
70 #define ICR_MA (1 << 4) /* master abort */
71 #define ICR_SCLE (1 << 5) /* master clock enable */
72 #define ICR_IUE (1 << 6) /* unit enable */
73 #define ICR_GCD (1 << 7) /* general call disable */
74 #define ICR_ITEIE (1 << 8) /* enable tx interrupts */
75 #define ICR_IRFIE (1 << 9) /* enable rx interrupts */
76 #define ICR_BEIE (1 << 10) /* enable bus error ints */
77 #define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */
78 #define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */
79 #define ICR_SADIE (1 << 13) /* slave address detected int enable */
80 #define ICR_UR (1 << 14) /* unit reset */
81 #define ICR_FM (1 << 15) /* fast mode */
82
83 #define ISR_RWM (1 << 0) /* read/write mode */
84 #define ISR_ACKNAK (1 << 1) /* ack/nak status */
85 #define ISR_UB (1 << 2) /* unit busy */
86 #define ISR_IBB (1 << 3) /* bus busy */
87 #define ISR_SSD (1 << 4) /* slave stop detected */
88 #define ISR_ALD (1 << 5) /* arbitration loss detected */
89 #define ISR_ITE (1 << 6) /* tx buffer empty */
90 #define ISR_IRF (1 << 7) /* rx buffer full */
91 #define ISR_GCAD (1 << 8) /* general call address detected */
92 #define ISR_SAD (1 << 9) /* slave address detected */
93 #define ISR_BED (1 << 10) /* bus error no ACK/NAK */
94
95 struct pxa_i2c {
96 spinlock_t lock;
97 wait_queue_head_t wait;
98 struct i2c_msg *msg;
99 unsigned int msg_num;
100 unsigned int msg_idx;
101 unsigned int msg_ptr;
102 unsigned int slave_addr;
103
104 struct i2c_adapter adap;
105 struct clk *clk;
106 #ifdef CONFIG_I2C_PXA_SLAVE
107 struct i2c_slave_client *slave;
108 #endif
109
110 unsigned int irqlogidx;
111 u32 isrlog[32];
112 u32 icrlog[32];
113
114 void __iomem *reg_base;
115 unsigned int reg_shift;
116
117 unsigned long iobase;
118 unsigned long iosize;
119
120 int irq;
121 unsigned int use_pio :1;
122 unsigned int fast_mode :1;
123 };
124
125 #define _IBMR(i2c) ((i2c)->reg_base + (0x0 << (i2c)->reg_shift))
126 #define _IDBR(i2c) ((i2c)->reg_base + (0x4 << (i2c)->reg_shift))
127 #define _ICR(i2c) ((i2c)->reg_base + (0x8 << (i2c)->reg_shift))
128 #define _ISR(i2c) ((i2c)->reg_base + (0xc << (i2c)->reg_shift))
129 #define _ISAR(i2c) ((i2c)->reg_base + (0x10 << (i2c)->reg_shift))
130
131 /*
132 * I2C Slave mode address
133 */
134 #define I2C_PXA_SLAVE_ADDR 0x1
135
136 #ifdef DEBUG
137
138 struct bits {
139 u32 mask;
140 const char *set;
141 const char *unset;
142 };
143 #define PXA_BIT(m, s, u) { .mask = m, .set = s, .unset = u }
144
145 static inline void
146 decode_bits(const char *prefix, const struct bits *bits, int num, u32 val)
147 {
148 printk("%s %08x: ", prefix, val);
149 while (num--) {
150 const char *str = val & bits->mask ? bits->set : bits->unset;
151 if (str)
152 printk("%s ", str);
153 bits++;
154 }
155 }
156
157 static const struct bits isr_bits[] = {
158 PXA_BIT(ISR_RWM, "RX", "TX"),
159 PXA_BIT(ISR_ACKNAK, "NAK", "ACK"),
160 PXA_BIT(ISR_UB, "Bsy", "Rdy"),
161 PXA_BIT(ISR_IBB, "BusBsy", "BusRdy"),
162 PXA_BIT(ISR_SSD, "SlaveStop", NULL),
163 PXA_BIT(ISR_ALD, "ALD", NULL),
164 PXA_BIT(ISR_ITE, "TxEmpty", NULL),
165 PXA_BIT(ISR_IRF, "RxFull", NULL),
166 PXA_BIT(ISR_GCAD, "GenCall", NULL),
167 PXA_BIT(ISR_SAD, "SlaveAddr", NULL),
168 PXA_BIT(ISR_BED, "BusErr", NULL),
169 };
170
171 static void decode_ISR(unsigned int val)
172 {
173 decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val);
174 printk("\n");
175 }
176
177 static const struct bits icr_bits[] = {
178 PXA_BIT(ICR_START, "START", NULL),
179 PXA_BIT(ICR_STOP, "STOP", NULL),
180 PXA_BIT(ICR_ACKNAK, "ACKNAK", NULL),
181 PXA_BIT(ICR_TB, "TB", NULL),
182 PXA_BIT(ICR_MA, "MA", NULL),
183 PXA_BIT(ICR_SCLE, "SCLE", "scle"),
184 PXA_BIT(ICR_IUE, "IUE", "iue"),
185 PXA_BIT(ICR_GCD, "GCD", NULL),
186 PXA_BIT(ICR_ITEIE, "ITEIE", NULL),
187 PXA_BIT(ICR_IRFIE, "IRFIE", NULL),
188 PXA_BIT(ICR_BEIE, "BEIE", NULL),
189 PXA_BIT(ICR_SSDIE, "SSDIE", NULL),
190 PXA_BIT(ICR_ALDIE, "ALDIE", NULL),
191 PXA_BIT(ICR_SADIE, "SADIE", NULL),
192 PXA_BIT(ICR_UR, "UR", "ur"),
193 };
194
195 #ifdef CONFIG_I2C_PXA_SLAVE
196 static void decode_ICR(unsigned int val)
197 {
198 decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val);
199 printk("\n");
200 }
201 #endif
202
203 static unsigned int i2c_debug = DEBUG;
204
205 static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname)
206 {
207 dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno,
208 readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
209 }
210
211 #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __func__)
212 #else
213 #define i2c_debug 0
214
215 #define show_state(i2c) do { } while (0)
216 #define decode_ISR(val) do { } while (0)
217 #define decode_ICR(val) do { } while (0)
218 #endif
219
220 #define eedbg(lvl, x...) do { if ((lvl) < 1) { printk(KERN_DEBUG "" x); } } while(0)
221
222 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret);
223 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id);
224
225 static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
226 {
227 unsigned int i;
228 printk(KERN_ERR "i2c: error: %s\n", why);
229 printk(KERN_ERR "i2c: msg_num: %d msg_idx: %d msg_ptr: %d\n",
230 i2c->msg_num, i2c->msg_idx, i2c->msg_ptr);
231 printk(KERN_ERR "i2c: ICR: %08x ISR: %08x\n",
232 readl(_ICR(i2c)), readl(_ISR(i2c)));
233 printk(KERN_DEBUG "i2c: log: ");
234 for (i = 0; i < i2c->irqlogidx; i++)
235 printk("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]);
236 printk("\n");
237 }
238
239 static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c)
240 {
241 return !(readl(_ICR(i2c)) & ICR_SCLE);
242 }
243
244 static void i2c_pxa_abort(struct pxa_i2c *i2c)
245 {
246 int i = 250;
247
248 if (i2c_pxa_is_slavemode(i2c)) {
249 dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__);
250 return;
251 }
252
253 while ((i > 0) && (readl(_IBMR(i2c)) & 0x1) == 0) {
254 unsigned long icr = readl(_ICR(i2c));
255
256 icr &= ~ICR_START;
257 icr |= ICR_ACKNAK | ICR_STOP | ICR_TB;
258
259 writel(icr, _ICR(i2c));
260
261 show_state(i2c);
262
263 mdelay(1);
264 i --;
265 }
266
267 writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP),
268 _ICR(i2c));
269 }
270
271 static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
272 {
273 int timeout = DEF_TIMEOUT;
274
275 while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
276 if ((readl(_ISR(i2c)) & ISR_SAD) != 0)
277 timeout += 4;
278
279 msleep(2);
280 show_state(i2c);
281 }
282
283 if (timeout < 0)
284 show_state(i2c);
285
286 return timeout < 0 ? I2C_RETRY : 0;
287 }
288
289 static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
290 {
291 unsigned long timeout = jiffies + HZ*4;
292
293 while (time_before(jiffies, timeout)) {
294 if (i2c_debug > 1)
295 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
296 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
297
298 if (readl(_ISR(i2c)) & ISR_SAD) {
299 if (i2c_debug > 0)
300 dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__);
301 goto out;
302 }
303
304 /* wait for unit and bus being not busy, and we also do a
305 * quick check of the i2c lines themselves to ensure they've
306 * gone high...
307 */
308 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 && readl(_IBMR(i2c)) == 3) {
309 if (i2c_debug > 0)
310 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
311 return 1;
312 }
313
314 msleep(1);
315 }
316
317 if (i2c_debug > 0)
318 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
319 out:
320 return 0;
321 }
322
323 static int i2c_pxa_set_master(struct pxa_i2c *i2c)
324 {
325 if (i2c_debug)
326 dev_dbg(&i2c->adap.dev, "setting to bus master\n");
327
328 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) {
329 dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__);
330 if (!i2c_pxa_wait_master(i2c)) {
331 dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__);
332 return I2C_RETRY;
333 }
334 }
335
336 writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
337 return 0;
338 }
339
340 #ifdef CONFIG_I2C_PXA_SLAVE
341 static int i2c_pxa_wait_slave(struct pxa_i2c *i2c)
342 {
343 unsigned long timeout = jiffies + HZ*1;
344
345 /* wait for stop */
346
347 show_state(i2c);
348
349 while (time_before(jiffies, timeout)) {
350 if (i2c_debug > 1)
351 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
352 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
353
354 if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 ||
355 (readl(_ISR(i2c)) & ISR_SAD) != 0 ||
356 (readl(_ICR(i2c)) & ICR_SCLE) == 0) {
357 if (i2c_debug > 1)
358 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
359 return 1;
360 }
361
362 msleep(1);
363 }
364
365 if (i2c_debug > 0)
366 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
367 return 0;
368 }
369
370 /*
371 * clear the hold on the bus, and take of anything else
372 * that has been configured
373 */
374 static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode)
375 {
376 show_state(i2c);
377
378 if (errcode < 0) {
379 udelay(100); /* simple delay */
380 } else {
381 /* we need to wait for the stop condition to end */
382
383 /* if we where in stop, then clear... */
384 if (readl(_ICR(i2c)) & ICR_STOP) {
385 udelay(100);
386 writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c));
387 }
388
389 if (!i2c_pxa_wait_slave(i2c)) {
390 dev_err(&i2c->adap.dev, "%s: wait timedout\n",
391 __func__);
392 return;
393 }
394 }
395
396 writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c));
397 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
398
399 if (i2c_debug) {
400 dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c)), readl(_ISR(i2c)));
401 decode_ICR(readl(_ICR(i2c)));
402 }
403 }
404 #else
405 #define i2c_pxa_set_slave(i2c, err) do { } while (0)
406 #endif
407
408 static void i2c_pxa_reset(struct pxa_i2c *i2c)
409 {
410 pr_debug("Resetting I2C Controller Unit\n");
411
412 /* abort any transfer currently under way */
413 i2c_pxa_abort(i2c);
414
415 /* reset according to 9.8 */
416 writel(ICR_UR, _ICR(i2c));
417 writel(I2C_ISR_INIT, _ISR(i2c));
418 writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c));
419
420 writel(i2c->slave_addr, _ISAR(i2c));
421
422 /* set control register values */
423 writel(I2C_ICR_INIT | (i2c->fast_mode ? ICR_FM : 0), _ICR(i2c));
424
425 #ifdef CONFIG_I2C_PXA_SLAVE
426 dev_info(&i2c->adap.dev, "Enabling slave mode\n");
427 writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c));
428 #endif
429
430 i2c_pxa_set_slave(i2c, 0);
431
432 /* enable unit */
433 writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c));
434 udelay(100);
435 }
436
437
438 #ifdef CONFIG_I2C_PXA_SLAVE
439 /*
440 * PXA I2C Slave mode
441 */
442
443 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
444 {
445 if (isr & ISR_BED) {
446 /* what should we do here? */
447 } else {
448 int ret = 0;
449
450 if (i2c->slave != NULL)
451 ret = i2c->slave->read(i2c->slave->data);
452
453 writel(ret, _IDBR(i2c));
454 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); /* allow next byte */
455 }
456 }
457
458 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
459 {
460 unsigned int byte = readl(_IDBR(i2c));
461
462 if (i2c->slave != NULL)
463 i2c->slave->write(i2c->slave->data, byte);
464
465 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
466 }
467
468 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
469 {
470 int timeout;
471
472 if (i2c_debug > 0)
473 dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n",
474 (isr & ISR_RWM) ? 'r' : 't');
475
476 if (i2c->slave != NULL)
477 i2c->slave->event(i2c->slave->data,
478 (isr & ISR_RWM) ? I2C_SLAVE_EVENT_START_READ : I2C_SLAVE_EVENT_START_WRITE);
479
480 /*
481 * slave could interrupt in the middle of us generating a
482 * start condition... if this happens, we'd better back off
483 * and stop holding the poor thing up
484 */
485 writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
486 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
487
488 timeout = 0x10000;
489
490 while (1) {
491 if ((readl(_IBMR(i2c)) & 2) == 2)
492 break;
493
494 timeout--;
495
496 if (timeout <= 0) {
497 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
498 break;
499 }
500 }
501
502 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
503 }
504
505 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
506 {
507 if (i2c_debug > 2)
508 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n");
509
510 if (i2c->slave != NULL)
511 i2c->slave->event(i2c->slave->data, I2C_SLAVE_EVENT_STOP);
512
513 if (i2c_debug > 2)
514 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n");
515
516 /*
517 * If we have a master-mode message waiting,
518 * kick it off now that the slave has completed.
519 */
520 if (i2c->msg)
521 i2c_pxa_master_complete(i2c, I2C_RETRY);
522 }
523 #else
524 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
525 {
526 if (isr & ISR_BED) {
527 /* what should we do here? */
528 } else {
529 writel(0, _IDBR(i2c));
530 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
531 }
532 }
533
534 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
535 {
536 writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
537 }
538
539 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
540 {
541 int timeout;
542
543 /*
544 * slave could interrupt in the middle of us generating a
545 * start condition... if this happens, we'd better back off
546 * and stop holding the poor thing up
547 */
548 writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
549 writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
550
551 timeout = 0x10000;
552
553 while (1) {
554 if ((readl(_IBMR(i2c)) & 2) == 2)
555 break;
556
557 timeout--;
558
559 if (timeout <= 0) {
560 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
561 break;
562 }
563 }
564
565 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
566 }
567
568 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
569 {
570 if (i2c->msg)
571 i2c_pxa_master_complete(i2c, I2C_RETRY);
572 }
573 #endif
574
575 /*
576 * PXA I2C Master mode
577 */
578
579 static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg)
580 {
581 unsigned int addr = (msg->addr & 0x7f) << 1;
582
583 if (msg->flags & I2C_M_RD)
584 addr |= 1;
585
586 return addr;
587 }
588
589 static inline void i2c_pxa_start_message(struct pxa_i2c *i2c)
590 {
591 u32 icr;
592
593 /*
594 * Step 1: target slave address into IDBR
595 */
596 writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
597
598 /*
599 * Step 2: initiate the write.
600 */
601 icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
602 writel(icr | ICR_START | ICR_TB, _ICR(i2c));
603 }
604
605 static inline void i2c_pxa_stop_message(struct pxa_i2c *i2c)
606 {
607 u32 icr;
608
609 /*
610 * Clear the STOP and ACK flags
611 */
612 icr = readl(_ICR(i2c));
613 icr &= ~(ICR_STOP | ICR_ACKNAK);
614 writel(icr, _ICR(i2c));
615 }
616
617 static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c)
618 {
619 /* make timeout the same as for interrupt based functions */
620 long timeout = 2 * DEF_TIMEOUT;
621
622 /*
623 * Wait for the bus to become free.
624 */
625 while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
626 udelay(1000);
627 show_state(i2c);
628 }
629
630 if (timeout < 0) {
631 show_state(i2c);
632 dev_err(&i2c->adap.dev,
633 "i2c_pxa: timeout waiting for bus free\n");
634 return I2C_RETRY;
635 }
636
637 /*
638 * Set master mode.
639 */
640 writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
641
642 return 0;
643 }
644
645 static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c,
646 struct i2c_msg *msg, int num)
647 {
648 unsigned long timeout = 500000; /* 5 seconds */
649 int ret = 0;
650
651 ret = i2c_pxa_pio_set_master(i2c);
652 if (ret)
653 goto out;
654
655 i2c->msg = msg;
656 i2c->msg_num = num;
657 i2c->msg_idx = 0;
658 i2c->msg_ptr = 0;
659 i2c->irqlogidx = 0;
660
661 i2c_pxa_start_message(i2c);
662
663 while (i2c->msg_num > 0 && --timeout) {
664 i2c_pxa_handler(0, i2c);
665 udelay(10);
666 }
667
668 i2c_pxa_stop_message(i2c);
669
670 /*
671 * We place the return code in i2c->msg_idx.
672 */
673 ret = i2c->msg_idx;
674
675 out:
676 if (timeout == 0)
677 i2c_pxa_scream_blue_murder(i2c, "timeout");
678
679 return ret;
680 }
681
682 /*
683 * We are protected by the adapter bus mutex.
684 */
685 static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num)
686 {
687 long timeout;
688 int ret;
689
690 /*
691 * Wait for the bus to become free.
692 */
693 ret = i2c_pxa_wait_bus_not_busy(i2c);
694 if (ret) {
695 dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n");
696 goto out;
697 }
698
699 /*
700 * Set master mode.
701 */
702 ret = i2c_pxa_set_master(i2c);
703 if (ret) {
704 dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret);
705 goto out;
706 }
707
708 spin_lock_irq(&i2c->lock);
709
710 i2c->msg = msg;
711 i2c->msg_num = num;
712 i2c->msg_idx = 0;
713 i2c->msg_ptr = 0;
714 i2c->irqlogidx = 0;
715
716 i2c_pxa_start_message(i2c);
717
718 spin_unlock_irq(&i2c->lock);
719
720 /*
721 * The rest of the processing occurs in the interrupt handler.
722 */
723 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
724 i2c_pxa_stop_message(i2c);
725
726 /*
727 * We place the return code in i2c->msg_idx.
728 */
729 ret = i2c->msg_idx;
730
731 if (timeout == 0)
732 i2c_pxa_scream_blue_murder(i2c, "timeout");
733
734 out:
735 return ret;
736 }
737
738 static int i2c_pxa_pio_xfer(struct i2c_adapter *adap,
739 struct i2c_msg msgs[], int num)
740 {
741 struct pxa_i2c *i2c = adap->algo_data;
742 int ret, i;
743
744 /* If the I2C controller is disabled we need to reset it
745 (probably due to a suspend/resume destroying state). We do
746 this here as we can then avoid worrying about resuming the
747 controller before its users. */
748 if (!(readl(_ICR(i2c)) & ICR_IUE))
749 i2c_pxa_reset(i2c);
750
751 for (i = adap->retries; i >= 0; i--) {
752 ret = i2c_pxa_do_pio_xfer(i2c, msgs, num);
753 if (ret != I2C_RETRY)
754 goto out;
755
756 if (i2c_debug)
757 dev_dbg(&adap->dev, "Retrying transmission\n");
758 udelay(100);
759 }
760 i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
761 ret = -EREMOTEIO;
762 out:
763 i2c_pxa_set_slave(i2c, ret);
764 return ret;
765 }
766
767 /*
768 * i2c_pxa_master_complete - complete the message and wake up.
769 */
770 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret)
771 {
772 i2c->msg_ptr = 0;
773 i2c->msg = NULL;
774 i2c->msg_idx ++;
775 i2c->msg_num = 0;
776 if (ret)
777 i2c->msg_idx = ret;
778 if (!i2c->use_pio)
779 wake_up(&i2c->wait);
780 }
781
782 static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
783 {
784 u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
785
786 again:
787 /*
788 * If ISR_ALD is set, we lost arbitration.
789 */
790 if (isr & ISR_ALD) {
791 /*
792 * Do we need to do anything here? The PXA docs
793 * are vague about what happens.
794 */
795 i2c_pxa_scream_blue_murder(i2c, "ALD set");
796
797 /*
798 * We ignore this error. We seem to see spurious ALDs
799 * for seemingly no reason. If we handle them as I think
800 * they should, we end up causing an I2C error, which
801 * is painful for some systems.
802 */
803 return; /* ignore */
804 }
805
806 if (isr & ISR_BED) {
807 int ret = BUS_ERROR;
808
809 /*
810 * I2C bus error - either the device NAK'd us, or
811 * something more serious happened. If we were NAK'd
812 * on the initial address phase, we can retry.
813 */
814 if (isr & ISR_ACKNAK) {
815 if (i2c->msg_ptr == 0 && i2c->msg_idx == 0)
816 ret = I2C_RETRY;
817 else
818 ret = XFER_NAKED;
819 }
820 i2c_pxa_master_complete(i2c, ret);
821 } else if (isr & ISR_RWM) {
822 /*
823 * Read mode. We have just sent the address byte, and
824 * now we must initiate the transfer.
825 */
826 if (i2c->msg_ptr == i2c->msg->len - 1 &&
827 i2c->msg_idx == i2c->msg_num - 1)
828 icr |= ICR_STOP | ICR_ACKNAK;
829
830 icr |= ICR_ALDIE | ICR_TB;
831 } else if (i2c->msg_ptr < i2c->msg->len) {
832 /*
833 * Write mode. Write the next data byte.
834 */
835 writel(i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c));
836
837 icr |= ICR_ALDIE | ICR_TB;
838
839 /*
840 * If this is the last byte of the last message, send
841 * a STOP.
842 */
843 if (i2c->msg_ptr == i2c->msg->len &&
844 i2c->msg_idx == i2c->msg_num - 1)
845 icr |= ICR_STOP;
846 } else if (i2c->msg_idx < i2c->msg_num - 1) {
847 /*
848 * Next segment of the message.
849 */
850 i2c->msg_ptr = 0;
851 i2c->msg_idx ++;
852 i2c->msg++;
853
854 /*
855 * If we aren't doing a repeated start and address,
856 * go back and try to send the next byte. Note that
857 * we do not support switching the R/W direction here.
858 */
859 if (i2c->msg->flags & I2C_M_NOSTART)
860 goto again;
861
862 /*
863 * Write the next address.
864 */
865 writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
866
867 /*
868 * And trigger a repeated start, and send the byte.
869 */
870 icr &= ~ICR_ALDIE;
871 icr |= ICR_START | ICR_TB;
872 } else {
873 if (i2c->msg->len == 0) {
874 /*
875 * Device probes have a message length of zero
876 * and need the bus to be reset before it can
877 * be used again.
878 */
879 i2c_pxa_reset(i2c);
880 }
881 i2c_pxa_master_complete(i2c, 0);
882 }
883
884 i2c->icrlog[i2c->irqlogidx-1] = icr;
885
886 writel(icr, _ICR(i2c));
887 show_state(i2c);
888 }
889
890 static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr)
891 {
892 u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
893
894 /*
895 * Read the byte.
896 */
897 i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c));
898
899 if (i2c->msg_ptr < i2c->msg->len) {
900 /*
901 * If this is the last byte of the last
902 * message, send a STOP.
903 */
904 if (i2c->msg_ptr == i2c->msg->len - 1)
905 icr |= ICR_STOP | ICR_ACKNAK;
906
907 icr |= ICR_ALDIE | ICR_TB;
908 } else {
909 i2c_pxa_master_complete(i2c, 0);
910 }
911
912 i2c->icrlog[i2c->irqlogidx-1] = icr;
913
914 writel(icr, _ICR(i2c));
915 }
916
917 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id)
918 {
919 struct pxa_i2c *i2c = dev_id;
920 u32 isr = readl(_ISR(i2c));
921
922 if (i2c_debug > 2 && 0) {
923 dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",
924 __func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c)));
925 decode_ISR(isr);
926 }
927
928 if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog))
929 i2c->isrlog[i2c->irqlogidx++] = isr;
930
931 show_state(i2c);
932
933 /*
934 * Always clear all pending IRQs.
935 */
936 writel(isr & (ISR_SSD|ISR_ALD|ISR_ITE|ISR_IRF|ISR_SAD|ISR_BED), _ISR(i2c));
937
938 if (isr & ISR_SAD)
939 i2c_pxa_slave_start(i2c, isr);
940 if (isr & ISR_SSD)
941 i2c_pxa_slave_stop(i2c);
942
943 if (i2c_pxa_is_slavemode(i2c)) {
944 if (isr & ISR_ITE)
945 i2c_pxa_slave_txempty(i2c, isr);
946 if (isr & ISR_IRF)
947 i2c_pxa_slave_rxfull(i2c, isr);
948 } else if (i2c->msg) {
949 if (isr & ISR_ITE)
950 i2c_pxa_irq_txempty(i2c, isr);
951 if (isr & ISR_IRF)
952 i2c_pxa_irq_rxfull(i2c, isr);
953 } else {
954 i2c_pxa_scream_blue_murder(i2c, "spurious irq");
955 }
956
957 return IRQ_HANDLED;
958 }
959
960
961 static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
962 {
963 struct pxa_i2c *i2c = adap->algo_data;
964 int ret, i;
965
966 for (i = adap->retries; i >= 0; i--) {
967 ret = i2c_pxa_do_xfer(i2c, msgs, num);
968 if (ret != I2C_RETRY)
969 goto out;
970
971 if (i2c_debug)
972 dev_dbg(&adap->dev, "Retrying transmission\n");
973 udelay(100);
974 }
975 i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
976 ret = -EREMOTEIO;
977 out:
978 i2c_pxa_set_slave(i2c, ret);
979 return ret;
980 }
981
982 static u32 i2c_pxa_functionality(struct i2c_adapter *adap)
983 {
984 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
985 }
986
987 static const struct i2c_algorithm i2c_pxa_algorithm = {
988 .master_xfer = i2c_pxa_xfer,
989 .functionality = i2c_pxa_functionality,
990 };
991
992 static const struct i2c_algorithm i2c_pxa_pio_algorithm = {
993 .master_xfer = i2c_pxa_pio_xfer,
994 .functionality = i2c_pxa_functionality,
995 };
996
997 static int i2c_pxa_probe(struct platform_device *dev)
998 {
999 struct pxa_i2c *i2c;
1000 struct resource *res;
1001 struct i2c_pxa_platform_data *plat = dev->dev.platform_data;
1002 struct platform_device_id *id = platform_get_device_id(dev);
1003 int ret;
1004 int irq;
1005
1006 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1007 irq = platform_get_irq(dev, 0);
1008 if (res == NULL || irq < 0)
1009 return -ENODEV;
1010
1011 if (!request_mem_region(res->start, resource_size(res), res->name))
1012 return -ENOMEM;
1013
1014 i2c = kzalloc(sizeof(struct pxa_i2c), GFP_KERNEL);
1015 if (!i2c) {
1016 ret = -ENOMEM;
1017 goto emalloc;
1018 }
1019
1020 i2c->adap.owner = THIS_MODULE;
1021 i2c->adap.retries = 5;
1022
1023 spin_lock_init(&i2c->lock);
1024 init_waitqueue_head(&i2c->wait);
1025
1026 /*
1027 * If "dev->id" is negative we consider it as zero.
1028 * The reason to do so is to avoid sysfs names that only make
1029 * sense when there are multiple adapters.
1030 */
1031 i2c->adap.nr = dev->id != -1 ? dev->id : 0;
1032 snprintf(i2c->adap.name, sizeof(i2c->adap.name), "pxa_i2c-i2c.%u",
1033 i2c->adap.nr);
1034
1035 i2c->clk = clk_get(&dev->dev, NULL);
1036 if (IS_ERR(i2c->clk)) {
1037 ret = PTR_ERR(i2c->clk);
1038 goto eclk;
1039 }
1040
1041 i2c->reg_base = ioremap(res->start, resource_size(res));
1042 if (!i2c->reg_base) {
1043 ret = -EIO;
1044 goto eremap;
1045 }
1046 i2c->reg_shift = REG_SHIFT(id->driver_data);
1047
1048 i2c->iobase = res->start;
1049 i2c->iosize = resource_size(res);
1050
1051 i2c->irq = irq;
1052
1053 i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
1054
1055 #ifdef CONFIG_I2C_PXA_SLAVE
1056 if (plat) {
1057 i2c->slave_addr = plat->slave_addr;
1058 i2c->slave = plat->slave;
1059 }
1060 #endif
1061
1062 clk_enable(i2c->clk);
1063
1064 if (plat) {
1065 i2c->adap.class = plat->class;
1066 i2c->use_pio = plat->use_pio;
1067 i2c->fast_mode = plat->fast_mode;
1068 }
1069
1070 if (i2c->use_pio) {
1071 i2c->adap.algo = &i2c_pxa_pio_algorithm;
1072 } else {
1073 i2c->adap.algo = &i2c_pxa_algorithm;
1074 ret = request_irq(irq, i2c_pxa_handler, IRQF_DISABLED,
1075 i2c->adap.name, i2c);
1076 if (ret)
1077 goto ereqirq;
1078 }
1079
1080 i2c_pxa_reset(i2c);
1081
1082 i2c->adap.algo_data = i2c;
1083 i2c->adap.dev.parent = &dev->dev;
1084
1085 ret = i2c_add_numbered_adapter(&i2c->adap);
1086 if (ret < 0) {
1087 printk(KERN_INFO "I2C: Failed to add bus\n");
1088 goto eadapt;
1089 }
1090
1091 platform_set_drvdata(dev, i2c);
1092
1093 #ifdef CONFIG_I2C_PXA_SLAVE
1094 printk(KERN_INFO "I2C: %s: PXA I2C adapter, slave address %d\n",
1095 dev_name(&i2c->adap.dev), i2c->slave_addr);
1096 #else
1097 printk(KERN_INFO "I2C: %s: PXA I2C adapter\n",
1098 dev_name(&i2c->adap.dev));
1099 #endif
1100 return 0;
1101
1102 eadapt:
1103 if (!i2c->use_pio)
1104 free_irq(irq, i2c);
1105 ereqirq:
1106 clk_disable(i2c->clk);
1107 iounmap(i2c->reg_base);
1108 eremap:
1109 clk_put(i2c->clk);
1110 eclk:
1111 kfree(i2c);
1112 emalloc:
1113 release_mem_region(res->start, resource_size(res));
1114 return ret;
1115 }
1116
1117 static int __exit i2c_pxa_remove(struct platform_device *dev)
1118 {
1119 struct pxa_i2c *i2c = platform_get_drvdata(dev);
1120
1121 platform_set_drvdata(dev, NULL);
1122
1123 i2c_del_adapter(&i2c->adap);
1124 if (!i2c->use_pio)
1125 free_irq(i2c->irq, i2c);
1126
1127 clk_disable(i2c->clk);
1128 clk_put(i2c->clk);
1129
1130 iounmap(i2c->reg_base);
1131 release_mem_region(i2c->iobase, i2c->iosize);
1132 kfree(i2c);
1133
1134 return 0;
1135 }
1136
1137 #ifdef CONFIG_PM
1138 static int i2c_pxa_suspend_noirq(struct device *dev)
1139 {
1140 struct platform_device *pdev = to_platform_device(dev);
1141 struct pxa_i2c *i2c = platform_get_drvdata(pdev);
1142
1143 clk_disable(i2c->clk);
1144
1145 return 0;
1146 }
1147
1148 static int i2c_pxa_resume_noirq(struct device *dev)
1149 {
1150 struct platform_device *pdev = to_platform_device(dev);
1151 struct pxa_i2c *i2c = platform_get_drvdata(pdev);
1152
1153 clk_enable(i2c->clk);
1154 i2c_pxa_reset(i2c);
1155
1156 return 0;
1157 }
1158
1159 static const struct dev_pm_ops i2c_pxa_dev_pm_ops = {
1160 .suspend_noirq = i2c_pxa_suspend_noirq,
1161 .resume_noirq = i2c_pxa_resume_noirq,
1162 };
1163
1164 #define I2C_PXA_DEV_PM_OPS (&i2c_pxa_dev_pm_ops)
1165 #else
1166 #define I2C_PXA_DEV_PM_OPS NULL
1167 #endif
1168
1169 static struct platform_driver i2c_pxa_driver = {
1170 .probe = i2c_pxa_probe,
1171 .remove = __exit_p(i2c_pxa_remove),
1172 .driver = {
1173 .name = "pxa2xx-i2c",
1174 .owner = THIS_MODULE,
1175 .pm = I2C_PXA_DEV_PM_OPS,
1176 },
1177 .id_table = i2c_pxa_id_table,
1178 };
1179
1180 static int __init i2c_adap_pxa_init(void)
1181 {
1182 return platform_driver_register(&i2c_pxa_driver);
1183 }
1184
1185 static void __exit i2c_adap_pxa_exit(void)
1186 {
1187 platform_driver_unregister(&i2c_pxa_driver);
1188 }
1189
1190 MODULE_LICENSE("GPL");
1191 MODULE_ALIAS("platform:pxa2xx-i2c");
1192
1193 subsys_initcall(i2c_adap_pxa_init);
1194 module_exit(i2c_adap_pxa_exit);
Linux with added FPC-III support