?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs
[linux/fpc-iii.git] / arch / arm / mach-integrator / integrator_ap.c
blob17c0fe6274357842d2769efc2f0bf2ac5241b982
1 /*
2 * linux/arch/arm/mach-integrator/integrator_ap.c
3 *
4 * Copyright (C) 2000-2003 Deep Blue Solutions Ltd
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include <linux/types.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/list.h>
24 #include <linux/platform_device.h>
25 #include <linux/slab.h>
26 #include <linux/string.h>
27 #include <linux/syscore_ops.h>
28 #include <linux/amba/bus.h>
29 #include <linux/amba/kmi.h>
30 #include <linux/clocksource.h>
31 #include <linux/clockchips.h>
32 #include <linux/interrupt.h>
33 #include <linux/io.h>
34 #include <linux/irqchip/versatile-fpga.h>
35 #include <linux/mtd/physmap.h>
36 #include <linux/clk.h>
37 #include <linux/platform_data/clk-integrator.h>
38 #include <linux/of_irq.h>
39 #include <linux/of_address.h>
40 #include <linux/of_platform.h>
41 #include <linux/stat.h>
42 #include <linux/sys_soc.h>
43 #include <linux/termios.h>
44 #include <linux/sched_clock.h>
45
46 #include <mach/hardware.h>
47 #include <mach/platform.h>
48 #include <asm/hardware/arm_timer.h>
49 #include <asm/setup.h>
50 #include <asm/param.h> /* HZ */
51 #include <asm/mach-types.h>
52
53 #include <mach/lm.h>
54
55 #include <asm/mach/arch.h>
56 #include <asm/mach/irq.h>
57 #include <asm/mach/map.h>
58 #include <asm/mach/time.h>
59
60 #include "cm.h"
61 #include "common.h"
62 #include "pci_v3.h"
63
64 /* Base address to the AP system controller */
65 void __iomem *ap_syscon_base;
66 /* Base address to the external bus interface */
67 static void __iomem *ebi_base;
68
69
70 /*
71 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
72 * is the (PA >> 12).
73 *
74 * Setup a VA for the Integrator interrupt controller (for header #0,
75 * just for now).
76 */
77 #define VA_IC_BASE __io_address(INTEGRATOR_IC_BASE)
78
79 /*
80 * Logical Physical
81 * ef000000 Cache flush
82 * f1100000 11000000 System controller registers
83 * f1300000 13000000 Counter/Timer
84 * f1400000 14000000 Interrupt controller
85 * f1600000 16000000 UART 0
86 * f1700000 17000000 UART 1
87 * f1a00000 1a000000 Debug LEDs
88 * f1b00000 1b000000 GPIO
89 */
90
91 static struct map_desc ap_io_desc[] __initdata __maybe_unused = {
92 {
93 .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
94 .pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
95 .length = SZ_4K,
96 .type = MT_DEVICE
97 }, {
98 .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
99 .pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
100 .length = SZ_4K,
101 .type = MT_DEVICE
102 }, {
103 .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
104 .pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
105 .length = SZ_4K,
106 .type = MT_DEVICE
107 }, {
108 .virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
109 .pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
110 .length = SZ_4K,
111 .type = MT_DEVICE
112 }, {
113 .virtual = IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE),
114 .pfn = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
115 .length = SZ_4K,
116 .type = MT_DEVICE
117 }
118 };
119
120 static void __init ap_map_io(void)
121 {
122 iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
123 pci_v3_early_init();
124 }
125
126 #ifdef CONFIG_PM
127 static unsigned long ic_irq_enable;
128
129 static int irq_suspend(void)
130 {
131 ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
132 return 0;
133 }
134
135 static void irq_resume(void)
136 {
137 /* disable all irq sources */
138 cm_clear_irqs();
139 writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
140 writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
141
142 writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
143 }
144 #else
145 #define irq_suspend NULL
146 #define irq_resume NULL
147 #endif
148
149 static struct syscore_ops irq_syscore_ops = {
150 .suspend = irq_suspend,
151 .resume = irq_resume,
152 };
153
154 static int __init irq_syscore_init(void)
155 {
156 register_syscore_ops(&irq_syscore_ops);
157
158 return 0;
159 }
160
161 device_initcall(irq_syscore_init);
162
163 /*
164 * Flash handling.
165 */
166 static int ap_flash_init(struct platform_device *dev)
167 {
168 u32 tmp;
169
170 writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP,
171 ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
172
173 tmp = readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) |
174 INTEGRATOR_EBI_WRITE_ENABLE;
175 writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
176
177 if (!(readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET)
178 & INTEGRATOR_EBI_WRITE_ENABLE)) {
179 writel(0xa05f, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
180 writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
181 writel(0, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
182 }
183 return 0;
184 }
185
186 static void ap_flash_exit(struct platform_device *dev)
187 {
188 u32 tmp;
189
190 writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP,
191 ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
192
193 tmp = readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) &
194 ~INTEGRATOR_EBI_WRITE_ENABLE;
195 writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
196
197 if (readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) &
198 INTEGRATOR_EBI_WRITE_ENABLE) {
199 writel(0xa05f, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
200 writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
201 writel(0, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
202 }
203 }
204
205 static void ap_flash_set_vpp(struct platform_device *pdev, int on)
206 {
207 if (on)
208 writel(INTEGRATOR_SC_CTRL_nFLVPPEN,
209 ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET);
210 else
211 writel(INTEGRATOR_SC_CTRL_nFLVPPEN,
212 ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
213 }
214
215 static struct physmap_flash_data ap_flash_data = {
216 .width = 4,
217 .init = ap_flash_init,
218 .exit = ap_flash_exit,
219 .set_vpp = ap_flash_set_vpp,
220 };
221
222 /*
223 * For the PL010 found in the Integrator/AP some of the UART control is
224 * implemented in the system controller and accessed using a callback
225 * from the driver.
226 */
227 static void integrator_uart_set_mctrl(struct amba_device *dev,
228 void __iomem *base, unsigned int mctrl)
229 {
230 unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
231 u32 phybase = dev->res.start;
232
233 if (phybase == INTEGRATOR_UART0_BASE) {
234 /* UART0 */
235 rts_mask = 1 << 4;
236 dtr_mask = 1 << 5;
237 } else {
238 /* UART1 */
239 rts_mask = 1 << 6;
240 dtr_mask = 1 << 7;
241 }
242
243 if (mctrl & TIOCM_RTS)
244 ctrlc |= rts_mask;
245 else
246 ctrls |= rts_mask;
247
248 if (mctrl & TIOCM_DTR)
249 ctrlc |= dtr_mask;
250 else
251 ctrls |= dtr_mask;
252
253 __raw_writel(ctrls, ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET);
254 __raw_writel(ctrlc, ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
255 }
256
257 struct amba_pl010_data ap_uart_data = {
258 .set_mctrl = integrator_uart_set_mctrl,
259 };
260
261 /*
262 * Where is the timer (VA)?
263 */
264 #define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
265 #define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
266 #define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)
267
268 static unsigned long timer_reload;
269
270 static u64 notrace integrator_read_sched_clock(void)
271 {
272 return -readl((void __iomem *) TIMER2_VA_BASE + TIMER_VALUE);
273 }
274
275 static void integrator_clocksource_init(unsigned long inrate,
276 void __iomem *base)
277 {
278 u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
279 unsigned long rate = inrate;
280
281 if (rate >= 1500000) {
282 rate /= 16;
283 ctrl |= TIMER_CTRL_DIV16;
284 }
285
286 writel(0xffff, base + TIMER_LOAD);
287 writel(ctrl, base + TIMER_CTRL);
288
289 clocksource_mmio_init(base + TIMER_VALUE, "timer2",
290 rate, 200, 16, clocksource_mmio_readl_down);
291 sched_clock_register(integrator_read_sched_clock, 16, rate);
292 }
293
294 static void __iomem * clkevt_base;
295
296 /*
297 * IRQ handler for the timer
298 */
299 static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
300 {
301 struct clock_event_device *evt = dev_id;
302
303 /* clear the interrupt */
304 writel(1, clkevt_base + TIMER_INTCLR);
305
306 evt->event_handler(evt);
307
308 return IRQ_HANDLED;
309 }
310
311 static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
312 {
313 u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
314
315 /* Disable timer */
316 writel(ctrl, clkevt_base + TIMER_CTRL);
317
318 switch (mode) {
319 case CLOCK_EVT_MODE_PERIODIC:
320 /* Enable the timer and start the periodic tick */
321 writel(timer_reload, clkevt_base + TIMER_LOAD);
322 ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
323 writel(ctrl, clkevt_base + TIMER_CTRL);
324 break;
325 case CLOCK_EVT_MODE_ONESHOT:
326 /* Leave the timer disabled, .set_next_event will enable it */
327 ctrl &= ~TIMER_CTRL_PERIODIC;
328 writel(ctrl, clkevt_base + TIMER_CTRL);
329 break;
330 case CLOCK_EVT_MODE_UNUSED:
331 case CLOCK_EVT_MODE_SHUTDOWN:
332 case CLOCK_EVT_MODE_RESUME:
333 default:
334 /* Just leave in disabled state */
335 break;
336 }
337
338 }
339
340 static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
341 {
342 unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
343
344 writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
345 writel(next, clkevt_base + TIMER_LOAD);
346 writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
347
348 return 0;
349 }
350
351 static struct clock_event_device integrator_clockevent = {
352 .name = "timer1",
353 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
354 .set_mode = clkevt_set_mode,
355 .set_next_event = clkevt_set_next_event,
356 .rating = 300,
357 };
358
359 static struct irqaction integrator_timer_irq = {
360 .name = "timer",
361 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
362 .handler = integrator_timer_interrupt,
363 .dev_id = &integrator_clockevent,
364 };
365
366 static void integrator_clockevent_init(unsigned long inrate,
367 void __iomem *base, int irq)
368 {
369 unsigned long rate = inrate;
370 unsigned int ctrl = 0;
371
372 clkevt_base = base;
373 /* Calculate and program a divisor */
374 if (rate > 0x100000 * HZ) {
375 rate /= 256;
376 ctrl |= TIMER_CTRL_DIV256;
377 } else if (rate > 0x10000 * HZ) {
378 rate /= 16;
379 ctrl |= TIMER_CTRL_DIV16;
380 }
381 timer_reload = rate / HZ;
382 writel(ctrl, clkevt_base + TIMER_CTRL);
383
384 setup_irq(irq, &integrator_timer_irq);
385 clockevents_config_and_register(&integrator_clockevent,
386 rate,
387 1,
388 0xffffU);
389 }
390
391 void __init ap_init_early(void)
392 {
393 }
394
395 static void __init ap_of_timer_init(void)
396 {
397 struct device_node *node;
398 const char *path;
399 void __iomem *base;
400 int err;
401 int irq;
402 struct clk *clk;
403 unsigned long rate;
404
405 clk = clk_get_sys("ap_timer", NULL);
406 BUG_ON(IS_ERR(clk));
407 clk_prepare_enable(clk);
408 rate = clk_get_rate(clk);
409
410 err = of_property_read_string(of_aliases,
411 "arm,timer-primary", &path);
412 if (WARN_ON(err))
413 return;
414 node = of_find_node_by_path(path);
415 base = of_iomap(node, 0);
416 if (WARN_ON(!base))
417 return;
418 writel(0, base + TIMER_CTRL);
419 integrator_clocksource_init(rate, base);
420
421 err = of_property_read_string(of_aliases,
422 "arm,timer-secondary", &path);
423 if (WARN_ON(err))
424 return;
425 node = of_find_node_by_path(path);
426 base = of_iomap(node, 0);
427 if (WARN_ON(!base))
428 return;
429 irq = irq_of_parse_and_map(node, 0);
430 writel(0, base + TIMER_CTRL);
431 integrator_clockevent_init(rate, base, irq);
432 }
433
434 static const struct of_device_id fpga_irq_of_match[] __initconst = {
435 { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
436 { /* Sentinel */ }
437 };
438
439 static void __init ap_init_irq_of(void)
440 {
441 cm_init();
442 of_irq_init(fpga_irq_of_match);
443 integrator_clk_init(false);
444 }
445
446 /* For the Device Tree, add in the UART callbacks as AUXDATA */
447 static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
448 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
449 "rtc", NULL),
450 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
451 "uart0", &ap_uart_data),
452 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
453 "uart1", &ap_uart_data),
454 OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
455 "kmi0", NULL),
456 OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
457 "kmi1", NULL),
458 OF_DEV_AUXDATA("cfi-flash", INTEGRATOR_FLASH_BASE,
459 "physmap-flash", &ap_flash_data),
460 { /* sentinel */ },
461 };
462
463 static const struct of_device_id ap_syscon_match[] = {
464 { .compatible = "arm,integrator-ap-syscon"},
465 { },
466 };
467
468 static const struct of_device_id ebi_match[] = {
469 { .compatible = "arm,external-bus-interface"},
470 { },
471 };
472
473 static void __init ap_init_of(void)
474 {
475 unsigned long sc_dec;
476 struct device_node *root;
477 struct device_node *syscon;
478 struct device_node *ebi;
479 struct device *parent;
480 struct soc_device *soc_dev;
481 struct soc_device_attribute *soc_dev_attr;
482 u32 ap_sc_id;
483 int err;
484 int i;
485
486 /* Here we create an SoC device for the root node */
487 root = of_find_node_by_path("/");
488 if (!root)
489 return;
490
491 syscon = of_find_matching_node(root, ap_syscon_match);
492 if (!syscon)
493 return;
494 ebi = of_find_matching_node(root, ebi_match);
495 if (!ebi)
496 return;
497
498 ap_syscon_base = of_iomap(syscon, 0);
499 if (!ap_syscon_base)
500 return;
501 ebi_base = of_iomap(ebi, 0);
502 if (!ebi_base)
503 return;
504
505 ap_sc_id = readl(ap_syscon_base);
506
507 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
508 if (!soc_dev_attr)
509 return;
510
511 err = of_property_read_string(root, "compatible",
512 &soc_dev_attr->soc_id);
513 if (err)
514 return;
515 err = of_property_read_string(root, "model", &soc_dev_attr->machine);
516 if (err)
517 return;
518 soc_dev_attr->family = "Integrator";
519 soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c",
520 'A' + (ap_sc_id & 0x0f));
521
522 soc_dev = soc_device_register(soc_dev_attr);
523 if (IS_ERR(soc_dev)) {
524 kfree(soc_dev_attr->revision);
525 kfree(soc_dev_attr);
526 return;
527 }
528
529 parent = soc_device_to_device(soc_dev);
530 integrator_init_sysfs(parent, ap_sc_id);
531
532 of_platform_populate(root, of_default_bus_match_table,
533 ap_auxdata_lookup, parent);
534
535 sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET);
536 for (i = 0; i < 4; i++) {
537 struct lm_device *lmdev;
538
539 if ((sc_dec & (16 << i)) == 0)
540 continue;
541
542 lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
543 if (!lmdev)
544 continue;
545
546 lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
547 lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
548 lmdev->resource.flags = IORESOURCE_MEM;
549 lmdev->irq = irq_of_parse_and_map(syscon, i);
550 lmdev->id = i;
551
552 lm_device_register(lmdev);
553 }
554 }
555
556 static const char * ap_dt_board_compat[] = {
557 "arm,integrator-ap",
558 NULL,
559 };
560
561 DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
562 .reserve = integrator_reserve,
563 .map_io = ap_map_io,
564 .init_early = ap_init_early,
565 .init_irq = ap_init_irq_of,
566 .handle_irq = fpga_handle_irq,
567 .init_time = ap_of_timer_init,
568 .init_machine = ap_init_of,
569 .restart = integrator_restart,
570 .dt_compat = ap_dt_board_compat,
571 MACHINE_END
Linux with added FPC-III support