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ocfs2: fix several issues of append dio
[linux/fpc-iii.git] / drivers / scsi / hpsa.c
blob40669f8dd0df12af584c581d71a151386d9155e2
1 /*
2 * Disk Array driver for HP Smart Array SAS controllers
3 * Copyright 2014-2015 PMC-Sierra, Inc.
4 * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more details.
14 *
15 * Questions/Comments/Bugfixes to storagedev@pmcs.com
16 *
17 */
18
19 #include <linux/module.h>
20 #include <linux/interrupt.h>
21 #include <linux/types.h>
22 #include <linux/pci.h>
23 #include <linux/pci-aspm.h>
24 #include <linux/kernel.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/fs.h>
28 #include <linux/timer.h>
29 #include <linux/init.h>
30 #include <linux/spinlock.h>
31 #include <linux/compat.h>
32 #include <linux/blktrace_api.h>
33 #include <linux/uaccess.h>
34 #include <linux/io.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/completion.h>
37 #include <linux/moduleparam.h>
38 #include <scsi/scsi.h>
39 #include <scsi/scsi_cmnd.h>
40 #include <scsi/scsi_device.h>
41 #include <scsi/scsi_host.h>
42 #include <scsi/scsi_tcq.h>
43 #include <scsi/scsi_eh.h>
44 #include <scsi/scsi_dbg.h>
45 #include <linux/cciss_ioctl.h>
46 #include <linux/string.h>
47 #include <linux/bitmap.h>
48 #include <linux/atomic.h>
49 #include <linux/jiffies.h>
50 #include <linux/percpu-defs.h>
51 #include <linux/percpu.h>
52 #include <asm/unaligned.h>
53 #include <asm/div64.h>
54 #include "hpsa_cmd.h"
55 #include "hpsa.h"
56
57 /* HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' */
58 #define HPSA_DRIVER_VERSION "3.4.10-0"
59 #define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
60 #define HPSA "hpsa"
61
62 /* How long to wait for CISS doorbell communication */
63 #define CLEAR_EVENT_WAIT_INTERVAL 20 /* ms for each msleep() call */
64 #define MODE_CHANGE_WAIT_INTERVAL 10 /* ms for each msleep() call */
65 #define MAX_CLEAR_EVENT_WAIT 30000 /* times 20 ms = 600 s */
66 #define MAX_MODE_CHANGE_WAIT 2000 /* times 10 ms = 20 s */
67 #define MAX_IOCTL_CONFIG_WAIT 1000
68
69 /*define how many times we will try a command because of bus resets */
70 #define MAX_CMD_RETRIES 3
71
72 /* Embedded module documentation macros - see modules.h */
73 MODULE_AUTHOR("Hewlett-Packard Company");
74 MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
75 HPSA_DRIVER_VERSION);
76 MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
77 MODULE_VERSION(HPSA_DRIVER_VERSION);
78 MODULE_LICENSE("GPL");
79
80 static int hpsa_allow_any;
81 module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
82 MODULE_PARM_DESC(hpsa_allow_any,
83 "Allow hpsa driver to access unknown HP Smart Array hardware");
84 static int hpsa_simple_mode;
85 module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
86 MODULE_PARM_DESC(hpsa_simple_mode,
87 "Use 'simple mode' rather than 'performant mode'");
88
89 /* define the PCI info for the cards we can control */
90 static const struct pci_device_id hpsa_pci_device_id[] = {
91 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
92 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
93 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
94 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
95 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
101 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
102 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
114 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
115 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
116 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
117 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
118 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
119 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
120 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
121 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
122 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C6},
123 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
124 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
125 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
126 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CA},
127 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CB},
128 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CC},
129 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CD},
130 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CE},
131 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0580},
132 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0581},
133 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0582},
134 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0583},
135 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0584},
136 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0585},
137 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0076},
138 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0087},
139 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x007D},
140 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0088},
141 {PCI_VENDOR_ID_HP, 0x333f, 0x103c, 0x333f},
142 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
143 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
144 {0,}
145 };
146
147 MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
148
149 /* board_id = Subsystem Device ID & Vendor ID
150 * product = Marketing Name for the board
151 * access = Address of the struct of function pointers
152 */
153 static struct board_type products[] = {
154 {0x3241103C, "Smart Array P212", &SA5_access},
155 {0x3243103C, "Smart Array P410", &SA5_access},
156 {0x3245103C, "Smart Array P410i", &SA5_access},
157 {0x3247103C, "Smart Array P411", &SA5_access},
158 {0x3249103C, "Smart Array P812", &SA5_access},
159 {0x324A103C, "Smart Array P712m", &SA5_access},
160 {0x324B103C, "Smart Array P711m", &SA5_access},
161 {0x3233103C, "HP StorageWorks 1210m", &SA5_access}, /* alias of 333f */
162 {0x3350103C, "Smart Array P222", &SA5_access},
163 {0x3351103C, "Smart Array P420", &SA5_access},
164 {0x3352103C, "Smart Array P421", &SA5_access},
165 {0x3353103C, "Smart Array P822", &SA5_access},
166 {0x3354103C, "Smart Array P420i", &SA5_access},
167 {0x3355103C, "Smart Array P220i", &SA5_access},
168 {0x3356103C, "Smart Array P721m", &SA5_access},
169 {0x1921103C, "Smart Array P830i", &SA5_access},
170 {0x1922103C, "Smart Array P430", &SA5_access},
171 {0x1923103C, "Smart Array P431", &SA5_access},
172 {0x1924103C, "Smart Array P830", &SA5_access},
173 {0x1926103C, "Smart Array P731m", &SA5_access},
174 {0x1928103C, "Smart Array P230i", &SA5_access},
175 {0x1929103C, "Smart Array P530", &SA5_access},
176 {0x21BD103C, "Smart Array P244br", &SA5_access},
177 {0x21BE103C, "Smart Array P741m", &SA5_access},
178 {0x21BF103C, "Smart HBA H240ar", &SA5_access},
179 {0x21C0103C, "Smart Array P440ar", &SA5_access},
180 {0x21C1103C, "Smart Array P840ar", &SA5_access},
181 {0x21C2103C, "Smart Array P440", &SA5_access},
182 {0x21C3103C, "Smart Array P441", &SA5_access},
183 {0x21C4103C, "Smart Array", &SA5_access},
184 {0x21C5103C, "Smart Array P841", &SA5_access},
185 {0x21C6103C, "Smart HBA H244br", &SA5_access},
186 {0x21C7103C, "Smart HBA H240", &SA5_access},
187 {0x21C8103C, "Smart HBA H241", &SA5_access},
188 {0x21C9103C, "Smart Array", &SA5_access},
189 {0x21CA103C, "Smart Array P246br", &SA5_access},
190 {0x21CB103C, "Smart Array P840", &SA5_access},
191 {0x21CC103C, "Smart Array", &SA5_access},
192 {0x21CD103C, "Smart Array", &SA5_access},
193 {0x21CE103C, "Smart HBA", &SA5_access},
194 {0x05809005, "SmartHBA-SA", &SA5_access},
195 {0x05819005, "SmartHBA-SA 8i", &SA5_access},
196 {0x05829005, "SmartHBA-SA 8i8e", &SA5_access},
197 {0x05839005, "SmartHBA-SA 8e", &SA5_access},
198 {0x05849005, "SmartHBA-SA 16i", &SA5_access},
199 {0x05859005, "SmartHBA-SA 4i4e", &SA5_access},
200 {0x00761590, "HP Storage P1224 Array Controller", &SA5_access},
201 {0x00871590, "HP Storage P1224e Array Controller", &SA5_access},
202 {0x007D1590, "HP Storage P1228 Array Controller", &SA5_access},
203 {0x00881590, "HP Storage P1228e Array Controller", &SA5_access},
204 {0x333f103c, "HP StorageWorks 1210m Array Controller", &SA5_access},
205 {0xFFFF103C, "Unknown Smart Array", &SA5_access},
206 };
207
208 #define SCSI_CMD_BUSY ((struct scsi_cmnd *)&hpsa_cmd_busy)
209 static const struct scsi_cmnd hpsa_cmd_busy;
210 #define SCSI_CMD_IDLE ((struct scsi_cmnd *)&hpsa_cmd_idle)
211 static const struct scsi_cmnd hpsa_cmd_idle;
212 static int number_of_controllers;
213
214 static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
215 static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
216 static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg);
217
218 #ifdef CONFIG_COMPAT
219 static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd,
220 void __user *arg);
221 #endif
222
223 static void cmd_free(struct ctlr_info *h, struct CommandList *c);
224 static struct CommandList *cmd_alloc(struct ctlr_info *h);
225 static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c);
226 static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h,
227 struct scsi_cmnd *scmd);
228 static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
229 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
230 int cmd_type);
231 static void hpsa_free_cmd_pool(struct ctlr_info *h);
232 #define VPD_PAGE (1 << 8)
233
234 static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
235 static void hpsa_scan_start(struct Scsi_Host *);
236 static int hpsa_scan_finished(struct Scsi_Host *sh,
237 unsigned long elapsed_time);
238 static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth);
239
240 static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
241 static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd);
242 static int hpsa_slave_alloc(struct scsi_device *sdev);
243 static int hpsa_slave_configure(struct scsi_device *sdev);
244 static void hpsa_slave_destroy(struct scsi_device *sdev);
245
246 static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno);
247 static int check_for_unit_attention(struct ctlr_info *h,
248 struct CommandList *c);
249 static void check_ioctl_unit_attention(struct ctlr_info *h,
250 struct CommandList *c);
251 /* performant mode helper functions */
252 static void calc_bucket_map(int *bucket, int num_buckets,
253 int nsgs, int min_blocks, u32 *bucket_map);
254 static void hpsa_free_performant_mode(struct ctlr_info *h);
255 static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
256 static inline u32 next_command(struct ctlr_info *h, u8 q);
257 static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
258 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
259 u64 *cfg_offset);
260 static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
261 unsigned long *memory_bar);
262 static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
263 static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
264 int wait_for_ready);
265 static inline void finish_cmd(struct CommandList *c);
266 static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
267 #define BOARD_NOT_READY 0
268 #define BOARD_READY 1
269 static void hpsa_drain_accel_commands(struct ctlr_info *h);
270 static void hpsa_flush_cache(struct ctlr_info *h);
271 static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
272 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
273 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk);
274 static void hpsa_command_resubmit_worker(struct work_struct *work);
275 static u32 lockup_detected(struct ctlr_info *h);
276 static int detect_controller_lockup(struct ctlr_info *h);
277 static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device);
278
279 static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
280 {
281 unsigned long *priv = shost_priv(sdev->host);
282 return (struct ctlr_info *) *priv;
283 }
284
285 static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
286 {
287 unsigned long *priv = shost_priv(sh);
288 return (struct ctlr_info *) *priv;
289 }
290
291 static inline bool hpsa_is_cmd_idle(struct CommandList *c)
292 {
293 return c->scsi_cmd == SCSI_CMD_IDLE;
294 }
295
296 static inline bool hpsa_is_pending_event(struct CommandList *c)
297 {
298 return c->abort_pending || c->reset_pending;
299 }
300
301 /* extract sense key, asc, and ascq from sense data. -1 means invalid. */
302 static void decode_sense_data(const u8 *sense_data, int sense_data_len,
303 u8 *sense_key, u8 *asc, u8 *ascq)
304 {
305 struct scsi_sense_hdr sshdr;
306 bool rc;
307
308 *sense_key = -1;
309 *asc = -1;
310 *ascq = -1;
311
312 if (sense_data_len < 1)
313 return;
314
315 rc = scsi_normalize_sense(sense_data, sense_data_len, &sshdr);
316 if (rc) {
317 *sense_key = sshdr.sense_key;
318 *asc = sshdr.asc;
319 *ascq = sshdr.ascq;
320 }
321 }
322
323 static int check_for_unit_attention(struct ctlr_info *h,
324 struct CommandList *c)
325 {
326 u8 sense_key, asc, ascq;
327 int sense_len;
328
329 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
330 sense_len = sizeof(c->err_info->SenseInfo);
331 else
332 sense_len = c->err_info->SenseLen;
333
334 decode_sense_data(c->err_info->SenseInfo, sense_len,
335 &sense_key, &asc, &ascq);
336 if (sense_key != UNIT_ATTENTION || asc == 0xff)
337 return 0;
338
339 switch (asc) {
340 case STATE_CHANGED:
341 dev_warn(&h->pdev->dev,
342 "%s: a state change detected, command retried\n",
343 h->devname);
344 break;
345 case LUN_FAILED:
346 dev_warn(&h->pdev->dev,
347 "%s: LUN failure detected\n", h->devname);
348 break;
349 case REPORT_LUNS_CHANGED:
350 dev_warn(&h->pdev->dev,
351 "%s: report LUN data changed\n", h->devname);
352 /*
353 * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
354 * target (array) devices.
355 */
356 break;
357 case POWER_OR_RESET:
358 dev_warn(&h->pdev->dev,
359 "%s: a power on or device reset detected\n",
360 h->devname);
361 break;
362 case UNIT_ATTENTION_CLEARED:
363 dev_warn(&h->pdev->dev,
364 "%s: unit attention cleared by another initiator\n",
365 h->devname);
366 break;
367 default:
368 dev_warn(&h->pdev->dev,
369 "%s: unknown unit attention detected\n",
370 h->devname);
371 break;
372 }
373 return 1;
374 }
375
376 static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
377 {
378 if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
379 (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
380 c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
381 return 0;
382 dev_warn(&h->pdev->dev, HPSA "device busy");
383 return 1;
384 }
385
386 static u32 lockup_detected(struct ctlr_info *h);
387 static ssize_t host_show_lockup_detected(struct device *dev,
388 struct device_attribute *attr, char *buf)
389 {
390 int ld;
391 struct ctlr_info *h;
392 struct Scsi_Host *shost = class_to_shost(dev);
393
394 h = shost_to_hba(shost);
395 ld = lockup_detected(h);
396
397 return sprintf(buf, "ld=%d\n", ld);
398 }
399
400 static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev,
401 struct device_attribute *attr,
402 const char *buf, size_t count)
403 {
404 int status, len;
405 struct ctlr_info *h;
406 struct Scsi_Host *shost = class_to_shost(dev);
407 char tmpbuf[10];
408
409 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
410 return -EACCES;
411 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
412 strncpy(tmpbuf, buf, len);
413 tmpbuf[len] = '\0';
414 if (sscanf(tmpbuf, "%d", &status) != 1)
415 return -EINVAL;
416 h = shost_to_hba(shost);
417 h->acciopath_status = !!status;
418 dev_warn(&h->pdev->dev,
419 "hpsa: HP SSD Smart Path %s via sysfs update.\n",
420 h->acciopath_status ? "enabled" : "disabled");
421 return count;
422 }
423
424 static ssize_t host_store_raid_offload_debug(struct device *dev,
425 struct device_attribute *attr,
426 const char *buf, size_t count)
427 {
428 int debug_level, len;
429 struct ctlr_info *h;
430 struct Scsi_Host *shost = class_to_shost(dev);
431 char tmpbuf[10];
432
433 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
434 return -EACCES;
435 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
436 strncpy(tmpbuf, buf, len);
437 tmpbuf[len] = '\0';
438 if (sscanf(tmpbuf, "%d", &debug_level) != 1)
439 return -EINVAL;
440 if (debug_level < 0)
441 debug_level = 0;
442 h = shost_to_hba(shost);
443 h->raid_offload_debug = debug_level;
444 dev_warn(&h->pdev->dev, "hpsa: Set raid_offload_debug level = %d\n",
445 h->raid_offload_debug);
446 return count;
447 }
448
449 static ssize_t host_store_rescan(struct device *dev,
450 struct device_attribute *attr,
451 const char *buf, size_t count)
452 {
453 struct ctlr_info *h;
454 struct Scsi_Host *shost = class_to_shost(dev);
455 h = shost_to_hba(shost);
456 hpsa_scan_start(h->scsi_host);
457 return count;
458 }
459
460 static ssize_t host_show_firmware_revision(struct device *dev,
461 struct device_attribute *attr, char *buf)
462 {
463 struct ctlr_info *h;
464 struct Scsi_Host *shost = class_to_shost(dev);
465 unsigned char *fwrev;
466
467 h = shost_to_hba(shost);
468 if (!h->hba_inquiry_data)
469 return 0;
470 fwrev = &h->hba_inquiry_data[32];
471 return snprintf(buf, 20, "%c%c%c%c\n",
472 fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
473 }
474
475 static ssize_t host_show_commands_outstanding(struct device *dev,
476 struct device_attribute *attr, char *buf)
477 {
478 struct Scsi_Host *shost = class_to_shost(dev);
479 struct ctlr_info *h = shost_to_hba(shost);
480
481 return snprintf(buf, 20, "%d\n",
482 atomic_read(&h->commands_outstanding));
483 }
484
485 static ssize_t host_show_transport_mode(struct device *dev,
486 struct device_attribute *attr, char *buf)
487 {
488 struct ctlr_info *h;
489 struct Scsi_Host *shost = class_to_shost(dev);
490
491 h = shost_to_hba(shost);
492 return snprintf(buf, 20, "%s\n",
493 h->transMethod & CFGTBL_Trans_Performant ?
494 "performant" : "simple");
495 }
496
497 static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev,
498 struct device_attribute *attr, char *buf)
499 {
500 struct ctlr_info *h;
501 struct Scsi_Host *shost = class_to_shost(dev);
502
503 h = shost_to_hba(shost);
504 return snprintf(buf, 30, "HP SSD Smart Path %s\n",
505 (h->acciopath_status == 1) ? "enabled" : "disabled");
506 }
507
508 /* List of controllers which cannot be hard reset on kexec with reset_devices */
509 static u32 unresettable_controller[] = {
510 0x324a103C, /* Smart Array P712m */
511 0x324b103C, /* Smart Array P711m */
512 0x3223103C, /* Smart Array P800 */
513 0x3234103C, /* Smart Array P400 */
514 0x3235103C, /* Smart Array P400i */
515 0x3211103C, /* Smart Array E200i */
516 0x3212103C, /* Smart Array E200 */
517 0x3213103C, /* Smart Array E200i */
518 0x3214103C, /* Smart Array E200i */
519 0x3215103C, /* Smart Array E200i */
520 0x3237103C, /* Smart Array E500 */
521 0x323D103C, /* Smart Array P700m */
522 0x40800E11, /* Smart Array 5i */
523 0x409C0E11, /* Smart Array 6400 */
524 0x409D0E11, /* Smart Array 6400 EM */
525 0x40700E11, /* Smart Array 5300 */
526 0x40820E11, /* Smart Array 532 */
527 0x40830E11, /* Smart Array 5312 */
528 0x409A0E11, /* Smart Array 641 */
529 0x409B0E11, /* Smart Array 642 */
530 0x40910E11, /* Smart Array 6i */
531 };
532
533 /* List of controllers which cannot even be soft reset */
534 static u32 soft_unresettable_controller[] = {
535 0x40800E11, /* Smart Array 5i */
536 0x40700E11, /* Smart Array 5300 */
537 0x40820E11, /* Smart Array 532 */
538 0x40830E11, /* Smart Array 5312 */
539 0x409A0E11, /* Smart Array 641 */
540 0x409B0E11, /* Smart Array 642 */
541 0x40910E11, /* Smart Array 6i */
542 /* Exclude 640x boards. These are two pci devices in one slot
543 * which share a battery backed cache module. One controls the
544 * cache, the other accesses the cache through the one that controls
545 * it. If we reset the one controlling the cache, the other will
546 * likely not be happy. Just forbid resetting this conjoined mess.
547 * The 640x isn't really supported by hpsa anyway.
548 */
549 0x409C0E11, /* Smart Array 6400 */
550 0x409D0E11, /* Smart Array 6400 EM */
551 };
552
553 static u32 needs_abort_tags_swizzled[] = {
554 0x323D103C, /* Smart Array P700m */
555 0x324a103C, /* Smart Array P712m */
556 0x324b103C, /* SmartArray P711m */
557 };
558
559 static int board_id_in_array(u32 a[], int nelems, u32 board_id)
560 {
561 int i;
562
563 for (i = 0; i < nelems; i++)
564 if (a[i] == board_id)
565 return 1;
566 return 0;
567 }
568
569 static int ctlr_is_hard_resettable(u32 board_id)
570 {
571 return !board_id_in_array(unresettable_controller,
572 ARRAY_SIZE(unresettable_controller), board_id);
573 }
574
575 static int ctlr_is_soft_resettable(u32 board_id)
576 {
577 return !board_id_in_array(soft_unresettable_controller,
578 ARRAY_SIZE(soft_unresettable_controller), board_id);
579 }
580
581 static int ctlr_is_resettable(u32 board_id)
582 {
583 return ctlr_is_hard_resettable(board_id) ||
584 ctlr_is_soft_resettable(board_id);
585 }
586
587 static int ctlr_needs_abort_tags_swizzled(u32 board_id)
588 {
589 return board_id_in_array(needs_abort_tags_swizzled,
590 ARRAY_SIZE(needs_abort_tags_swizzled), board_id);
591 }
592
593 static ssize_t host_show_resettable(struct device *dev,
594 struct device_attribute *attr, char *buf)
595 {
596 struct ctlr_info *h;
597 struct Scsi_Host *shost = class_to_shost(dev);
598
599 h = shost_to_hba(shost);
600 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
601 }
602
603 static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
604 {
605 return (scsi3addr[3] & 0xC0) == 0x40;
606 }
607
608 static const char * const raid_label[] = { "0", "4", "1(+0)", "5", "5+1", "6",
609 "1(+0)ADM", "UNKNOWN"
610 };
611 #define HPSA_RAID_0 0
612 #define HPSA_RAID_4 1
613 #define HPSA_RAID_1 2 /* also used for RAID 10 */
614 #define HPSA_RAID_5 3 /* also used for RAID 50 */
615 #define HPSA_RAID_51 4
616 #define HPSA_RAID_6 5 /* also used for RAID 60 */
617 #define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */
618 #define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 1)
619
620 static ssize_t raid_level_show(struct device *dev,
621 struct device_attribute *attr, char *buf)
622 {
623 ssize_t l = 0;
624 unsigned char rlevel;
625 struct ctlr_info *h;
626 struct scsi_device *sdev;
627 struct hpsa_scsi_dev_t *hdev;
628 unsigned long flags;
629
630 sdev = to_scsi_device(dev);
631 h = sdev_to_hba(sdev);
632 spin_lock_irqsave(&h->lock, flags);
633 hdev = sdev->hostdata;
634 if (!hdev) {
635 spin_unlock_irqrestore(&h->lock, flags);
636 return -ENODEV;
637 }
638
639 /* Is this even a logical drive? */
640 if (!is_logical_dev_addr_mode(hdev->scsi3addr)) {
641 spin_unlock_irqrestore(&h->lock, flags);
642 l = snprintf(buf, PAGE_SIZE, "N/A\n");
643 return l;
644 }
645
646 rlevel = hdev->raid_level;
647 spin_unlock_irqrestore(&h->lock, flags);
648 if (rlevel > RAID_UNKNOWN)
649 rlevel = RAID_UNKNOWN;
650 l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
651 return l;
652 }
653
654 static ssize_t lunid_show(struct device *dev,
655 struct device_attribute *attr, char *buf)
656 {
657 struct ctlr_info *h;
658 struct scsi_device *sdev;
659 struct hpsa_scsi_dev_t *hdev;
660 unsigned long flags;
661 unsigned char lunid[8];
662
663 sdev = to_scsi_device(dev);
664 h = sdev_to_hba(sdev);
665 spin_lock_irqsave(&h->lock, flags);
666 hdev = sdev->hostdata;
667 if (!hdev) {
668 spin_unlock_irqrestore(&h->lock, flags);
669 return -ENODEV;
670 }
671 memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
672 spin_unlock_irqrestore(&h->lock, flags);
673 return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
674 lunid[0], lunid[1], lunid[2], lunid[3],
675 lunid[4], lunid[5], lunid[6], lunid[7]);
676 }
677
678 static ssize_t unique_id_show(struct device *dev,
679 struct device_attribute *attr, char *buf)
680 {
681 struct ctlr_info *h;
682 struct scsi_device *sdev;
683 struct hpsa_scsi_dev_t *hdev;
684 unsigned long flags;
685 unsigned char sn[16];
686
687 sdev = to_scsi_device(dev);
688 h = sdev_to_hba(sdev);
689 spin_lock_irqsave(&h->lock, flags);
690 hdev = sdev->hostdata;
691 if (!hdev) {
692 spin_unlock_irqrestore(&h->lock, flags);
693 return -ENODEV;
694 }
695 memcpy(sn, hdev->device_id, sizeof(sn));
696 spin_unlock_irqrestore(&h->lock, flags);
697 return snprintf(buf, 16 * 2 + 2,
698 "%02X%02X%02X%02X%02X%02X%02X%02X"
699 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
700 sn[0], sn[1], sn[2], sn[3],
701 sn[4], sn[5], sn[6], sn[7],
702 sn[8], sn[9], sn[10], sn[11],
703 sn[12], sn[13], sn[14], sn[15]);
704 }
705
706 static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev,
707 struct device_attribute *attr, char *buf)
708 {
709 struct ctlr_info *h;
710 struct scsi_device *sdev;
711 struct hpsa_scsi_dev_t *hdev;
712 unsigned long flags;
713 int offload_enabled;
714
715 sdev = to_scsi_device(dev);
716 h = sdev_to_hba(sdev);
717 spin_lock_irqsave(&h->lock, flags);
718 hdev = sdev->hostdata;
719 if (!hdev) {
720 spin_unlock_irqrestore(&h->lock, flags);
721 return -ENODEV;
722 }
723 offload_enabled = hdev->offload_enabled;
724 spin_unlock_irqrestore(&h->lock, flags);
725 return snprintf(buf, 20, "%d\n", offload_enabled);
726 }
727
728 #define MAX_PATHS 8
729 #define PATH_STRING_LEN 50
730
731 static ssize_t path_info_show(struct device *dev,
732 struct device_attribute *attr, char *buf)
733 {
734 struct ctlr_info *h;
735 struct scsi_device *sdev;
736 struct hpsa_scsi_dev_t *hdev;
737 unsigned long flags;
738 int i;
739 int output_len = 0;
740 u8 box;
741 u8 bay;
742 u8 path_map_index = 0;
743 char *active;
744 unsigned char phys_connector[2];
745 unsigned char path[MAX_PATHS][PATH_STRING_LEN];
746
747 memset(path, 0, MAX_PATHS * PATH_STRING_LEN);
748 sdev = to_scsi_device(dev);
749 h = sdev_to_hba(sdev);
750 spin_lock_irqsave(&h->devlock, flags);
751 hdev = sdev->hostdata;
752 if (!hdev) {
753 spin_unlock_irqrestore(&h->devlock, flags);
754 return -ENODEV;
755 }
756
757 bay = hdev->bay;
758 for (i = 0; i < MAX_PATHS; i++) {
759 path_map_index = 1<<i;
760 if (i == hdev->active_path_index)
761 active = "Active";
762 else if (hdev->path_map & path_map_index)
763 active = "Inactive";
764 else
765 continue;
766
767 output_len = snprintf(path[i],
768 PATH_STRING_LEN, "[%d:%d:%d:%d] %20.20s ",
769 h->scsi_host->host_no,
770 hdev->bus, hdev->target, hdev->lun,
771 scsi_device_type(hdev->devtype));
772
773 if (is_ext_target(h, hdev) ||
774 (hdev->devtype == TYPE_RAID) ||
775 is_logical_dev_addr_mode(hdev->scsi3addr)) {
776 output_len += snprintf(path[i] + output_len,
777 PATH_STRING_LEN, "%s\n",
778 active);
779 continue;
780 }
781
782 box = hdev->box[i];
783 memcpy(&phys_connector, &hdev->phys_connector[i],
784 sizeof(phys_connector));
785 if (phys_connector[0] < '0')
786 phys_connector[0] = '0';
787 if (phys_connector[1] < '0')
788 phys_connector[1] = '0';
789 if (hdev->phys_connector[i] > 0)
790 output_len += snprintf(path[i] + output_len,
791 PATH_STRING_LEN,
792 "PORT: %.2s ",
793 phys_connector);
794 if (hdev->devtype == TYPE_DISK &&
795 hdev->expose_state != HPSA_DO_NOT_EXPOSE) {
796 if (box == 0 || box == 0xFF) {
797 output_len += snprintf(path[i] + output_len,
798 PATH_STRING_LEN,
799 "BAY: %hhu %s\n",
800 bay, active);
801 } else {
802 output_len += snprintf(path[i] + output_len,
803 PATH_STRING_LEN,
804 "BOX: %hhu BAY: %hhu %s\n",
805 box, bay, active);
806 }
807 } else if (box != 0 && box != 0xFF) {
808 output_len += snprintf(path[i] + output_len,
809 PATH_STRING_LEN, "BOX: %hhu %s\n",
810 box, active);
811 } else
812 output_len += snprintf(path[i] + output_len,
813 PATH_STRING_LEN, "%s\n", active);
814 }
815
816 spin_unlock_irqrestore(&h->devlock, flags);
817 return snprintf(buf, output_len+1, "%s%s%s%s%s%s%s%s",
818 path[0], path[1], path[2], path[3],
819 path[4], path[5], path[6], path[7]);
820 }
821
822 static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
823 static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
824 static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
825 static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
826 static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO,
827 host_show_hp_ssd_smart_path_enabled, NULL);
828 static DEVICE_ATTR(path_info, S_IRUGO, path_info_show, NULL);
829 static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH,
830 host_show_hp_ssd_smart_path_status,
831 host_store_hp_ssd_smart_path_status);
832 static DEVICE_ATTR(raid_offload_debug, S_IWUSR, NULL,
833 host_store_raid_offload_debug);
834 static DEVICE_ATTR(firmware_revision, S_IRUGO,
835 host_show_firmware_revision, NULL);
836 static DEVICE_ATTR(commands_outstanding, S_IRUGO,
837 host_show_commands_outstanding, NULL);
838 static DEVICE_ATTR(transport_mode, S_IRUGO,
839 host_show_transport_mode, NULL);
840 static DEVICE_ATTR(resettable, S_IRUGO,
841 host_show_resettable, NULL);
842 static DEVICE_ATTR(lockup_detected, S_IRUGO,
843 host_show_lockup_detected, NULL);
844
845 static struct device_attribute *hpsa_sdev_attrs[] = {
846 &dev_attr_raid_level,
847 &dev_attr_lunid,
848 &dev_attr_unique_id,
849 &dev_attr_hp_ssd_smart_path_enabled,
850 &dev_attr_path_info,
851 &dev_attr_lockup_detected,
852 NULL,
853 };
854
855 static struct device_attribute *hpsa_shost_attrs[] = {
856 &dev_attr_rescan,
857 &dev_attr_firmware_revision,
858 &dev_attr_commands_outstanding,
859 &dev_attr_transport_mode,
860 &dev_attr_resettable,
861 &dev_attr_hp_ssd_smart_path_status,
862 &dev_attr_raid_offload_debug,
863 NULL,
864 };
865
866 #define HPSA_NRESERVED_CMDS (HPSA_CMDS_RESERVED_FOR_ABORTS + \
867 HPSA_CMDS_RESERVED_FOR_DRIVER + HPSA_MAX_CONCURRENT_PASSTHRUS)
868
869 static struct scsi_host_template hpsa_driver_template = {
870 .module = THIS_MODULE,
871 .name = HPSA,
872 .proc_name = HPSA,
873 .queuecommand = hpsa_scsi_queue_command,
874 .scan_start = hpsa_scan_start,
875 .scan_finished = hpsa_scan_finished,
876 .change_queue_depth = hpsa_change_queue_depth,
877 .this_id = -1,
878 .use_clustering = ENABLE_CLUSTERING,
879 .eh_abort_handler = hpsa_eh_abort_handler,
880 .eh_device_reset_handler = hpsa_eh_device_reset_handler,
881 .ioctl = hpsa_ioctl,
882 .slave_alloc = hpsa_slave_alloc,
883 .slave_configure = hpsa_slave_configure,
884 .slave_destroy = hpsa_slave_destroy,
885 #ifdef CONFIG_COMPAT
886 .compat_ioctl = hpsa_compat_ioctl,
887 #endif
888 .sdev_attrs = hpsa_sdev_attrs,
889 .shost_attrs = hpsa_shost_attrs,
890 .max_sectors = 8192,
891 .no_write_same = 1,
892 };
893
894 static inline u32 next_command(struct ctlr_info *h, u8 q)
895 {
896 u32 a;
897 struct reply_queue_buffer *rq = &h->reply_queue[q];
898
899 if (h->transMethod & CFGTBL_Trans_io_accel1)
900 return h->access.command_completed(h, q);
901
902 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
903 return h->access.command_completed(h, q);
904
905 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
906 a = rq->head[rq->current_entry];
907 rq->current_entry++;
908 atomic_dec(&h->commands_outstanding);
909 } else {
910 a = FIFO_EMPTY;
911 }
912 /* Check for wraparound */
913 if (rq->current_entry == h->max_commands) {
914 rq->current_entry = 0;
915 rq->wraparound ^= 1;
916 }
917 return a;
918 }
919
920 /*
921 * There are some special bits in the bus address of the
922 * command that we have to set for the controller to know
923 * how to process the command:
924 *
925 * Normal performant mode:
926 * bit 0: 1 means performant mode, 0 means simple mode.
927 * bits 1-3 = block fetch table entry
928 * bits 4-6 = command type (== 0)
929 *
930 * ioaccel1 mode:
931 * bit 0 = "performant mode" bit.
932 * bits 1-3 = block fetch table entry
933 * bits 4-6 = command type (== 110)
934 * (command type is needed because ioaccel1 mode
935 * commands are submitted through the same register as normal
936 * mode commands, so this is how the controller knows whether
937 * the command is normal mode or ioaccel1 mode.)
938 *
939 * ioaccel2 mode:
940 * bit 0 = "performant mode" bit.
941 * bits 1-4 = block fetch table entry (note extra bit)
942 * bits 4-6 = not needed, because ioaccel2 mode has
943 * a separate special register for submitting commands.
944 */
945
946 /*
947 * set_performant_mode: Modify the tag for cciss performant
948 * set bit 0 for pull model, bits 3-1 for block fetch
949 * register number
950 */
951 #define DEFAULT_REPLY_QUEUE (-1)
952 static void set_performant_mode(struct ctlr_info *h, struct CommandList *c,
953 int reply_queue)
954 {
955 if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
956 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
957 if (unlikely(!h->msix_vector))
958 return;
959 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
960 c->Header.ReplyQueue =
961 raw_smp_processor_id() % h->nreply_queues;
962 else
963 c->Header.ReplyQueue = reply_queue % h->nreply_queues;
964 }
965 }
966
967 static void set_ioaccel1_performant_mode(struct ctlr_info *h,
968 struct CommandList *c,
969 int reply_queue)
970 {
971 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
972
973 /*
974 * Tell the controller to post the reply to the queue for this
975 * processor. This seems to give the best I/O throughput.
976 */
977 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
978 cp->ReplyQueue = smp_processor_id() % h->nreply_queues;
979 else
980 cp->ReplyQueue = reply_queue % h->nreply_queues;
981 /*
982 * Set the bits in the address sent down to include:
983 * - performant mode bit (bit 0)
984 * - pull count (bits 1-3)
985 * - command type (bits 4-6)
986 */
987 c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) |
988 IOACCEL1_BUSADDR_CMDTYPE;
989 }
990
991 static void set_ioaccel2_tmf_performant_mode(struct ctlr_info *h,
992 struct CommandList *c,
993 int reply_queue)
994 {
995 struct hpsa_tmf_struct *cp = (struct hpsa_tmf_struct *)
996 &h->ioaccel2_cmd_pool[c->cmdindex];
997
998 /* Tell the controller to post the reply to the queue for this
999 * processor. This seems to give the best I/O throughput.
1000 */
1001 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
1002 cp->reply_queue = smp_processor_id() % h->nreply_queues;
1003 else
1004 cp->reply_queue = reply_queue % h->nreply_queues;
1005 /* Set the bits in the address sent down to include:
1006 * - performant mode bit not used in ioaccel mode 2
1007 * - pull count (bits 0-3)
1008 * - command type isn't needed for ioaccel2
1009 */
1010 c->busaddr |= h->ioaccel2_blockFetchTable[0];
1011 }
1012
1013 static void set_ioaccel2_performant_mode(struct ctlr_info *h,
1014 struct CommandList *c,
1015 int reply_queue)
1016 {
1017 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
1018
1019 /*
1020 * Tell the controller to post the reply to the queue for this
1021 * processor. This seems to give the best I/O throughput.
1022 */
1023 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
1024 cp->reply_queue = smp_processor_id() % h->nreply_queues;
1025 else
1026 cp->reply_queue = reply_queue % h->nreply_queues;
1027 /*
1028 * Set the bits in the address sent down to include:
1029 * - performant mode bit not used in ioaccel mode 2
1030 * - pull count (bits 0-3)
1031 * - command type isn't needed for ioaccel2
1032 */
1033 c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]);
1034 }
1035
1036 static int is_firmware_flash_cmd(u8 *cdb)
1037 {
1038 return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
1039 }
1040
1041 /*
1042 * During firmware flash, the heartbeat register may not update as frequently
1043 * as it should. So we dial down lockup detection during firmware flash. and
1044 * dial it back up when firmware flash completes.
1045 */
1046 #define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
1047 #define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
1048 static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
1049 struct CommandList *c)
1050 {
1051 if (!is_firmware_flash_cmd(c->Request.CDB))
1052 return;
1053 atomic_inc(&h->firmware_flash_in_progress);
1054 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
1055 }
1056
1057 static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
1058 struct CommandList *c)
1059 {
1060 if (is_firmware_flash_cmd(c->Request.CDB) &&
1061 atomic_dec_and_test(&h->firmware_flash_in_progress))
1062 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
1063 }
1064
1065 static void __enqueue_cmd_and_start_io(struct ctlr_info *h,
1066 struct CommandList *c, int reply_queue)
1067 {
1068 dial_down_lockup_detection_during_fw_flash(h, c);
1069 atomic_inc(&h->commands_outstanding);
1070 switch (c->cmd_type) {
1071 case CMD_IOACCEL1:
1072 set_ioaccel1_performant_mode(h, c, reply_queue);
1073 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
1074 break;
1075 case CMD_IOACCEL2:
1076 set_ioaccel2_performant_mode(h, c, reply_queue);
1077 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
1078 break;
1079 case IOACCEL2_TMF:
1080 set_ioaccel2_tmf_performant_mode(h, c, reply_queue);
1081 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
1082 break;
1083 default:
1084 set_performant_mode(h, c, reply_queue);
1085 h->access.submit_command(h, c);
1086 }
1087 }
1088
1089 static void enqueue_cmd_and_start_io(struct ctlr_info *h, struct CommandList *c)
1090 {
1091 if (unlikely(hpsa_is_pending_event(c)))
1092 return finish_cmd(c);
1093
1094 __enqueue_cmd_and_start_io(h, c, DEFAULT_REPLY_QUEUE);
1095 }
1096
1097 static inline int is_hba_lunid(unsigned char scsi3addr[])
1098 {
1099 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
1100 }
1101
1102 static inline int is_scsi_rev_5(struct ctlr_info *h)
1103 {
1104 if (!h->hba_inquiry_data)
1105 return 0;
1106 if ((h->hba_inquiry_data[2] & 0x07) == 5)
1107 return 1;
1108 return 0;
1109 }
1110
1111 static int hpsa_find_target_lun(struct ctlr_info *h,
1112 unsigned char scsi3addr[], int bus, int *target, int *lun)
1113 {
1114 /* finds an unused bus, target, lun for a new physical device
1115 * assumes h->devlock is held
1116 */
1117 int i, found = 0;
1118 DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
1119
1120 bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
1121
1122 for (i = 0; i < h->ndevices; i++) {
1123 if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
1124 __set_bit(h->dev[i]->target, lun_taken);
1125 }
1126
1127 i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
1128 if (i < HPSA_MAX_DEVICES) {
1129 /* *bus = 1; */
1130 *target = i;
1131 *lun = 0;
1132 found = 1;
1133 }
1134 return !found;
1135 }
1136
1137 static inline void hpsa_show_dev_msg(const char *level, struct ctlr_info *h,
1138 struct hpsa_scsi_dev_t *dev, char *description)
1139 {
1140 dev_printk(level, &h->pdev->dev,
1141 "scsi %d:%d:%d:%d: %s %s %.8s %.16s RAID-%s SSDSmartPathCap%c En%c Exp=%d\n",
1142 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
1143 description,
1144 scsi_device_type(dev->devtype),
1145 dev->vendor,
1146 dev->model,
1147 dev->raid_level > RAID_UNKNOWN ?
1148 "RAID-?" : raid_label[dev->raid_level],
1149 dev->offload_config ? '+' : '-',
1150 dev->offload_enabled ? '+' : '-',
1151 dev->expose_state);
1152 }
1153
1154 /* Add an entry into h->dev[] array. */
1155 static int hpsa_scsi_add_entry(struct ctlr_info *h, int hostno,
1156 struct hpsa_scsi_dev_t *device,
1157 struct hpsa_scsi_dev_t *added[], int *nadded)
1158 {
1159 /* assumes h->devlock is held */
1160 int n = h->ndevices;
1161 int i;
1162 unsigned char addr1[8], addr2[8];
1163 struct hpsa_scsi_dev_t *sd;
1164
1165 if (n >= HPSA_MAX_DEVICES) {
1166 dev_err(&h->pdev->dev, "too many devices, some will be "
1167 "inaccessible.\n");
1168 return -1;
1169 }
1170
1171 /* physical devices do not have lun or target assigned until now. */
1172 if (device->lun != -1)
1173 /* Logical device, lun is already assigned. */
1174 goto lun_assigned;
1175
1176 /* If this device a non-zero lun of a multi-lun device
1177 * byte 4 of the 8-byte LUN addr will contain the logical
1178 * unit no, zero otherwise.
1179 */
1180 if (device->scsi3addr[4] == 0) {
1181 /* This is not a non-zero lun of a multi-lun device */
1182 if (hpsa_find_target_lun(h, device->scsi3addr,
1183 device->bus, &device->target, &device->lun) != 0)
1184 return -1;
1185 goto lun_assigned;
1186 }
1187
1188 /* This is a non-zero lun of a multi-lun device.
1189 * Search through our list and find the device which
1190 * has the same 8 byte LUN address, excepting byte 4 and 5.
1191 * Assign the same bus and target for this new LUN.
1192 * Use the logical unit number from the firmware.
1193 */
1194 memcpy(addr1, device->scsi3addr, 8);
1195 addr1[4] = 0;
1196 addr1[5] = 0;
1197 for (i = 0; i < n; i++) {
1198 sd = h->dev[i];
1199 memcpy(addr2, sd->scsi3addr, 8);
1200 addr2[4] = 0;
1201 addr2[5] = 0;
1202 /* differ only in byte 4 and 5? */
1203 if (memcmp(addr1, addr2, 8) == 0) {
1204 device->bus = sd->bus;
1205 device->target = sd->target;
1206 device->lun = device->scsi3addr[4];
1207 break;
1208 }
1209 }
1210 if (device->lun == -1) {
1211 dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
1212 " suspect firmware bug or unsupported hardware "
1213 "configuration.\n");
1214 return -1;
1215 }
1216
1217 lun_assigned:
1218
1219 h->dev[n] = device;
1220 h->ndevices++;
1221 added[*nadded] = device;
1222 (*nadded)++;
1223 hpsa_show_dev_msg(KERN_INFO, h, device,
1224 device->expose_state & HPSA_SCSI_ADD ? "added" : "masked");
1225 device->offload_to_be_enabled = device->offload_enabled;
1226 device->offload_enabled = 0;
1227 return 0;
1228 }
1229
1230 /* Update an entry in h->dev[] array. */
1231 static void hpsa_scsi_update_entry(struct ctlr_info *h, int hostno,
1232 int entry, struct hpsa_scsi_dev_t *new_entry)
1233 {
1234 int offload_enabled;
1235 /* assumes h->devlock is held */
1236 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
1237
1238 /* Raid level changed. */
1239 h->dev[entry]->raid_level = new_entry->raid_level;
1240
1241 /* Raid offload parameters changed. Careful about the ordering. */
1242 if (new_entry->offload_config && new_entry->offload_enabled) {
1243 /*
1244 * if drive is newly offload_enabled, we want to copy the
1245 * raid map data first. If previously offload_enabled and
1246 * offload_config were set, raid map data had better be
1247 * the same as it was before. if raid map data is changed
1248 * then it had better be the case that
1249 * h->dev[entry]->offload_enabled is currently 0.
1250 */
1251 h->dev[entry]->raid_map = new_entry->raid_map;
1252 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
1253 }
1254 if (new_entry->hba_ioaccel_enabled) {
1255 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
1256 wmb(); /* set ioaccel_handle *before* hba_ioaccel_enabled */
1257 }
1258 h->dev[entry]->hba_ioaccel_enabled = new_entry->hba_ioaccel_enabled;
1259 h->dev[entry]->offload_config = new_entry->offload_config;
1260 h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror;
1261 h->dev[entry]->queue_depth = new_entry->queue_depth;
1262
1263 /*
1264 * We can turn off ioaccel offload now, but need to delay turning
1265 * it on until we can update h->dev[entry]->phys_disk[], but we
1266 * can't do that until all the devices are updated.
1267 */
1268 h->dev[entry]->offload_to_be_enabled = new_entry->offload_enabled;
1269 if (!new_entry->offload_enabled)
1270 h->dev[entry]->offload_enabled = 0;
1271
1272 offload_enabled = h->dev[entry]->offload_enabled;
1273 h->dev[entry]->offload_enabled = h->dev[entry]->offload_to_be_enabled;
1274 hpsa_show_dev_msg(KERN_INFO, h, h->dev[entry], "updated");
1275 h->dev[entry]->offload_enabled = offload_enabled;
1276 }
1277
1278 /* Replace an entry from h->dev[] array. */
1279 static void hpsa_scsi_replace_entry(struct ctlr_info *h, int hostno,
1280 int entry, struct hpsa_scsi_dev_t *new_entry,
1281 struct hpsa_scsi_dev_t *added[], int *nadded,
1282 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1283 {
1284 /* assumes h->devlock is held */
1285 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
1286 removed[*nremoved] = h->dev[entry];
1287 (*nremoved)++;
1288
1289 /*
1290 * New physical devices won't have target/lun assigned yet
1291 * so we need to preserve the values in the slot we are replacing.
1292 */
1293 if (new_entry->target == -1) {
1294 new_entry->target = h->dev[entry]->target;
1295 new_entry->lun = h->dev[entry]->lun;
1296 }
1297
1298 h->dev[entry] = new_entry;
1299 added[*nadded] = new_entry;
1300 (*nadded)++;
1301 hpsa_show_dev_msg(KERN_INFO, h, new_entry, "replaced");
1302 new_entry->offload_to_be_enabled = new_entry->offload_enabled;
1303 new_entry->offload_enabled = 0;
1304 }
1305
1306 /* Remove an entry from h->dev[] array. */
1307 static void hpsa_scsi_remove_entry(struct ctlr_info *h, int hostno, int entry,
1308 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1309 {
1310 /* assumes h->devlock is held */
1311 int i;
1312 struct hpsa_scsi_dev_t *sd;
1313
1314 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
1315
1316 sd = h->dev[entry];
1317 removed[*nremoved] = h->dev[entry];
1318 (*nremoved)++;
1319
1320 for (i = entry; i < h->ndevices-1; i++)
1321 h->dev[i] = h->dev[i+1];
1322 h->ndevices--;
1323 hpsa_show_dev_msg(KERN_INFO, h, sd, "removed");
1324 }
1325
1326 #define SCSI3ADDR_EQ(a, b) ( \
1327 (a)[7] == (b)[7] && \
1328 (a)[6] == (b)[6] && \
1329 (a)[5] == (b)[5] && \
1330 (a)[4] == (b)[4] && \
1331 (a)[3] == (b)[3] && \
1332 (a)[2] == (b)[2] && \
1333 (a)[1] == (b)[1] && \
1334 (a)[0] == (b)[0])
1335
1336 static void fixup_botched_add(struct ctlr_info *h,
1337 struct hpsa_scsi_dev_t *added)
1338 {
1339 /* called when scsi_add_device fails in order to re-adjust
1340 * h->dev[] to match the mid layer's view.
1341 */
1342 unsigned long flags;
1343 int i, j;
1344
1345 spin_lock_irqsave(&h->lock, flags);
1346 for (i = 0; i < h->ndevices; i++) {
1347 if (h->dev[i] == added) {
1348 for (j = i; j < h->ndevices-1; j++)
1349 h->dev[j] = h->dev[j+1];
1350 h->ndevices--;
1351 break;
1352 }
1353 }
1354 spin_unlock_irqrestore(&h->lock, flags);
1355 kfree(added);
1356 }
1357
1358 static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
1359 struct hpsa_scsi_dev_t *dev2)
1360 {
1361 /* we compare everything except lun and target as these
1362 * are not yet assigned. Compare parts likely
1363 * to differ first
1364 */
1365 if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
1366 sizeof(dev1->scsi3addr)) != 0)
1367 return 0;
1368 if (memcmp(dev1->device_id, dev2->device_id,
1369 sizeof(dev1->device_id)) != 0)
1370 return 0;
1371 if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
1372 return 0;
1373 if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
1374 return 0;
1375 if (dev1->devtype != dev2->devtype)
1376 return 0;
1377 if (dev1->bus != dev2->bus)
1378 return 0;
1379 return 1;
1380 }
1381
1382 static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
1383 struct hpsa_scsi_dev_t *dev2)
1384 {
1385 /* Device attributes that can change, but don't mean
1386 * that the device is a different device, nor that the OS
1387 * needs to be told anything about the change.
1388 */
1389 if (dev1->raid_level != dev2->raid_level)
1390 return 1;
1391 if (dev1->offload_config != dev2->offload_config)
1392 return 1;
1393 if (dev1->offload_enabled != dev2->offload_enabled)
1394 return 1;
1395 if (!is_logical_dev_addr_mode(dev1->scsi3addr))
1396 if (dev1->queue_depth != dev2->queue_depth)
1397 return 1;
1398 return 0;
1399 }
1400
1401 /* Find needle in haystack. If exact match found, return DEVICE_SAME,
1402 * and return needle location in *index. If scsi3addr matches, but not
1403 * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
1404 * location in *index.
1405 * In the case of a minor device attribute change, such as RAID level, just
1406 * return DEVICE_UPDATED, along with the updated device's location in index.
1407 * If needle not found, return DEVICE_NOT_FOUND.
1408 */
1409 static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
1410 struct hpsa_scsi_dev_t *haystack[], int haystack_size,
1411 int *index)
1412 {
1413 int i;
1414 #define DEVICE_NOT_FOUND 0
1415 #define DEVICE_CHANGED 1
1416 #define DEVICE_SAME 2
1417 #define DEVICE_UPDATED 3
1418 for (i = 0; i < haystack_size; i++) {
1419 if (haystack[i] == NULL) /* previously removed. */
1420 continue;
1421 if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
1422 *index = i;
1423 if (device_is_the_same(needle, haystack[i])) {
1424 if (device_updated(needle, haystack[i]))
1425 return DEVICE_UPDATED;
1426 return DEVICE_SAME;
1427 } else {
1428 /* Keep offline devices offline */
1429 if (needle->volume_offline)
1430 return DEVICE_NOT_FOUND;
1431 return DEVICE_CHANGED;
1432 }
1433 }
1434 }
1435 *index = -1;
1436 return DEVICE_NOT_FOUND;
1437 }
1438
1439 static void hpsa_monitor_offline_device(struct ctlr_info *h,
1440 unsigned char scsi3addr[])
1441 {
1442 struct offline_device_entry *device;
1443 unsigned long flags;
1444
1445 /* Check to see if device is already on the list */
1446 spin_lock_irqsave(&h->offline_device_lock, flags);
1447 list_for_each_entry(device, &h->offline_device_list, offline_list) {
1448 if (memcmp(device->scsi3addr, scsi3addr,
1449 sizeof(device->scsi3addr)) == 0) {
1450 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1451 return;
1452 }
1453 }
1454 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1455
1456 /* Device is not on the list, add it. */
1457 device = kmalloc(sizeof(*device), GFP_KERNEL);
1458 if (!device) {
1459 dev_warn(&h->pdev->dev, "out of memory in %s\n", __func__);
1460 return;
1461 }
1462 memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr));
1463 spin_lock_irqsave(&h->offline_device_lock, flags);
1464 list_add_tail(&device->offline_list, &h->offline_device_list);
1465 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1466 }
1467
1468 /* Print a message explaining various offline volume states */
1469 static void hpsa_show_volume_status(struct ctlr_info *h,
1470 struct hpsa_scsi_dev_t *sd)
1471 {
1472 if (sd->volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED)
1473 dev_info(&h->pdev->dev,
1474 "C%d:B%d:T%d:L%d Volume status is not available through vital product data pages.\n",
1475 h->scsi_host->host_no,
1476 sd->bus, sd->target, sd->lun);
1477 switch (sd->volume_offline) {
1478 case HPSA_LV_OK:
1479 break;
1480 case HPSA_LV_UNDERGOING_ERASE:
1481 dev_info(&h->pdev->dev,
1482 "C%d:B%d:T%d:L%d Volume is undergoing background erase process.\n",
1483 h->scsi_host->host_no,
1484 sd->bus, sd->target, sd->lun);
1485 break;
1486 case HPSA_LV_NOT_AVAILABLE:
1487 dev_info(&h->pdev->dev,
1488 "C%d:B%d:T%d:L%d Volume is waiting for transforming volume.\n",
1489 h->scsi_host->host_no,
1490 sd->bus, sd->target, sd->lun);
1491 break;
1492 case HPSA_LV_UNDERGOING_RPI:
1493 dev_info(&h->pdev->dev,
1494 "C%d:B%d:T%d:L%d Volume is undergoing rapid parity init.\n",
1495 h->scsi_host->host_no,
1496 sd->bus, sd->target, sd->lun);
1497 break;
1498 case HPSA_LV_PENDING_RPI:
1499 dev_info(&h->pdev->dev,
1500 "C%d:B%d:T%d:L%d Volume is queued for rapid parity initialization process.\n",
1501 h->scsi_host->host_no,
1502 sd->bus, sd->target, sd->lun);
1503 break;
1504 case HPSA_LV_ENCRYPTED_NO_KEY:
1505 dev_info(&h->pdev->dev,
1506 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because key is not present.\n",
1507 h->scsi_host->host_no,
1508 sd->bus, sd->target, sd->lun);
1509 break;
1510 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
1511 dev_info(&h->pdev->dev,
1512 "C%d:B%d:T%d:L%d Volume is not encrypted and cannot be accessed because controller is in encryption-only mode.\n",
1513 h->scsi_host->host_no,
1514 sd->bus, sd->target, sd->lun);
1515 break;
1516 case HPSA_LV_UNDERGOING_ENCRYPTION:
1517 dev_info(&h->pdev->dev,
1518 "C%d:B%d:T%d:L%d Volume is undergoing encryption process.\n",
1519 h->scsi_host->host_no,
1520 sd->bus, sd->target, sd->lun);
1521 break;
1522 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
1523 dev_info(&h->pdev->dev,
1524 "C%d:B%d:T%d:L%d Volume is undergoing encryption re-keying process.\n",
1525 h->scsi_host->host_no,
1526 sd->bus, sd->target, sd->lun);
1527 break;
1528 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
1529 dev_info(&h->pdev->dev,
1530 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because controller does not have encryption enabled.\n",
1531 h->scsi_host->host_no,
1532 sd->bus, sd->target, sd->lun);
1533 break;
1534 case HPSA_LV_PENDING_ENCRYPTION:
1535 dev_info(&h->pdev->dev,
1536 "C%d:B%d:T%d:L%d Volume is pending migration to encrypted state, but process has not started.\n",
1537 h->scsi_host->host_no,
1538 sd->bus, sd->target, sd->lun);
1539 break;
1540 case HPSA_LV_PENDING_ENCRYPTION_REKEYING:
1541 dev_info(&h->pdev->dev,
1542 "C%d:B%d:T%d:L%d Volume is encrypted and is pending encryption rekeying.\n",
1543 h->scsi_host->host_no,
1544 sd->bus, sd->target, sd->lun);
1545 break;
1546 }
1547 }
1548
1549 /*
1550 * Figure the list of physical drive pointers for a logical drive with
1551 * raid offload configured.
1552 */
1553 static void hpsa_figure_phys_disk_ptrs(struct ctlr_info *h,
1554 struct hpsa_scsi_dev_t *dev[], int ndevices,
1555 struct hpsa_scsi_dev_t *logical_drive)
1556 {
1557 struct raid_map_data *map = &logical_drive->raid_map;
1558 struct raid_map_disk_data *dd = &map->data[0];
1559 int i, j;
1560 int total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
1561 le16_to_cpu(map->metadata_disks_per_row);
1562 int nraid_map_entries = le16_to_cpu(map->row_cnt) *
1563 le16_to_cpu(map->layout_map_count) *
1564 total_disks_per_row;
1565 int nphys_disk = le16_to_cpu(map->layout_map_count) *
1566 total_disks_per_row;
1567 int qdepth;
1568
1569 if (nraid_map_entries > RAID_MAP_MAX_ENTRIES)
1570 nraid_map_entries = RAID_MAP_MAX_ENTRIES;
1571
1572 logical_drive->nphysical_disks = nraid_map_entries;
1573
1574 qdepth = 0;
1575 for (i = 0; i < nraid_map_entries; i++) {
1576 logical_drive->phys_disk[i] = NULL;
1577 if (!logical_drive->offload_config)
1578 continue;
1579 for (j = 0; j < ndevices; j++) {
1580 if (dev[j]->devtype != TYPE_DISK)
1581 continue;
1582 if (is_logical_dev_addr_mode(dev[j]->scsi3addr))
1583 continue;
1584 if (dev[j]->ioaccel_handle != dd[i].ioaccel_handle)
1585 continue;
1586
1587 logical_drive->phys_disk[i] = dev[j];
1588 if (i < nphys_disk)
1589 qdepth = min(h->nr_cmds, qdepth +
1590 logical_drive->phys_disk[i]->queue_depth);
1591 break;
1592 }
1593
1594 /*
1595 * This can happen if a physical drive is removed and
1596 * the logical drive is degraded. In that case, the RAID
1597 * map data will refer to a physical disk which isn't actually
1598 * present. And in that case offload_enabled should already
1599 * be 0, but we'll turn it off here just in case
1600 */
1601 if (!logical_drive->phys_disk[i]) {
1602 logical_drive->offload_enabled = 0;
1603 logical_drive->offload_to_be_enabled = 0;
1604 logical_drive->queue_depth = 8;
1605 }
1606 }
1607 if (nraid_map_entries)
1608 /*
1609 * This is correct for reads, too high for full stripe writes,
1610 * way too high for partial stripe writes
1611 */
1612 logical_drive->queue_depth = qdepth;
1613 else
1614 logical_drive->queue_depth = h->nr_cmds;
1615 }
1616
1617 static void hpsa_update_log_drive_phys_drive_ptrs(struct ctlr_info *h,
1618 struct hpsa_scsi_dev_t *dev[], int ndevices)
1619 {
1620 int i;
1621
1622 for (i = 0; i < ndevices; i++) {
1623 if (dev[i]->devtype != TYPE_DISK)
1624 continue;
1625 if (!is_logical_dev_addr_mode(dev[i]->scsi3addr))
1626 continue;
1627
1628 /*
1629 * If offload is currently enabled, the RAID map and
1630 * phys_disk[] assignment *better* not be changing
1631 * and since it isn't changing, we do not need to
1632 * update it.
1633 */
1634 if (dev[i]->offload_enabled)
1635 continue;
1636
1637 hpsa_figure_phys_disk_ptrs(h, dev, ndevices, dev[i]);
1638 }
1639 }
1640
1641 static void adjust_hpsa_scsi_table(struct ctlr_info *h, int hostno,
1642 struct hpsa_scsi_dev_t *sd[], int nsds)
1643 {
1644 /* sd contains scsi3 addresses and devtypes, and inquiry
1645 * data. This function takes what's in sd to be the current
1646 * reality and updates h->dev[] to reflect that reality.
1647 */
1648 int i, entry, device_change, changes = 0;
1649 struct hpsa_scsi_dev_t *csd;
1650 unsigned long flags;
1651 struct hpsa_scsi_dev_t **added, **removed;
1652 int nadded, nremoved;
1653 struct Scsi_Host *sh = NULL;
1654
1655 added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
1656 removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
1657
1658 if (!added || !removed) {
1659 dev_warn(&h->pdev->dev, "out of memory in "
1660 "adjust_hpsa_scsi_table\n");
1661 goto free_and_out;
1662 }
1663
1664 spin_lock_irqsave(&h->devlock, flags);
1665
1666 /* find any devices in h->dev[] that are not in
1667 * sd[] and remove them from h->dev[], and for any
1668 * devices which have changed, remove the old device
1669 * info and add the new device info.
1670 * If minor device attributes change, just update
1671 * the existing device structure.
1672 */
1673 i = 0;
1674 nremoved = 0;
1675 nadded = 0;
1676 while (i < h->ndevices) {
1677 csd = h->dev[i];
1678 device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
1679 if (device_change == DEVICE_NOT_FOUND) {
1680 changes++;
1681 hpsa_scsi_remove_entry(h, hostno, i,
1682 removed, &nremoved);
1683 continue; /* remove ^^^, hence i not incremented */
1684 } else if (device_change == DEVICE_CHANGED) {
1685 changes++;
1686 hpsa_scsi_replace_entry(h, hostno, i, sd[entry],
1687 added, &nadded, removed, &nremoved);
1688 /* Set it to NULL to prevent it from being freed
1689 * at the bottom of hpsa_update_scsi_devices()
1690 */
1691 sd[entry] = NULL;
1692 } else if (device_change == DEVICE_UPDATED) {
1693 hpsa_scsi_update_entry(h, hostno, i, sd[entry]);
1694 }
1695 i++;
1696 }
1697
1698 /* Now, make sure every device listed in sd[] is also
1699 * listed in h->dev[], adding them if they aren't found
1700 */
1701
1702 for (i = 0; i < nsds; i++) {
1703 if (!sd[i]) /* if already added above. */
1704 continue;
1705
1706 /* Don't add devices which are NOT READY, FORMAT IN PROGRESS
1707 * as the SCSI mid-layer does not handle such devices well.
1708 * It relentlessly loops sending TUR at 3Hz, then READ(10)
1709 * at 160Hz, and prevents the system from coming up.
1710 */
1711 if (sd[i]->volume_offline) {
1712 hpsa_show_volume_status(h, sd[i]);
1713 hpsa_show_dev_msg(KERN_INFO, h, sd[i], "offline");
1714 continue;
1715 }
1716
1717 device_change = hpsa_scsi_find_entry(sd[i], h->dev,
1718 h->ndevices, &entry);
1719 if (device_change == DEVICE_NOT_FOUND) {
1720 changes++;
1721 if (hpsa_scsi_add_entry(h, hostno, sd[i],
1722 added, &nadded) != 0)
1723 break;
1724 sd[i] = NULL; /* prevent from being freed later. */
1725 } else if (device_change == DEVICE_CHANGED) {
1726 /* should never happen... */
1727 changes++;
1728 dev_warn(&h->pdev->dev,
1729 "device unexpectedly changed.\n");
1730 /* but if it does happen, we just ignore that device */
1731 }
1732 }
1733 hpsa_update_log_drive_phys_drive_ptrs(h, h->dev, h->ndevices);
1734
1735 /* Now that h->dev[]->phys_disk[] is coherent, we can enable
1736 * any logical drives that need it enabled.
1737 */
1738 for (i = 0; i < h->ndevices; i++)
1739 h->dev[i]->offload_enabled = h->dev[i]->offload_to_be_enabled;
1740
1741 spin_unlock_irqrestore(&h->devlock, flags);
1742
1743 /* Monitor devices which are in one of several NOT READY states to be
1744 * brought online later. This must be done without holding h->devlock,
1745 * so don't touch h->dev[]
1746 */
1747 for (i = 0; i < nsds; i++) {
1748 if (!sd[i]) /* if already added above. */
1749 continue;
1750 if (sd[i]->volume_offline)
1751 hpsa_monitor_offline_device(h, sd[i]->scsi3addr);
1752 }
1753
1754 /* Don't notify scsi mid layer of any changes the first time through
1755 * (or if there are no changes) scsi_scan_host will do it later the
1756 * first time through.
1757 */
1758 if (hostno == -1 || !changes)
1759 goto free_and_out;
1760
1761 sh = h->scsi_host;
1762 /* Notify scsi mid layer of any removed devices */
1763 for (i = 0; i < nremoved; i++) {
1764 if (removed[i]->expose_state & HPSA_SCSI_ADD) {
1765 struct scsi_device *sdev =
1766 scsi_device_lookup(sh, removed[i]->bus,
1767 removed[i]->target, removed[i]->lun);
1768 if (sdev != NULL) {
1769 scsi_remove_device(sdev);
1770 scsi_device_put(sdev);
1771 } else {
1772 /*
1773 * We don't expect to get here.
1774 * future cmds to this device will get selection
1775 * timeout as if the device was gone.
1776 */
1777 hpsa_show_dev_msg(KERN_WARNING, h, removed[i],
1778 "didn't find device for removal.");
1779 }
1780 }
1781 kfree(removed[i]);
1782 removed[i] = NULL;
1783 }
1784
1785 /* Notify scsi mid layer of any added devices */
1786 for (i = 0; i < nadded; i++) {
1787 if (!(added[i]->expose_state & HPSA_SCSI_ADD))
1788 continue;
1789 if (scsi_add_device(sh, added[i]->bus,
1790 added[i]->target, added[i]->lun) == 0)
1791 continue;
1792 hpsa_show_dev_msg(KERN_WARNING, h, added[i],
1793 "addition failed, device not added.");
1794 /* now we have to remove it from h->dev,
1795 * since it didn't get added to scsi mid layer
1796 */
1797 fixup_botched_add(h, added[i]);
1798 added[i] = NULL;
1799 }
1800
1801 free_and_out:
1802 kfree(added);
1803 kfree(removed);
1804 }
1805
1806 /*
1807 * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
1808 * Assume's h->devlock is held.
1809 */
1810 static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
1811 int bus, int target, int lun)
1812 {
1813 int i;
1814 struct hpsa_scsi_dev_t *sd;
1815
1816 for (i = 0; i < h->ndevices; i++) {
1817 sd = h->dev[i];
1818 if (sd->bus == bus && sd->target == target && sd->lun == lun)
1819 return sd;
1820 }
1821 return NULL;
1822 }
1823
1824 static int hpsa_slave_alloc(struct scsi_device *sdev)
1825 {
1826 struct hpsa_scsi_dev_t *sd;
1827 unsigned long flags;
1828 struct ctlr_info *h;
1829
1830 h = sdev_to_hba(sdev);
1831 spin_lock_irqsave(&h->devlock, flags);
1832 sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
1833 sdev_id(sdev), sdev->lun);
1834 if (likely(sd)) {
1835 atomic_set(&sd->ioaccel_cmds_out, 0);
1836 sdev->hostdata = (sd->expose_state & HPSA_SCSI_ADD) ? sd : NULL;
1837 } else
1838 sdev->hostdata = NULL;
1839 spin_unlock_irqrestore(&h->devlock, flags);
1840 return 0;
1841 }
1842
1843 /* configure scsi device based on internal per-device structure */
1844 static int hpsa_slave_configure(struct scsi_device *sdev)
1845 {
1846 struct hpsa_scsi_dev_t *sd;
1847 int queue_depth;
1848
1849 sd = sdev->hostdata;
1850 sdev->no_uld_attach = !sd || !(sd->expose_state & HPSA_ULD_ATTACH);
1851
1852 if (sd)
1853 queue_depth = sd->queue_depth != 0 ?
1854 sd->queue_depth : sdev->host->can_queue;
1855 else
1856 queue_depth = sdev->host->can_queue;
1857
1858 scsi_change_queue_depth(sdev, queue_depth);
1859
1860 return 0;
1861 }
1862
1863 static void hpsa_slave_destroy(struct scsi_device *sdev)
1864 {
1865 /* nothing to do. */
1866 }
1867
1868 static void hpsa_free_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
1869 {
1870 int i;
1871
1872 if (!h->ioaccel2_cmd_sg_list)
1873 return;
1874 for (i = 0; i < h->nr_cmds; i++) {
1875 kfree(h->ioaccel2_cmd_sg_list[i]);
1876 h->ioaccel2_cmd_sg_list[i] = NULL;
1877 }
1878 kfree(h->ioaccel2_cmd_sg_list);
1879 h->ioaccel2_cmd_sg_list = NULL;
1880 }
1881
1882 static int hpsa_allocate_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
1883 {
1884 int i;
1885
1886 if (h->chainsize <= 0)
1887 return 0;
1888
1889 h->ioaccel2_cmd_sg_list =
1890 kzalloc(sizeof(*h->ioaccel2_cmd_sg_list) * h->nr_cmds,
1891 GFP_KERNEL);
1892 if (!h->ioaccel2_cmd_sg_list)
1893 return -ENOMEM;
1894 for (i = 0; i < h->nr_cmds; i++) {
1895 h->ioaccel2_cmd_sg_list[i] =
1896 kmalloc(sizeof(*h->ioaccel2_cmd_sg_list[i]) *
1897 h->maxsgentries, GFP_KERNEL);
1898 if (!h->ioaccel2_cmd_sg_list[i])
1899 goto clean;
1900 }
1901 return 0;
1902
1903 clean:
1904 hpsa_free_ioaccel2_sg_chain_blocks(h);
1905 return -ENOMEM;
1906 }
1907
1908 static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
1909 {
1910 int i;
1911
1912 if (!h->cmd_sg_list)
1913 return;
1914 for (i = 0; i < h->nr_cmds; i++) {
1915 kfree(h->cmd_sg_list[i]);
1916 h->cmd_sg_list[i] = NULL;
1917 }
1918 kfree(h->cmd_sg_list);
1919 h->cmd_sg_list = NULL;
1920 }
1921
1922 static int hpsa_alloc_sg_chain_blocks(struct ctlr_info *h)
1923 {
1924 int i;
1925
1926 if (h->chainsize <= 0)
1927 return 0;
1928
1929 h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
1930 GFP_KERNEL);
1931 if (!h->cmd_sg_list) {
1932 dev_err(&h->pdev->dev, "Failed to allocate SG list\n");
1933 return -ENOMEM;
1934 }
1935 for (i = 0; i < h->nr_cmds; i++) {
1936 h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
1937 h->chainsize, GFP_KERNEL);
1938 if (!h->cmd_sg_list[i]) {
1939 dev_err(&h->pdev->dev, "Failed to allocate cmd SG\n");
1940 goto clean;
1941 }
1942 }
1943 return 0;
1944
1945 clean:
1946 hpsa_free_sg_chain_blocks(h);
1947 return -ENOMEM;
1948 }
1949
1950 static int hpsa_map_ioaccel2_sg_chain_block(struct ctlr_info *h,
1951 struct io_accel2_cmd *cp, struct CommandList *c)
1952 {
1953 struct ioaccel2_sg_element *chain_block;
1954 u64 temp64;
1955 u32 chain_size;
1956
1957 chain_block = h->ioaccel2_cmd_sg_list[c->cmdindex];
1958 chain_size = le32_to_cpu(cp->data_len);
1959 temp64 = pci_map_single(h->pdev, chain_block, chain_size,
1960 PCI_DMA_TODEVICE);
1961 if (dma_mapping_error(&h->pdev->dev, temp64)) {
1962 /* prevent subsequent unmapping */
1963 cp->sg->address = 0;
1964 return -1;
1965 }
1966 cp->sg->address = cpu_to_le64(temp64);
1967 return 0;
1968 }
1969
1970 static void hpsa_unmap_ioaccel2_sg_chain_block(struct ctlr_info *h,
1971 struct io_accel2_cmd *cp)
1972 {
1973 struct ioaccel2_sg_element *chain_sg;
1974 u64 temp64;
1975 u32 chain_size;
1976
1977 chain_sg = cp->sg;
1978 temp64 = le64_to_cpu(chain_sg->address);
1979 chain_size = le32_to_cpu(cp->data_len);
1980 pci_unmap_single(h->pdev, temp64, chain_size, PCI_DMA_TODEVICE);
1981 }
1982
1983 static int hpsa_map_sg_chain_block(struct ctlr_info *h,
1984 struct CommandList *c)
1985 {
1986 struct SGDescriptor *chain_sg, *chain_block;
1987 u64 temp64;
1988 u32 chain_len;
1989
1990 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
1991 chain_block = h->cmd_sg_list[c->cmdindex];
1992 chain_sg->Ext = cpu_to_le32(HPSA_SG_CHAIN);
1993 chain_len = sizeof(*chain_sg) *
1994 (le16_to_cpu(c->Header.SGTotal) - h->max_cmd_sg_entries);
1995 chain_sg->Len = cpu_to_le32(chain_len);
1996 temp64 = pci_map_single(h->pdev, chain_block, chain_len,
1997 PCI_DMA_TODEVICE);
1998 if (dma_mapping_error(&h->pdev->dev, temp64)) {
1999 /* prevent subsequent unmapping */
2000 chain_sg->Addr = cpu_to_le64(0);
2001 return -1;
2002 }
2003 chain_sg->Addr = cpu_to_le64(temp64);
2004 return 0;
2005 }
2006
2007 static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
2008 struct CommandList *c)
2009 {
2010 struct SGDescriptor *chain_sg;
2011
2012 if (le16_to_cpu(c->Header.SGTotal) <= h->max_cmd_sg_entries)
2013 return;
2014
2015 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
2016 pci_unmap_single(h->pdev, le64_to_cpu(chain_sg->Addr),
2017 le32_to_cpu(chain_sg->Len), PCI_DMA_TODEVICE);
2018 }
2019
2020
2021 /* Decode the various types of errors on ioaccel2 path.
2022 * Return 1 for any error that should generate a RAID path retry.
2023 * Return 0 for errors that don't require a RAID path retry.
2024 */
2025 static int handle_ioaccel_mode2_error(struct ctlr_info *h,
2026 struct CommandList *c,
2027 struct scsi_cmnd *cmd,
2028 struct io_accel2_cmd *c2)
2029 {
2030 int data_len;
2031 int retry = 0;
2032 u32 ioaccel2_resid = 0;
2033
2034 switch (c2->error_data.serv_response) {
2035 case IOACCEL2_SERV_RESPONSE_COMPLETE:
2036 switch (c2->error_data.status) {
2037 case IOACCEL2_STATUS_SR_TASK_COMP_GOOD:
2038 break;
2039 case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND:
2040 cmd->result |= SAM_STAT_CHECK_CONDITION;
2041 if (c2->error_data.data_present !=
2042 IOACCEL2_SENSE_DATA_PRESENT) {
2043 memset(cmd->sense_buffer, 0,
2044 SCSI_SENSE_BUFFERSIZE);
2045 break;
2046 }
2047 /* copy the sense data */
2048 data_len = c2->error_data.sense_data_len;
2049 if (data_len > SCSI_SENSE_BUFFERSIZE)
2050 data_len = SCSI_SENSE_BUFFERSIZE;
2051 if (data_len > sizeof(c2->error_data.sense_data_buff))
2052 data_len =
2053 sizeof(c2->error_data.sense_data_buff);
2054 memcpy(cmd->sense_buffer,
2055 c2->error_data.sense_data_buff, data_len);
2056 retry = 1;
2057 break;
2058 case IOACCEL2_STATUS_SR_TASK_COMP_BUSY:
2059 retry = 1;
2060 break;
2061 case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON:
2062 retry = 1;
2063 break;
2064 case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL:
2065 retry = 1;
2066 break;
2067 case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED:
2068 retry = 1;
2069 break;
2070 default:
2071 retry = 1;
2072 break;
2073 }
2074 break;
2075 case IOACCEL2_SERV_RESPONSE_FAILURE:
2076 switch (c2->error_data.status) {
2077 case IOACCEL2_STATUS_SR_IO_ERROR:
2078 case IOACCEL2_STATUS_SR_IO_ABORTED:
2079 case IOACCEL2_STATUS_SR_OVERRUN:
2080 retry = 1;
2081 break;
2082 case IOACCEL2_STATUS_SR_UNDERRUN:
2083 cmd->result = (DID_OK << 16); /* host byte */
2084 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
2085 ioaccel2_resid = get_unaligned_le32(
2086 &c2->error_data.resid_cnt[0]);
2087 scsi_set_resid(cmd, ioaccel2_resid);
2088 break;
2089 case IOACCEL2_STATUS_SR_NO_PATH_TO_DEVICE:
2090 case IOACCEL2_STATUS_SR_INVALID_DEVICE:
2091 case IOACCEL2_STATUS_SR_IOACCEL_DISABLED:
2092 /* We will get an event from ctlr to trigger rescan */
2093 retry = 1;
2094 break;
2095 default:
2096 retry = 1;
2097 }
2098 break;
2099 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
2100 break;
2101 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
2102 break;
2103 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
2104 retry = 1;
2105 break;
2106 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
2107 break;
2108 default:
2109 retry = 1;
2110 break;
2111 }
2112
2113 return retry; /* retry on raid path? */
2114 }
2115
2116 static void hpsa_cmd_resolve_events(struct ctlr_info *h,
2117 struct CommandList *c)
2118 {
2119 bool do_wake = false;
2120
2121 /*
2122 * Prevent the following race in the abort handler:
2123 *
2124 * 1. LLD is requested to abort a SCSI command
2125 * 2. The SCSI command completes
2126 * 3. The struct CommandList associated with step 2 is made available
2127 * 4. New I/O request to LLD to another LUN re-uses struct CommandList
2128 * 5. Abort handler follows scsi_cmnd->host_scribble and
2129 * finds struct CommandList and tries to aborts it
2130 * Now we have aborted the wrong command.
2131 *
2132 * Reset c->scsi_cmd here so that the abort or reset handler will know
2133 * this command has completed. Then, check to see if the handler is
2134 * waiting for this command, and, if so, wake it.
2135 */
2136 c->scsi_cmd = SCSI_CMD_IDLE;
2137 mb(); /* Declare command idle before checking for pending events. */
2138 if (c->abort_pending) {
2139 do_wake = true;
2140 c->abort_pending = false;
2141 }
2142 if (c->reset_pending) {
2143 unsigned long flags;
2144 struct hpsa_scsi_dev_t *dev;
2145
2146 /*
2147 * There appears to be a reset pending; lock the lock and
2148 * reconfirm. If so, then decrement the count of outstanding
2149 * commands and wake the reset command if this is the last one.
2150 */
2151 spin_lock_irqsave(&h->lock, flags);
2152 dev = c->reset_pending; /* Re-fetch under the lock. */
2153 if (dev && atomic_dec_and_test(&dev->reset_cmds_out))
2154 do_wake = true;
2155 c->reset_pending = NULL;
2156 spin_unlock_irqrestore(&h->lock, flags);
2157 }
2158
2159 if (do_wake)
2160 wake_up_all(&h->event_sync_wait_queue);
2161 }
2162
2163 static void hpsa_cmd_resolve_and_free(struct ctlr_info *h,
2164 struct CommandList *c)
2165 {
2166 hpsa_cmd_resolve_events(h, c);
2167 cmd_tagged_free(h, c);
2168 }
2169
2170 static void hpsa_cmd_free_and_done(struct ctlr_info *h,
2171 struct CommandList *c, struct scsi_cmnd *cmd)
2172 {
2173 hpsa_cmd_resolve_and_free(h, c);
2174 cmd->scsi_done(cmd);
2175 }
2176
2177 static void hpsa_retry_cmd(struct ctlr_info *h, struct CommandList *c)
2178 {
2179 INIT_WORK(&c->work, hpsa_command_resubmit_worker);
2180 queue_work_on(raw_smp_processor_id(), h->resubmit_wq, &c->work);
2181 }
2182
2183 static void hpsa_set_scsi_cmd_aborted(struct scsi_cmnd *cmd)
2184 {
2185 cmd->result = DID_ABORT << 16;
2186 }
2187
2188 static void hpsa_cmd_abort_and_free(struct ctlr_info *h, struct CommandList *c,
2189 struct scsi_cmnd *cmd)
2190 {
2191 hpsa_set_scsi_cmd_aborted(cmd);
2192 dev_warn(&h->pdev->dev, "CDB %16phN was aborted with status 0x%x\n",
2193 c->Request.CDB, c->err_info->ScsiStatus);
2194 hpsa_cmd_resolve_and_free(h, c);
2195 }
2196
2197 static void process_ioaccel2_completion(struct ctlr_info *h,
2198 struct CommandList *c, struct scsi_cmnd *cmd,
2199 struct hpsa_scsi_dev_t *dev)
2200 {
2201 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
2202
2203 /* check for good status */
2204 if (likely(c2->error_data.serv_response == 0 &&
2205 c2->error_data.status == 0))
2206 return hpsa_cmd_free_and_done(h, c, cmd);
2207
2208 /*
2209 * Any RAID offload error results in retry which will use
2210 * the normal I/O path so the controller can handle whatever's
2211 * wrong.
2212 */
2213 if (is_logical_dev_addr_mode(dev->scsi3addr) &&
2214 c2->error_data.serv_response ==
2215 IOACCEL2_SERV_RESPONSE_FAILURE) {
2216 if (c2->error_data.status ==
2217 IOACCEL2_STATUS_SR_IOACCEL_DISABLED)
2218 dev->offload_enabled = 0;
2219
2220 return hpsa_retry_cmd(h, c);
2221 }
2222
2223 if (handle_ioaccel_mode2_error(h, c, cmd, c2))
2224 return hpsa_retry_cmd(h, c);
2225
2226 return hpsa_cmd_free_and_done(h, c, cmd);
2227 }
2228
2229 /* Returns 0 on success, < 0 otherwise. */
2230 static int hpsa_evaluate_tmf_status(struct ctlr_info *h,
2231 struct CommandList *cp)
2232 {
2233 u8 tmf_status = cp->err_info->ScsiStatus;
2234
2235 switch (tmf_status) {
2236 case CISS_TMF_COMPLETE:
2237 /*
2238 * CISS_TMF_COMPLETE never happens, instead,
2239 * ei->CommandStatus == 0 for this case.
2240 */
2241 case CISS_TMF_SUCCESS:
2242 return 0;
2243 case CISS_TMF_INVALID_FRAME:
2244 case CISS_TMF_NOT_SUPPORTED:
2245 case CISS_TMF_FAILED:
2246 case CISS_TMF_WRONG_LUN:
2247 case CISS_TMF_OVERLAPPED_TAG:
2248 break;
2249 default:
2250 dev_warn(&h->pdev->dev, "Unknown TMF status: 0x%02x\n",
2251 tmf_status);
2252 break;
2253 }
2254 return -tmf_status;
2255 }
2256
2257 static void complete_scsi_command(struct CommandList *cp)
2258 {
2259 struct scsi_cmnd *cmd;
2260 struct ctlr_info *h;
2261 struct ErrorInfo *ei;
2262 struct hpsa_scsi_dev_t *dev;
2263 struct io_accel2_cmd *c2;
2264
2265 u8 sense_key;
2266 u8 asc; /* additional sense code */
2267 u8 ascq; /* additional sense code qualifier */
2268 unsigned long sense_data_size;
2269
2270 ei = cp->err_info;
2271 cmd = cp->scsi_cmd;
2272 h = cp->h;
2273 dev = cmd->device->hostdata;
2274 c2 = &h->ioaccel2_cmd_pool[cp->cmdindex];
2275
2276 scsi_dma_unmap(cmd); /* undo the DMA mappings */
2277 if ((cp->cmd_type == CMD_SCSI) &&
2278 (le16_to_cpu(cp->Header.SGTotal) > h->max_cmd_sg_entries))
2279 hpsa_unmap_sg_chain_block(h, cp);
2280
2281 if ((cp->cmd_type == CMD_IOACCEL2) &&
2282 (c2->sg[0].chain_indicator == IOACCEL2_CHAIN))
2283 hpsa_unmap_ioaccel2_sg_chain_block(h, c2);
2284
2285 cmd->result = (DID_OK << 16); /* host byte */
2286 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
2287
2288 if (cp->cmd_type == CMD_IOACCEL2 || cp->cmd_type == CMD_IOACCEL1)
2289 atomic_dec(&cp->phys_disk->ioaccel_cmds_out);
2290
2291 /*
2292 * We check for lockup status here as it may be set for
2293 * CMD_SCSI, CMD_IOACCEL1 and CMD_IOACCEL2 commands by
2294 * fail_all_oustanding_cmds()
2295 */
2296 if (unlikely(ei->CommandStatus == CMD_CTLR_LOCKUP)) {
2297 /* DID_NO_CONNECT will prevent a retry */
2298 cmd->result = DID_NO_CONNECT << 16;
2299 return hpsa_cmd_free_and_done(h, cp, cmd);
2300 }
2301
2302 if ((unlikely(hpsa_is_pending_event(cp)))) {
2303 if (cp->reset_pending)
2304 return hpsa_cmd_resolve_and_free(h, cp);
2305 if (cp->abort_pending)
2306 return hpsa_cmd_abort_and_free(h, cp, cmd);
2307 }
2308
2309 if (cp->cmd_type == CMD_IOACCEL2)
2310 return process_ioaccel2_completion(h, cp, cmd, dev);
2311
2312 scsi_set_resid(cmd, ei->ResidualCnt);
2313 if (ei->CommandStatus == 0)
2314 return hpsa_cmd_free_and_done(h, cp, cmd);
2315
2316 /* For I/O accelerator commands, copy over some fields to the normal
2317 * CISS header used below for error handling.
2318 */
2319 if (cp->cmd_type == CMD_IOACCEL1) {
2320 struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
2321 cp->Header.SGList = scsi_sg_count(cmd);
2322 cp->Header.SGTotal = cpu_to_le16(cp->Header.SGList);
2323 cp->Request.CDBLen = le16_to_cpu(c->io_flags) &
2324 IOACCEL1_IOFLAGS_CDBLEN_MASK;
2325 cp->Header.tag = c->tag;
2326 memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
2327 memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
2328
2329 /* Any RAID offload error results in retry which will use
2330 * the normal I/O path so the controller can handle whatever's
2331 * wrong.
2332 */
2333 if (is_logical_dev_addr_mode(dev->scsi3addr)) {
2334 if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
2335 dev->offload_enabled = 0;
2336 return hpsa_retry_cmd(h, cp);
2337 }
2338 }
2339
2340 /* an error has occurred */
2341 switch (ei->CommandStatus) {
2342
2343 case CMD_TARGET_STATUS:
2344 cmd->result |= ei->ScsiStatus;
2345 /* copy the sense data */
2346 if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
2347 sense_data_size = SCSI_SENSE_BUFFERSIZE;
2348 else
2349 sense_data_size = sizeof(ei->SenseInfo);
2350 if (ei->SenseLen < sense_data_size)
2351 sense_data_size = ei->SenseLen;
2352 memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
2353 if (ei->ScsiStatus)
2354 decode_sense_data(ei->SenseInfo, sense_data_size,
2355 &sense_key, &asc, &ascq);
2356 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
2357 if (sense_key == ABORTED_COMMAND) {
2358 cmd->result |= DID_SOFT_ERROR << 16;
2359 break;
2360 }
2361 break;
2362 }
2363 /* Problem was not a check condition
2364 * Pass it up to the upper layers...
2365 */
2366 if (ei->ScsiStatus) {
2367 dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
2368 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
2369 "Returning result: 0x%x\n",
2370 cp, ei->ScsiStatus,
2371 sense_key, asc, ascq,
2372 cmd->result);
2373 } else { /* scsi status is zero??? How??? */
2374 dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
2375 "Returning no connection.\n", cp),
2376
2377 /* Ordinarily, this case should never happen,
2378 * but there is a bug in some released firmware
2379 * revisions that allows it to happen if, for
2380 * example, a 4100 backplane loses power and
2381 * the tape drive is in it. We assume that
2382 * it's a fatal error of some kind because we
2383 * can't show that it wasn't. We will make it
2384 * look like selection timeout since that is
2385 * the most common reason for this to occur,
2386 * and it's severe enough.
2387 */
2388
2389 cmd->result = DID_NO_CONNECT << 16;
2390 }
2391 break;
2392
2393 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
2394 break;
2395 case CMD_DATA_OVERRUN:
2396 dev_warn(&h->pdev->dev,
2397 "CDB %16phN data overrun\n", cp->Request.CDB);
2398 break;
2399 case CMD_INVALID: {
2400 /* print_bytes(cp, sizeof(*cp), 1, 0);
2401 print_cmd(cp); */
2402 /* We get CMD_INVALID if you address a non-existent device
2403 * instead of a selection timeout (no response). You will
2404 * see this if you yank out a drive, then try to access it.
2405 * This is kind of a shame because it means that any other
2406 * CMD_INVALID (e.g. driver bug) will get interpreted as a
2407 * missing target. */
2408 cmd->result = DID_NO_CONNECT << 16;
2409 }
2410 break;
2411 case CMD_PROTOCOL_ERR:
2412 cmd->result = DID_ERROR << 16;
2413 dev_warn(&h->pdev->dev, "CDB %16phN : protocol error\n",
2414 cp->Request.CDB);
2415 break;
2416 case CMD_HARDWARE_ERR:
2417 cmd->result = DID_ERROR << 16;
2418 dev_warn(&h->pdev->dev, "CDB %16phN : hardware error\n",
2419 cp->Request.CDB);
2420 break;
2421 case CMD_CONNECTION_LOST:
2422 cmd->result = DID_ERROR << 16;
2423 dev_warn(&h->pdev->dev, "CDB %16phN : connection lost\n",
2424 cp->Request.CDB);
2425 break;
2426 case CMD_ABORTED:
2427 /* Return now to avoid calling scsi_done(). */
2428 return hpsa_cmd_abort_and_free(h, cp, cmd);
2429 case CMD_ABORT_FAILED:
2430 cmd->result = DID_ERROR << 16;
2431 dev_warn(&h->pdev->dev, "CDB %16phN : abort failed\n",
2432 cp->Request.CDB);
2433 break;
2434 case CMD_UNSOLICITED_ABORT:
2435 cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
2436 dev_warn(&h->pdev->dev, "CDB %16phN : unsolicited abort\n",
2437 cp->Request.CDB);
2438 break;
2439 case CMD_TIMEOUT:
2440 cmd->result = DID_TIME_OUT << 16;
2441 dev_warn(&h->pdev->dev, "CDB %16phN timed out\n",
2442 cp->Request.CDB);
2443 break;
2444 case CMD_UNABORTABLE:
2445 cmd->result = DID_ERROR << 16;
2446 dev_warn(&h->pdev->dev, "Command unabortable\n");
2447 break;
2448 case CMD_TMF_STATUS:
2449 if (hpsa_evaluate_tmf_status(h, cp)) /* TMF failed? */
2450 cmd->result = DID_ERROR << 16;
2451 break;
2452 case CMD_IOACCEL_DISABLED:
2453 /* This only handles the direct pass-through case since RAID
2454 * offload is handled above. Just attempt a retry.
2455 */
2456 cmd->result = DID_SOFT_ERROR << 16;
2457 dev_warn(&h->pdev->dev,
2458 "cp %p had HP SSD Smart Path error\n", cp);
2459 break;
2460 default:
2461 cmd->result = DID_ERROR << 16;
2462 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
2463 cp, ei->CommandStatus);
2464 }
2465
2466 return hpsa_cmd_free_and_done(h, cp, cmd);
2467 }
2468
2469 static void hpsa_pci_unmap(struct pci_dev *pdev,
2470 struct CommandList *c, int sg_used, int data_direction)
2471 {
2472 int i;
2473
2474 for (i = 0; i < sg_used; i++)
2475 pci_unmap_single(pdev, (dma_addr_t) le64_to_cpu(c->SG[i].Addr),
2476 le32_to_cpu(c->SG[i].Len),
2477 data_direction);
2478 }
2479
2480 static int hpsa_map_one(struct pci_dev *pdev,
2481 struct CommandList *cp,
2482 unsigned char *buf,
2483 size_t buflen,
2484 int data_direction)
2485 {
2486 u64 addr64;
2487
2488 if (buflen == 0 || data_direction == PCI_DMA_NONE) {
2489 cp->Header.SGList = 0;
2490 cp->Header.SGTotal = cpu_to_le16(0);
2491 return 0;
2492 }
2493
2494 addr64 = pci_map_single(pdev, buf, buflen, data_direction);
2495 if (dma_mapping_error(&pdev->dev, addr64)) {
2496 /* Prevent subsequent unmap of something never mapped */
2497 cp->Header.SGList = 0;
2498 cp->Header.SGTotal = cpu_to_le16(0);
2499 return -1;
2500 }
2501 cp->SG[0].Addr = cpu_to_le64(addr64);
2502 cp->SG[0].Len = cpu_to_le32(buflen);
2503 cp->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* we are not chaining */
2504 cp->Header.SGList = 1; /* no. SGs contig in this cmd */
2505 cp->Header.SGTotal = cpu_to_le16(1); /* total sgs in cmd list */
2506 return 0;
2507 }
2508
2509 #define NO_TIMEOUT ((unsigned long) -1)
2510 #define DEFAULT_TIMEOUT 30000 /* milliseconds */
2511 static int hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
2512 struct CommandList *c, int reply_queue, unsigned long timeout_msecs)
2513 {
2514 DECLARE_COMPLETION_ONSTACK(wait);
2515
2516 c->waiting = &wait;
2517 __enqueue_cmd_and_start_io(h, c, reply_queue);
2518 if (timeout_msecs == NO_TIMEOUT) {
2519 /* TODO: get rid of this no-timeout thing */
2520 wait_for_completion_io(&wait);
2521 return IO_OK;
2522 }
2523 if (!wait_for_completion_io_timeout(&wait,
2524 msecs_to_jiffies(timeout_msecs))) {
2525 dev_warn(&h->pdev->dev, "Command timed out.\n");
2526 return -ETIMEDOUT;
2527 }
2528 return IO_OK;
2529 }
2530
2531 static int hpsa_scsi_do_simple_cmd(struct ctlr_info *h, struct CommandList *c,
2532 int reply_queue, unsigned long timeout_msecs)
2533 {
2534 if (unlikely(lockup_detected(h))) {
2535 c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
2536 return IO_OK;
2537 }
2538 return hpsa_scsi_do_simple_cmd_core(h, c, reply_queue, timeout_msecs);
2539 }
2540
2541 static u32 lockup_detected(struct ctlr_info *h)
2542 {
2543 int cpu;
2544 u32 rc, *lockup_detected;
2545
2546 cpu = get_cpu();
2547 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
2548 rc = *lockup_detected;
2549 put_cpu();
2550 return rc;
2551 }
2552
2553 #define MAX_DRIVER_CMD_RETRIES 25
2554 static int hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
2555 struct CommandList *c, int data_direction, unsigned long timeout_msecs)
2556 {
2557 int backoff_time = 10, retry_count = 0;
2558 int rc;
2559
2560 do {
2561 memset(c->err_info, 0, sizeof(*c->err_info));
2562 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
2563 timeout_msecs);
2564 if (rc)
2565 break;
2566 retry_count++;
2567 if (retry_count > 3) {
2568 msleep(backoff_time);
2569 if (backoff_time < 1000)
2570 backoff_time *= 2;
2571 }
2572 } while ((check_for_unit_attention(h, c) ||
2573 check_for_busy(h, c)) &&
2574 retry_count <= MAX_DRIVER_CMD_RETRIES);
2575 hpsa_pci_unmap(h->pdev, c, 1, data_direction);
2576 if (retry_count > MAX_DRIVER_CMD_RETRIES)
2577 rc = -EIO;
2578 return rc;
2579 }
2580
2581 static void hpsa_print_cmd(struct ctlr_info *h, char *txt,
2582 struct CommandList *c)
2583 {
2584 const u8 *cdb = c->Request.CDB;
2585 const u8 *lun = c->Header.LUN.LunAddrBytes;
2586
2587 dev_warn(&h->pdev->dev, "%s: LUN:%02x%02x%02x%02x%02x%02x%02x%02x"
2588 " CDB:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2589 txt, lun[0], lun[1], lun[2], lun[3],
2590 lun[4], lun[5], lun[6], lun[7],
2591 cdb[0], cdb[1], cdb[2], cdb[3],
2592 cdb[4], cdb[5], cdb[6], cdb[7],
2593 cdb[8], cdb[9], cdb[10], cdb[11],
2594 cdb[12], cdb[13], cdb[14], cdb[15]);
2595 }
2596
2597 static void hpsa_scsi_interpret_error(struct ctlr_info *h,
2598 struct CommandList *cp)
2599 {
2600 const struct ErrorInfo *ei = cp->err_info;
2601 struct device *d = &cp->h->pdev->dev;
2602 u8 sense_key, asc, ascq;
2603 int sense_len;
2604
2605 switch (ei->CommandStatus) {
2606 case CMD_TARGET_STATUS:
2607 if (ei->SenseLen > sizeof(ei->SenseInfo))
2608 sense_len = sizeof(ei->SenseInfo);
2609 else
2610 sense_len = ei->SenseLen;
2611 decode_sense_data(ei->SenseInfo, sense_len,
2612 &sense_key, &asc, &ascq);
2613 hpsa_print_cmd(h, "SCSI status", cp);
2614 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION)
2615 dev_warn(d, "SCSI Status = 02, Sense key = 0x%02x, ASC = 0x%02x, ASCQ = 0x%02x\n",
2616 sense_key, asc, ascq);
2617 else
2618 dev_warn(d, "SCSI Status = 0x%02x\n", ei->ScsiStatus);
2619 if (ei->ScsiStatus == 0)
2620 dev_warn(d, "SCSI status is abnormally zero. "
2621 "(probably indicates selection timeout "
2622 "reported incorrectly due to a known "
2623 "firmware bug, circa July, 2001.)\n");
2624 break;
2625 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
2626 break;
2627 case CMD_DATA_OVERRUN:
2628 hpsa_print_cmd(h, "overrun condition", cp);
2629 break;
2630 case CMD_INVALID: {
2631 /* controller unfortunately reports SCSI passthru's
2632 * to non-existent targets as invalid commands.
2633 */
2634 hpsa_print_cmd(h, "invalid command", cp);
2635 dev_warn(d, "probably means device no longer present\n");
2636 }
2637 break;
2638 case CMD_PROTOCOL_ERR:
2639 hpsa_print_cmd(h, "protocol error", cp);
2640 break;
2641 case CMD_HARDWARE_ERR:
2642 hpsa_print_cmd(h, "hardware error", cp);
2643 break;
2644 case CMD_CONNECTION_LOST:
2645 hpsa_print_cmd(h, "connection lost", cp);
2646 break;
2647 case CMD_ABORTED:
2648 hpsa_print_cmd(h, "aborted", cp);
2649 break;
2650 case CMD_ABORT_FAILED:
2651 hpsa_print_cmd(h, "abort failed", cp);
2652 break;
2653 case CMD_UNSOLICITED_ABORT:
2654 hpsa_print_cmd(h, "unsolicited abort", cp);
2655 break;
2656 case CMD_TIMEOUT:
2657 hpsa_print_cmd(h, "timed out", cp);
2658 break;
2659 case CMD_UNABORTABLE:
2660 hpsa_print_cmd(h, "unabortable", cp);
2661 break;
2662 case CMD_CTLR_LOCKUP:
2663 hpsa_print_cmd(h, "controller lockup detected", cp);
2664 break;
2665 default:
2666 hpsa_print_cmd(h, "unknown status", cp);
2667 dev_warn(d, "Unknown command status %x\n",
2668 ei->CommandStatus);
2669 }
2670 }
2671
2672 static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
2673 u16 page, unsigned char *buf,
2674 unsigned char bufsize)
2675 {
2676 int rc = IO_OK;
2677 struct CommandList *c;
2678 struct ErrorInfo *ei;
2679
2680 c = cmd_alloc(h);
2681
2682 if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
2683 page, scsi3addr, TYPE_CMD)) {
2684 rc = -1;
2685 goto out;
2686 }
2687 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
2688 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
2689 if (rc)
2690 goto out;
2691 ei = c->err_info;
2692 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
2693 hpsa_scsi_interpret_error(h, c);
2694 rc = -1;
2695 }
2696 out:
2697 cmd_free(h, c);
2698 return rc;
2699 }
2700
2701 static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr,
2702 u8 reset_type, int reply_queue)
2703 {
2704 int rc = IO_OK;
2705 struct CommandList *c;
2706 struct ErrorInfo *ei;
2707
2708 c = cmd_alloc(h);
2709
2710
2711 /* fill_cmd can't fail here, no data buffer to map. */
2712 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
2713 scsi3addr, TYPE_MSG);
2714 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to LUN reset */
2715 rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
2716 if (rc) {
2717 dev_warn(&h->pdev->dev, "Failed to send reset command\n");
2718 goto out;
2719 }
2720 /* no unmap needed here because no data xfer. */
2721
2722 ei = c->err_info;
2723 if (ei->CommandStatus != 0) {
2724 hpsa_scsi_interpret_error(h, c);
2725 rc = -1;
2726 }
2727 out:
2728 cmd_free(h, c);
2729 return rc;
2730 }
2731
2732 static bool hpsa_cmd_dev_match(struct ctlr_info *h, struct CommandList *c,
2733 struct hpsa_scsi_dev_t *dev,
2734 unsigned char *scsi3addr)
2735 {
2736 int i;
2737 bool match = false;
2738 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
2739 struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2;
2740
2741 if (hpsa_is_cmd_idle(c))
2742 return false;
2743
2744 switch (c->cmd_type) {
2745 case CMD_SCSI:
2746 case CMD_IOCTL_PEND:
2747 match = !memcmp(scsi3addr, &c->Header.LUN.LunAddrBytes,
2748 sizeof(c->Header.LUN.LunAddrBytes));
2749 break;
2750
2751 case CMD_IOACCEL1:
2752 case CMD_IOACCEL2:
2753 if (c->phys_disk == dev) {
2754 /* HBA mode match */
2755 match = true;
2756 } else {
2757 /* Possible RAID mode -- check each phys dev. */
2758 /* FIXME: Do we need to take out a lock here? If
2759 * so, we could just call hpsa_get_pdisk_of_ioaccel2()
2760 * instead. */
2761 for (i = 0; i < dev->nphysical_disks && !match; i++) {
2762 /* FIXME: an alternate test might be
2763 *
2764 * match = dev->phys_disk[i]->ioaccel_handle
2765 * == c2->scsi_nexus; */
2766 match = dev->phys_disk[i] == c->phys_disk;
2767 }
2768 }
2769 break;
2770
2771 case IOACCEL2_TMF:
2772 for (i = 0; i < dev->nphysical_disks && !match; i++) {
2773 match = dev->phys_disk[i]->ioaccel_handle ==
2774 le32_to_cpu(ac->it_nexus);
2775 }
2776 break;
2777
2778 case 0: /* The command is in the middle of being initialized. */
2779 match = false;
2780 break;
2781
2782 default:
2783 dev_err(&h->pdev->dev, "unexpected cmd_type: %d\n",
2784 c->cmd_type);
2785 BUG();
2786 }
2787
2788 return match;
2789 }
2790
2791 static int hpsa_do_reset(struct ctlr_info *h, struct hpsa_scsi_dev_t *dev,
2792 unsigned char *scsi3addr, u8 reset_type, int reply_queue)
2793 {
2794 int i;
2795 int rc = 0;
2796
2797 /* We can really only handle one reset at a time */
2798 if (mutex_lock_interruptible(&h->reset_mutex) == -EINTR) {
2799 dev_warn(&h->pdev->dev, "concurrent reset wait interrupted.\n");
2800 return -EINTR;
2801 }
2802
2803 BUG_ON(atomic_read(&dev->reset_cmds_out) != 0);
2804
2805 for (i = 0; i < h->nr_cmds; i++) {
2806 struct CommandList *c = h->cmd_pool + i;
2807 int refcount = atomic_inc_return(&c->refcount);
2808
2809 if (refcount > 1 && hpsa_cmd_dev_match(h, c, dev, scsi3addr)) {
2810 unsigned long flags;
2811
2812 /*
2813 * Mark the target command as having a reset pending,
2814 * then lock a lock so that the command cannot complete
2815 * while we're considering it. If the command is not
2816 * idle then count it; otherwise revoke the event.
2817 */
2818 c->reset_pending = dev;
2819 spin_lock_irqsave(&h->lock, flags); /* Implied MB */
2820 if (!hpsa_is_cmd_idle(c))
2821 atomic_inc(&dev->reset_cmds_out);
2822 else
2823 c->reset_pending = NULL;
2824 spin_unlock_irqrestore(&h->lock, flags);
2825 }
2826
2827 cmd_free(h, c);
2828 }
2829
2830 rc = hpsa_send_reset(h, scsi3addr, reset_type, reply_queue);
2831 if (!rc)
2832 wait_event(h->event_sync_wait_queue,
2833 atomic_read(&dev->reset_cmds_out) == 0 ||
2834 lockup_detected(h));
2835
2836 if (unlikely(lockup_detected(h))) {
2837 dev_warn(&h->pdev->dev,
2838 "Controller lockup detected during reset wait\n");
2839 rc = -ENODEV;
2840 }
2841
2842 if (unlikely(rc))
2843 atomic_set(&dev->reset_cmds_out, 0);
2844
2845 mutex_unlock(&h->reset_mutex);
2846 return rc;
2847 }
2848
2849 static void hpsa_get_raid_level(struct ctlr_info *h,
2850 unsigned char *scsi3addr, unsigned char *raid_level)
2851 {
2852 int rc;
2853 unsigned char *buf;
2854
2855 *raid_level = RAID_UNKNOWN;
2856 buf = kzalloc(64, GFP_KERNEL);
2857 if (!buf)
2858 return;
2859 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0xC1, buf, 64);
2860 if (rc == 0)
2861 *raid_level = buf[8];
2862 if (*raid_level > RAID_UNKNOWN)
2863 *raid_level = RAID_UNKNOWN;
2864 kfree(buf);
2865 return;
2866 }
2867
2868 #define HPSA_MAP_DEBUG
2869 #ifdef HPSA_MAP_DEBUG
2870 static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
2871 struct raid_map_data *map_buff)
2872 {
2873 struct raid_map_disk_data *dd = &map_buff->data[0];
2874 int map, row, col;
2875 u16 map_cnt, row_cnt, disks_per_row;
2876
2877 if (rc != 0)
2878 return;
2879
2880 /* Show details only if debugging has been activated. */
2881 if (h->raid_offload_debug < 2)
2882 return;
2883
2884 dev_info(&h->pdev->dev, "structure_size = %u\n",
2885 le32_to_cpu(map_buff->structure_size));
2886 dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
2887 le32_to_cpu(map_buff->volume_blk_size));
2888 dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
2889 le64_to_cpu(map_buff->volume_blk_cnt));
2890 dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
2891 map_buff->phys_blk_shift);
2892 dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
2893 map_buff->parity_rotation_shift);
2894 dev_info(&h->pdev->dev, "strip_size = %u\n",
2895 le16_to_cpu(map_buff->strip_size));
2896 dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
2897 le64_to_cpu(map_buff->disk_starting_blk));
2898 dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
2899 le64_to_cpu(map_buff->disk_blk_cnt));
2900 dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
2901 le16_to_cpu(map_buff->data_disks_per_row));
2902 dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
2903 le16_to_cpu(map_buff->metadata_disks_per_row));
2904 dev_info(&h->pdev->dev, "row_cnt = %u\n",
2905 le16_to_cpu(map_buff->row_cnt));
2906 dev_info(&h->pdev->dev, "layout_map_count = %u\n",
2907 le16_to_cpu(map_buff->layout_map_count));
2908 dev_info(&h->pdev->dev, "flags = 0x%x\n",
2909 le16_to_cpu(map_buff->flags));
2910 dev_info(&h->pdev->dev, "encrypytion = %s\n",
2911 le16_to_cpu(map_buff->flags) &
2912 RAID_MAP_FLAG_ENCRYPT_ON ? "ON" : "OFF");
2913 dev_info(&h->pdev->dev, "dekindex = %u\n",
2914 le16_to_cpu(map_buff->dekindex));
2915 map_cnt = le16_to_cpu(map_buff->layout_map_count);
2916 for (map = 0; map < map_cnt; map++) {
2917 dev_info(&h->pdev->dev, "Map%u:\n", map);
2918 row_cnt = le16_to_cpu(map_buff->row_cnt);
2919 for (row = 0; row < row_cnt; row++) {
2920 dev_info(&h->pdev->dev, " Row%u:\n", row);
2921 disks_per_row =
2922 le16_to_cpu(map_buff->data_disks_per_row);
2923 for (col = 0; col < disks_per_row; col++, dd++)
2924 dev_info(&h->pdev->dev,
2925 " D%02u: h=0x%04x xor=%u,%u\n",
2926 col, dd->ioaccel_handle,
2927 dd->xor_mult[0], dd->xor_mult[1]);
2928 disks_per_row =
2929 le16_to_cpu(map_buff->metadata_disks_per_row);
2930 for (col = 0; col < disks_per_row; col++, dd++)
2931 dev_info(&h->pdev->dev,
2932 " M%02u: h=0x%04x xor=%u,%u\n",
2933 col, dd->ioaccel_handle,
2934 dd->xor_mult[0], dd->xor_mult[1]);
2935 }
2936 }
2937 }
2938 #else
2939 static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
2940 __attribute__((unused)) int rc,
2941 __attribute__((unused)) struct raid_map_data *map_buff)
2942 {
2943 }
2944 #endif
2945
2946 static int hpsa_get_raid_map(struct ctlr_info *h,
2947 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2948 {
2949 int rc = 0;
2950 struct CommandList *c;
2951 struct ErrorInfo *ei;
2952
2953 c = cmd_alloc(h);
2954
2955 if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
2956 sizeof(this_device->raid_map), 0,
2957 scsi3addr, TYPE_CMD)) {
2958 dev_warn(&h->pdev->dev, "hpsa_get_raid_map fill_cmd failed\n");
2959 cmd_free(h, c);
2960 return -1;
2961 }
2962 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
2963 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
2964 if (rc)
2965 goto out;
2966 ei = c->err_info;
2967 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
2968 hpsa_scsi_interpret_error(h, c);
2969 rc = -1;
2970 goto out;
2971 }
2972 cmd_free(h, c);
2973
2974 /* @todo in the future, dynamically allocate RAID map memory */
2975 if (le32_to_cpu(this_device->raid_map.structure_size) >
2976 sizeof(this_device->raid_map)) {
2977 dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
2978 rc = -1;
2979 }
2980 hpsa_debug_map_buff(h, rc, &this_device->raid_map);
2981 return rc;
2982 out:
2983 cmd_free(h, c);
2984 return rc;
2985 }
2986
2987 static int hpsa_bmic_id_physical_device(struct ctlr_info *h,
2988 unsigned char scsi3addr[], u16 bmic_device_index,
2989 struct bmic_identify_physical_device *buf, size_t bufsize)
2990 {
2991 int rc = IO_OK;
2992 struct CommandList *c;
2993 struct ErrorInfo *ei;
2994
2995 c = cmd_alloc(h);
2996 rc = fill_cmd(c, BMIC_IDENTIFY_PHYSICAL_DEVICE, h, buf, bufsize,
2997 0, RAID_CTLR_LUNID, TYPE_CMD);
2998 if (rc)
2999 goto out;
3000
3001 c->Request.CDB[2] = bmic_device_index & 0xff;
3002 c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff;
3003
3004 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE,
3005 NO_TIMEOUT);
3006 ei = c->err_info;
3007 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
3008 hpsa_scsi_interpret_error(h, c);
3009 rc = -1;
3010 }
3011 out:
3012 cmd_free(h, c);
3013 return rc;
3014 }
3015
3016 static int hpsa_vpd_page_supported(struct ctlr_info *h,
3017 unsigned char scsi3addr[], u8 page)
3018 {
3019 int rc;
3020 int i;
3021 int pages;
3022 unsigned char *buf, bufsize;
3023
3024 buf = kzalloc(256, GFP_KERNEL);
3025 if (!buf)
3026 return 0;
3027
3028 /* Get the size of the page list first */
3029 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
3030 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
3031 buf, HPSA_VPD_HEADER_SZ);
3032 if (rc != 0)
3033 goto exit_unsupported;
3034 pages = buf[3];
3035 if ((pages + HPSA_VPD_HEADER_SZ) <= 255)
3036 bufsize = pages + HPSA_VPD_HEADER_SZ;
3037 else
3038 bufsize = 255;
3039
3040 /* Get the whole VPD page list */
3041 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
3042 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
3043 buf, bufsize);
3044 if (rc != 0)
3045 goto exit_unsupported;
3046
3047 pages = buf[3];
3048 for (i = 1; i <= pages; i++)
3049 if (buf[3 + i] == page)
3050 goto exit_supported;
3051 exit_unsupported:
3052 kfree(buf);
3053 return 0;
3054 exit_supported:
3055 kfree(buf);
3056 return 1;
3057 }
3058
3059 static void hpsa_get_ioaccel_status(struct ctlr_info *h,
3060 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
3061 {
3062 int rc;
3063 unsigned char *buf;
3064 u8 ioaccel_status;
3065
3066 this_device->offload_config = 0;
3067 this_device->offload_enabled = 0;
3068 this_device->offload_to_be_enabled = 0;
3069
3070 buf = kzalloc(64, GFP_KERNEL);
3071 if (!buf)
3072 return;
3073 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS))
3074 goto out;
3075 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
3076 VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
3077 if (rc != 0)
3078 goto out;
3079
3080 #define IOACCEL_STATUS_BYTE 4
3081 #define OFFLOAD_CONFIGURED_BIT 0x01
3082 #define OFFLOAD_ENABLED_BIT 0x02
3083 ioaccel_status = buf[IOACCEL_STATUS_BYTE];
3084 this_device->offload_config =
3085 !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
3086 if (this_device->offload_config) {
3087 this_device->offload_enabled =
3088 !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
3089 if (hpsa_get_raid_map(h, scsi3addr, this_device))
3090 this_device->offload_enabled = 0;
3091 }
3092 this_device->offload_to_be_enabled = this_device->offload_enabled;
3093 out:
3094 kfree(buf);
3095 return;
3096 }
3097
3098 /* Get the device id from inquiry page 0x83 */
3099 static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
3100 unsigned char *device_id, int buflen)
3101 {
3102 int rc;
3103 unsigned char *buf;
3104
3105 if (buflen > 16)
3106 buflen = 16;
3107 buf = kzalloc(64, GFP_KERNEL);
3108 if (!buf)
3109 return -ENOMEM;
3110 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0x83, buf, 64);
3111 if (rc == 0)
3112 memcpy(device_id, &buf[8], buflen);
3113 kfree(buf);
3114 return rc != 0;
3115 }
3116
3117 static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
3118 void *buf, int bufsize,
3119 int extended_response)
3120 {
3121 int rc = IO_OK;
3122 struct CommandList *c;
3123 unsigned char scsi3addr[8];
3124 struct ErrorInfo *ei;
3125
3126 c = cmd_alloc(h);
3127
3128 /* address the controller */
3129 memset(scsi3addr, 0, sizeof(scsi3addr));
3130 if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
3131 buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
3132 rc = -1;
3133 goto out;
3134 }
3135 if (extended_response)
3136 c->Request.CDB[1] = extended_response;
3137 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
3138 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
3139 if (rc)
3140 goto out;
3141 ei = c->err_info;
3142 if (ei->CommandStatus != 0 &&
3143 ei->CommandStatus != CMD_DATA_UNDERRUN) {
3144 hpsa_scsi_interpret_error(h, c);
3145 rc = -1;
3146 } else {
3147 struct ReportLUNdata *rld = buf;
3148
3149 if (rld->extended_response_flag != extended_response) {
3150 dev_err(&h->pdev->dev,
3151 "report luns requested format %u, got %u\n",
3152 extended_response,
3153 rld->extended_response_flag);
3154 rc = -1;
3155 }
3156 }
3157 out:
3158 cmd_free(h, c);
3159 return rc;
3160 }
3161
3162 static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
3163 struct ReportExtendedLUNdata *buf, int bufsize)
3164 {
3165 return hpsa_scsi_do_report_luns(h, 0, buf, bufsize,
3166 HPSA_REPORT_PHYS_EXTENDED);
3167 }
3168
3169 static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
3170 struct ReportLUNdata *buf, int bufsize)
3171 {
3172 return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
3173 }
3174
3175 static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
3176 int bus, int target, int lun)
3177 {
3178 device->bus = bus;
3179 device->target = target;
3180 device->lun = lun;
3181 }
3182
3183 /* Use VPD inquiry to get details of volume status */
3184 static int hpsa_get_volume_status(struct ctlr_info *h,
3185 unsigned char scsi3addr[])
3186 {
3187 int rc;
3188 int status;
3189 int size;
3190 unsigned char *buf;
3191
3192 buf = kzalloc(64, GFP_KERNEL);
3193 if (!buf)
3194 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
3195
3196 /* Does controller have VPD for logical volume status? */
3197 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_STATUS))
3198 goto exit_failed;
3199
3200 /* Get the size of the VPD return buffer */
3201 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
3202 buf, HPSA_VPD_HEADER_SZ);
3203 if (rc != 0)
3204 goto exit_failed;
3205 size = buf[3];
3206
3207 /* Now get the whole VPD buffer */
3208 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
3209 buf, size + HPSA_VPD_HEADER_SZ);
3210 if (rc != 0)
3211 goto exit_failed;
3212 status = buf[4]; /* status byte */
3213
3214 kfree(buf);
3215 return status;
3216 exit_failed:
3217 kfree(buf);
3218 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
3219 }
3220
3221 /* Determine offline status of a volume.
3222 * Return either:
3223 * 0 (not offline)
3224 * 0xff (offline for unknown reasons)
3225 * # (integer code indicating one of several NOT READY states
3226 * describing why a volume is to be kept offline)
3227 */
3228 static int hpsa_volume_offline(struct ctlr_info *h,
3229 unsigned char scsi3addr[])
3230 {
3231 struct CommandList *c;
3232 unsigned char *sense;
3233 u8 sense_key, asc, ascq;
3234 int sense_len;
3235 int rc, ldstat = 0;
3236 u16 cmd_status;
3237 u8 scsi_status;
3238 #define ASC_LUN_NOT_READY 0x04
3239 #define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x04
3240 #define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x02
3241
3242 c = cmd_alloc(h);
3243
3244 (void) fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, scsi3addr, TYPE_CMD);
3245 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
3246 if (rc) {
3247 cmd_free(h, c);
3248 return 0;
3249 }
3250 sense = c->err_info->SenseInfo;
3251 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
3252 sense_len = sizeof(c->err_info->SenseInfo);
3253 else
3254 sense_len = c->err_info->SenseLen;
3255 decode_sense_data(sense, sense_len, &sense_key, &asc, &ascq);
3256 cmd_status = c->err_info->CommandStatus;
3257 scsi_status = c->err_info->ScsiStatus;
3258 cmd_free(h, c);
3259 /* Is the volume 'not ready'? */
3260 if (cmd_status != CMD_TARGET_STATUS ||
3261 scsi_status != SAM_STAT_CHECK_CONDITION ||
3262 sense_key != NOT_READY ||
3263 asc != ASC_LUN_NOT_READY) {
3264 return 0;
3265 }
3266
3267 /* Determine the reason for not ready state */
3268 ldstat = hpsa_get_volume_status(h, scsi3addr);
3269
3270 /* Keep volume offline in certain cases: */
3271 switch (ldstat) {
3272 case HPSA_LV_UNDERGOING_ERASE:
3273 case HPSA_LV_NOT_AVAILABLE:
3274 case HPSA_LV_UNDERGOING_RPI:
3275 case HPSA_LV_PENDING_RPI:
3276 case HPSA_LV_ENCRYPTED_NO_KEY:
3277 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
3278 case HPSA_LV_UNDERGOING_ENCRYPTION:
3279 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
3280 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
3281 return ldstat;
3282 case HPSA_VPD_LV_STATUS_UNSUPPORTED:
3283 /* If VPD status page isn't available,
3284 * use ASC/ASCQ to determine state
3285 */
3286 if ((ascq == ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS) ||
3287 (ascq == ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ))
3288 return ldstat;
3289 break;
3290 default:
3291 break;
3292 }
3293 return 0;
3294 }
3295
3296 /*
3297 * Find out if a logical device supports aborts by simply trying one.
3298 * Smart Array may claim not to support aborts on logical drives, but
3299 * if a MSA2000 * is connected, the drives on that will be presented
3300 * by the Smart Array as logical drives, and aborts may be sent to
3301 * those devices successfully. So the simplest way to find out is
3302 * to simply try an abort and see how the device responds.
3303 */
3304 static int hpsa_device_supports_aborts(struct ctlr_info *h,
3305 unsigned char *scsi3addr)
3306 {
3307 struct CommandList *c;
3308 struct ErrorInfo *ei;
3309 int rc = 0;
3310
3311 u64 tag = (u64) -1; /* bogus tag */
3312
3313 /* Assume that physical devices support aborts */
3314 if (!is_logical_dev_addr_mode(scsi3addr))
3315 return 1;
3316
3317 c = cmd_alloc(h);
3318
3319 (void) fill_cmd(c, HPSA_ABORT_MSG, h, &tag, 0, 0, scsi3addr, TYPE_MSG);
3320 (void) hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
3321 /* no unmap needed here because no data xfer. */
3322 ei = c->err_info;
3323 switch (ei->CommandStatus) {
3324 case CMD_INVALID:
3325 rc = 0;
3326 break;
3327 case CMD_UNABORTABLE:
3328 case CMD_ABORT_FAILED:
3329 rc = 1;
3330 break;
3331 case CMD_TMF_STATUS:
3332 rc = hpsa_evaluate_tmf_status(h, c);
3333 break;
3334 default:
3335 rc = 0;
3336 break;
3337 }
3338 cmd_free(h, c);
3339 return rc;
3340 }
3341
3342 static int hpsa_update_device_info(struct ctlr_info *h,
3343 unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
3344 unsigned char *is_OBDR_device)
3345 {
3346
3347 #define OBDR_SIG_OFFSET 43
3348 #define OBDR_TAPE_SIG "$DR-10"
3349 #define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
3350 #define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
3351
3352 unsigned char *inq_buff;
3353 unsigned char *obdr_sig;
3354
3355 inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
3356 if (!inq_buff)
3357 goto bail_out;
3358
3359 /* Do an inquiry to the device to see what it is. */
3360 if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
3361 (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
3362 /* Inquiry failed (msg printed already) */
3363 dev_err(&h->pdev->dev,
3364 "hpsa_update_device_info: inquiry failed\n");
3365 goto bail_out;
3366 }
3367
3368 this_device->devtype = (inq_buff[0] & 0x1f);
3369 memcpy(this_device->scsi3addr, scsi3addr, 8);
3370 memcpy(this_device->vendor, &inq_buff[8],
3371 sizeof(this_device->vendor));
3372 memcpy(this_device->model, &inq_buff[16],
3373 sizeof(this_device->model));
3374 memset(this_device->device_id, 0,
3375 sizeof(this_device->device_id));
3376 hpsa_get_device_id(h, scsi3addr, this_device->device_id,
3377 sizeof(this_device->device_id));
3378
3379 if (this_device->devtype == TYPE_DISK &&
3380 is_logical_dev_addr_mode(scsi3addr)) {
3381 int volume_offline;
3382
3383 hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
3384 if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
3385 hpsa_get_ioaccel_status(h, scsi3addr, this_device);
3386 volume_offline = hpsa_volume_offline(h, scsi3addr);
3387 if (volume_offline < 0 || volume_offline > 0xff)
3388 volume_offline = HPSA_VPD_LV_STATUS_UNSUPPORTED;
3389 this_device->volume_offline = volume_offline & 0xff;
3390 } else {
3391 this_device->raid_level = RAID_UNKNOWN;
3392 this_device->offload_config = 0;
3393 this_device->offload_enabled = 0;
3394 this_device->offload_to_be_enabled = 0;
3395 this_device->hba_ioaccel_enabled = 0;
3396 this_device->volume_offline = 0;
3397 this_device->queue_depth = h->nr_cmds;
3398 }
3399
3400 if (is_OBDR_device) {
3401 /* See if this is a One-Button-Disaster-Recovery device
3402 * by looking for "$DR-10" at offset 43 in inquiry data.
3403 */
3404 obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
3405 *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
3406 strncmp(obdr_sig, OBDR_TAPE_SIG,
3407 OBDR_SIG_LEN) == 0);
3408 }
3409 kfree(inq_buff);
3410 return 0;
3411
3412 bail_out:
3413 kfree(inq_buff);
3414 return 1;
3415 }
3416
3417 static void hpsa_update_device_supports_aborts(struct ctlr_info *h,
3418 struct hpsa_scsi_dev_t *dev, u8 *scsi3addr)
3419 {
3420 unsigned long flags;
3421 int rc, entry;
3422 /*
3423 * See if this device supports aborts. If we already know
3424 * the device, we already know if it supports aborts, otherwise
3425 * we have to find out if it supports aborts by trying one.
3426 */
3427 spin_lock_irqsave(&h->devlock, flags);
3428 rc = hpsa_scsi_find_entry(dev, h->dev, h->ndevices, &entry);
3429 if ((rc == DEVICE_SAME || rc == DEVICE_UPDATED) &&
3430 entry >= 0 && entry < h->ndevices) {
3431 dev->supports_aborts = h->dev[entry]->supports_aborts;
3432 spin_unlock_irqrestore(&h->devlock, flags);
3433 } else {
3434 spin_unlock_irqrestore(&h->devlock, flags);
3435 dev->supports_aborts =
3436 hpsa_device_supports_aborts(h, scsi3addr);
3437 if (dev->supports_aborts < 0)
3438 dev->supports_aborts = 0;
3439 }
3440 }
3441
3442 static unsigned char *ext_target_model[] = {
3443 "MSA2012",
3444 "MSA2024",
3445 "MSA2312",
3446 "MSA2324",
3447 "P2000 G3 SAS",
3448 "MSA 2040 SAS",
3449 NULL,
3450 };
3451
3452 static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
3453 {
3454 int i;
3455
3456 for (i = 0; ext_target_model[i]; i++)
3457 if (strncmp(device->model, ext_target_model[i],
3458 strlen(ext_target_model[i])) == 0)
3459 return 1;
3460 return 0;
3461 }
3462
3463 /* Helper function to assign bus, target, lun mapping of devices.
3464 * Puts non-external target logical volumes on bus 0, external target logical
3465 * volumes on bus 1, physical devices on bus 2. and the hba on bus 3.
3466 * Logical drive target and lun are assigned at this time, but
3467 * physical device lun and target assignment are deferred (assigned
3468 * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
3469 */
3470 static void figure_bus_target_lun(struct ctlr_info *h,
3471 u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
3472 {
3473 u32 lunid = le32_to_cpu(*((__le32 *) lunaddrbytes));
3474
3475 if (!is_logical_dev_addr_mode(lunaddrbytes)) {
3476 /* physical device, target and lun filled in later */
3477 if (is_hba_lunid(lunaddrbytes))
3478 hpsa_set_bus_target_lun(device, 3, 0, lunid & 0x3fff);
3479 else
3480 /* defer target, lun assignment for physical devices */
3481 hpsa_set_bus_target_lun(device, 2, -1, -1);
3482 return;
3483 }
3484 /* It's a logical device */
3485 if (is_ext_target(h, device)) {
3486 /* external target way, put logicals on bus 1
3487 * and match target/lun numbers box
3488 * reports, other smart array, bus 0, target 0, match lunid
3489 */
3490 hpsa_set_bus_target_lun(device,
3491 1, (lunid >> 16) & 0x3fff, lunid & 0x00ff);
3492 return;
3493 }
3494 hpsa_set_bus_target_lun(device, 0, 0, lunid & 0x3fff);
3495 }
3496
3497 /*
3498 * If there is no lun 0 on a target, linux won't find any devices.
3499 * For the external targets (arrays), we have to manually detect the enclosure
3500 * which is at lun zero, as CCISS_REPORT_PHYSICAL_LUNS doesn't report
3501 * it for some reason. *tmpdevice is the target we're adding,
3502 * this_device is a pointer into the current element of currentsd[]
3503 * that we're building up in update_scsi_devices(), below.
3504 * lunzerobits is a bitmap that tracks which targets already have a
3505 * lun 0 assigned.
3506 * Returns 1 if an enclosure was added, 0 if not.
3507 */
3508 static int add_ext_target_dev(struct ctlr_info *h,
3509 struct hpsa_scsi_dev_t *tmpdevice,
3510 struct hpsa_scsi_dev_t *this_device, u8 *lunaddrbytes,
3511 unsigned long lunzerobits[], int *n_ext_target_devs)
3512 {
3513 unsigned char scsi3addr[8];
3514
3515 if (test_bit(tmpdevice->target, lunzerobits))
3516 return 0; /* There is already a lun 0 on this target. */
3517
3518 if (!is_logical_dev_addr_mode(lunaddrbytes))
3519 return 0; /* It's the logical targets that may lack lun 0. */
3520
3521 if (!is_ext_target(h, tmpdevice))
3522 return 0; /* Only external target devices have this problem. */
3523
3524 if (tmpdevice->lun == 0) /* if lun is 0, then we have a lun 0. */
3525 return 0;
3526
3527 memset(scsi3addr, 0, 8);
3528 scsi3addr[3] = tmpdevice->target;
3529 if (is_hba_lunid(scsi3addr))
3530 return 0; /* Don't add the RAID controller here. */
3531
3532 if (is_scsi_rev_5(h))
3533 return 0; /* p1210m doesn't need to do this. */
3534
3535 if (*n_ext_target_devs >= MAX_EXT_TARGETS) {
3536 dev_warn(&h->pdev->dev, "Maximum number of external "
3537 "target devices exceeded. Check your hardware "
3538 "configuration.");
3539 return 0;
3540 }
3541
3542 if (hpsa_update_device_info(h, scsi3addr, this_device, NULL))
3543 return 0;
3544 (*n_ext_target_devs)++;
3545 hpsa_set_bus_target_lun(this_device,
3546 tmpdevice->bus, tmpdevice->target, 0);
3547 hpsa_update_device_supports_aborts(h, this_device, scsi3addr);
3548 set_bit(tmpdevice->target, lunzerobits);
3549 return 1;
3550 }
3551
3552 /*
3553 * Get address of physical disk used for an ioaccel2 mode command:
3554 * 1. Extract ioaccel2 handle from the command.
3555 * 2. Find a matching ioaccel2 handle from list of physical disks.
3556 * 3. Return:
3557 * 1 and set scsi3addr to address of matching physical
3558 * 0 if no matching physical disk was found.
3559 */
3560 static int hpsa_get_pdisk_of_ioaccel2(struct ctlr_info *h,
3561 struct CommandList *ioaccel2_cmd_to_abort, unsigned char *scsi3addr)
3562 {
3563 struct io_accel2_cmd *c2 =
3564 &h->ioaccel2_cmd_pool[ioaccel2_cmd_to_abort->cmdindex];
3565 unsigned long flags;
3566 int i;
3567
3568 spin_lock_irqsave(&h->devlock, flags);
3569 for (i = 0; i < h->ndevices; i++)
3570 if (h->dev[i]->ioaccel_handle == le32_to_cpu(c2->scsi_nexus)) {
3571 memcpy(scsi3addr, h->dev[i]->scsi3addr,
3572 sizeof(h->dev[i]->scsi3addr));
3573 spin_unlock_irqrestore(&h->devlock, flags);
3574 return 1;
3575 }
3576 spin_unlock_irqrestore(&h->devlock, flags);
3577 return 0;
3578 }
3579
3580 /*
3581 * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
3582 * logdev. The number of luns in physdev and logdev are returned in
3583 * *nphysicals and *nlogicals, respectively.
3584 * Returns 0 on success, -1 otherwise.
3585 */
3586 static int hpsa_gather_lun_info(struct ctlr_info *h,
3587 struct ReportExtendedLUNdata *physdev, u32 *nphysicals,
3588 struct ReportLUNdata *logdev, u32 *nlogicals)
3589 {
3590 if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) {
3591 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
3592 return -1;
3593 }
3594 *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) / 24;
3595 if (*nphysicals > HPSA_MAX_PHYS_LUN) {
3596 dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded. %d LUNs ignored.\n",
3597 HPSA_MAX_PHYS_LUN, *nphysicals - HPSA_MAX_PHYS_LUN);
3598 *nphysicals = HPSA_MAX_PHYS_LUN;
3599 }
3600 if (hpsa_scsi_do_report_log_luns(h, logdev, sizeof(*logdev))) {
3601 dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
3602 return -1;
3603 }
3604 *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
3605 /* Reject Logicals in excess of our max capability. */
3606 if (*nlogicals > HPSA_MAX_LUN) {
3607 dev_warn(&h->pdev->dev,
3608 "maximum logical LUNs (%d) exceeded. "
3609 "%d LUNs ignored.\n", HPSA_MAX_LUN,
3610 *nlogicals - HPSA_MAX_LUN);
3611 *nlogicals = HPSA_MAX_LUN;
3612 }
3613 if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
3614 dev_warn(&h->pdev->dev,
3615 "maximum logical + physical LUNs (%d) exceeded. "
3616 "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
3617 *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
3618 *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
3619 }
3620 return 0;
3621 }
3622
3623 static u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position,
3624 int i, int nphysicals, int nlogicals,
3625 struct ReportExtendedLUNdata *physdev_list,
3626 struct ReportLUNdata *logdev_list)
3627 {
3628 /* Helper function, figure out where the LUN ID info is coming from
3629 * given index i, lists of physical and logical devices, where in
3630 * the list the raid controller is supposed to appear (first or last)
3631 */
3632
3633 int logicals_start = nphysicals + (raid_ctlr_position == 0);
3634 int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
3635
3636 if (i == raid_ctlr_position)
3637 return RAID_CTLR_LUNID;
3638
3639 if (i < logicals_start)
3640 return &physdev_list->LUN[i -
3641 (raid_ctlr_position == 0)].lunid[0];
3642
3643 if (i < last_device)
3644 return &logdev_list->LUN[i - nphysicals -
3645 (raid_ctlr_position == 0)][0];
3646 BUG();
3647 return NULL;
3648 }
3649
3650 /* get physical drive ioaccel handle and queue depth */
3651 static void hpsa_get_ioaccel_drive_info(struct ctlr_info *h,
3652 struct hpsa_scsi_dev_t *dev,
3653 u8 *lunaddrbytes,
3654 struct bmic_identify_physical_device *id_phys)
3655 {
3656 int rc;
3657 struct ext_report_lun_entry *rle =
3658 (struct ext_report_lun_entry *) lunaddrbytes;
3659
3660 dev->ioaccel_handle = rle->ioaccel_handle;
3661 if (PHYS_IOACCEL(lunaddrbytes) && dev->ioaccel_handle)
3662 dev->hba_ioaccel_enabled = 1;
3663 memset(id_phys, 0, sizeof(*id_phys));
3664 rc = hpsa_bmic_id_physical_device(h, lunaddrbytes,
3665 GET_BMIC_DRIVE_NUMBER(lunaddrbytes), id_phys,
3666 sizeof(*id_phys));
3667 if (!rc)
3668 /* Reserve space for FW operations */
3669 #define DRIVE_CMDS_RESERVED_FOR_FW 2
3670 #define DRIVE_QUEUE_DEPTH 7
3671 dev->queue_depth =
3672 le16_to_cpu(id_phys->current_queue_depth_limit) -
3673 DRIVE_CMDS_RESERVED_FOR_FW;
3674 else
3675 dev->queue_depth = DRIVE_QUEUE_DEPTH; /* conservative */
3676 atomic_set(&dev->ioaccel_cmds_out, 0);
3677 atomic_set(&dev->reset_cmds_out, 0);
3678 }
3679
3680 static void hpsa_get_path_info(struct hpsa_scsi_dev_t *this_device,
3681 u8 *lunaddrbytes,
3682 struct bmic_identify_physical_device *id_phys)
3683 {
3684 if (PHYS_IOACCEL(lunaddrbytes)
3685 && this_device->ioaccel_handle)
3686 this_device->hba_ioaccel_enabled = 1;
3687
3688 memcpy(&this_device->active_path_index,
3689 &id_phys->active_path_number,
3690 sizeof(this_device->active_path_index));
3691 memcpy(&this_device->path_map,
3692 &id_phys->redundant_path_present_map,
3693 sizeof(this_device->path_map));
3694 memcpy(&this_device->box,
3695 &id_phys->alternate_paths_phys_box_on_port,
3696 sizeof(this_device->box));
3697 memcpy(&this_device->phys_connector,
3698 &id_phys->alternate_paths_phys_connector,
3699 sizeof(this_device->phys_connector));
3700 memcpy(&this_device->bay,
3701 &id_phys->phys_bay_in_box,
3702 sizeof(this_device->bay));
3703 }
3704
3705 static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno)
3706 {
3707 /* the idea here is we could get notified
3708 * that some devices have changed, so we do a report
3709 * physical luns and report logical luns cmd, and adjust
3710 * our list of devices accordingly.
3711 *
3712 * The scsi3addr's of devices won't change so long as the
3713 * adapter is not reset. That means we can rescan and
3714 * tell which devices we already know about, vs. new
3715 * devices, vs. disappearing devices.
3716 */
3717 struct ReportExtendedLUNdata *physdev_list = NULL;
3718 struct ReportLUNdata *logdev_list = NULL;
3719 struct bmic_identify_physical_device *id_phys = NULL;
3720 u32 nphysicals = 0;
3721 u32 nlogicals = 0;
3722 u32 ndev_allocated = 0;
3723 struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
3724 int ncurrent = 0;
3725 int i, n_ext_target_devs, ndevs_to_allocate;
3726 int raid_ctlr_position;
3727 DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
3728
3729 currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
3730 physdev_list = kzalloc(sizeof(*physdev_list), GFP_KERNEL);
3731 logdev_list = kzalloc(sizeof(*logdev_list), GFP_KERNEL);
3732 tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
3733 id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL);
3734
3735 if (!currentsd || !physdev_list || !logdev_list ||
3736 !tmpdevice || !id_phys) {
3737 dev_err(&h->pdev->dev, "out of memory\n");
3738 goto out;
3739 }
3740 memset(lunzerobits, 0, sizeof(lunzerobits));
3741
3742 if (hpsa_gather_lun_info(h, physdev_list, &nphysicals,
3743 logdev_list, &nlogicals))
3744 goto out;
3745
3746 /* We might see up to the maximum number of logical and physical disks
3747 * plus external target devices, and a device for the local RAID
3748 * controller.
3749 */
3750 ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
3751
3752 /* Allocate the per device structures */
3753 for (i = 0; i < ndevs_to_allocate; i++) {
3754 if (i >= HPSA_MAX_DEVICES) {
3755 dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
3756 " %d devices ignored.\n", HPSA_MAX_DEVICES,
3757 ndevs_to_allocate - HPSA_MAX_DEVICES);
3758 break;
3759 }
3760
3761 currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
3762 if (!currentsd[i]) {
3763 dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
3764 __FILE__, __LINE__);
3765 goto out;
3766 }
3767 ndev_allocated++;
3768 }
3769
3770 if (is_scsi_rev_5(h))
3771 raid_ctlr_position = 0;
3772 else
3773 raid_ctlr_position = nphysicals + nlogicals;
3774
3775 /* adjust our table of devices */
3776 n_ext_target_devs = 0;
3777 for (i = 0; i < nphysicals + nlogicals + 1; i++) {
3778 u8 *lunaddrbytes, is_OBDR = 0;
3779
3780 /* Figure out where the LUN ID info is coming from */
3781 lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
3782 i, nphysicals, nlogicals, physdev_list, logdev_list);
3783
3784 /* skip masked non-disk devices */
3785 if (MASKED_DEVICE(lunaddrbytes))
3786 if (i < nphysicals + (raid_ctlr_position == 0) &&
3787 NON_DISK_PHYS_DEV(lunaddrbytes))
3788 continue;
3789
3790 /* Get device type, vendor, model, device id */
3791 if (hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
3792 &is_OBDR))
3793 continue; /* skip it if we can't talk to it. */
3794 figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
3795 hpsa_update_device_supports_aborts(h, tmpdevice, lunaddrbytes);
3796 this_device = currentsd[ncurrent];
3797
3798 /*
3799 * For external target devices, we have to insert a LUN 0 which
3800 * doesn't show up in CCISS_REPORT_PHYSICAL data, but there
3801 * is nonetheless an enclosure device there. We have to
3802 * present that otherwise linux won't find anything if
3803 * there is no lun 0.
3804 */
3805 if (add_ext_target_dev(h, tmpdevice, this_device,
3806 lunaddrbytes, lunzerobits,
3807 &n_ext_target_devs)) {
3808 ncurrent++;
3809 this_device = currentsd[ncurrent];
3810 }
3811
3812 *this_device = *tmpdevice;
3813
3814 /* do not expose masked devices */
3815 if (MASKED_DEVICE(lunaddrbytes) &&
3816 i < nphysicals + (raid_ctlr_position == 0)) {
3817 this_device->expose_state = HPSA_DO_NOT_EXPOSE;
3818 } else {
3819 this_device->expose_state =
3820 HPSA_SG_ATTACH | HPSA_ULD_ATTACH;
3821 }
3822
3823 switch (this_device->devtype) {
3824 case TYPE_ROM:
3825 /* We don't *really* support actual CD-ROM devices,
3826 * just "One Button Disaster Recovery" tape drive
3827 * which temporarily pretends to be a CD-ROM drive.
3828 * So we check that the device is really an OBDR tape
3829 * device by checking for "$DR-10" in bytes 43-48 of
3830 * the inquiry data.
3831 */
3832 if (is_OBDR)
3833 ncurrent++;
3834 break;
3835 case TYPE_DISK:
3836 if (i < nphysicals + (raid_ctlr_position == 0)) {
3837 /* The disk is in HBA mode. */
3838 /* Never use RAID mapper in HBA mode. */
3839 this_device->offload_enabled = 0;
3840 hpsa_get_ioaccel_drive_info(h, this_device,
3841 lunaddrbytes, id_phys);
3842 hpsa_get_path_info(this_device, lunaddrbytes,
3843 id_phys);
3844 }
3845 ncurrent++;
3846 break;
3847 case TYPE_TAPE:
3848 case TYPE_MEDIUM_CHANGER:
3849 case TYPE_ENCLOSURE:
3850 ncurrent++;
3851 break;
3852 case TYPE_RAID:
3853 /* Only present the Smartarray HBA as a RAID controller.
3854 * If it's a RAID controller other than the HBA itself
3855 * (an external RAID controller, MSA500 or similar)
3856 * don't present it.
3857 */
3858 if (!is_hba_lunid(lunaddrbytes))
3859 break;
3860 ncurrent++;
3861 break;
3862 default:
3863 break;
3864 }
3865 if (ncurrent >= HPSA_MAX_DEVICES)
3866 break;
3867 }
3868 adjust_hpsa_scsi_table(h, hostno, currentsd, ncurrent);
3869 out:
3870 kfree(tmpdevice);
3871 for (i = 0; i < ndev_allocated; i++)
3872 kfree(currentsd[i]);
3873 kfree(currentsd);
3874 kfree(physdev_list);
3875 kfree(logdev_list);
3876 kfree(id_phys);
3877 }
3878
3879 static void hpsa_set_sg_descriptor(struct SGDescriptor *desc,
3880 struct scatterlist *sg)
3881 {
3882 u64 addr64 = (u64) sg_dma_address(sg);
3883 unsigned int len = sg_dma_len(sg);
3884
3885 desc->Addr = cpu_to_le64(addr64);
3886 desc->Len = cpu_to_le32(len);
3887 desc->Ext = 0;
3888 }
3889
3890 /*
3891 * hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
3892 * dma mapping and fills in the scatter gather entries of the
3893 * hpsa command, cp.
3894 */
3895 static int hpsa_scatter_gather(struct ctlr_info *h,
3896 struct CommandList *cp,
3897 struct scsi_cmnd *cmd)
3898 {
3899 struct scatterlist *sg;
3900 int use_sg, i, sg_limit, chained, last_sg;
3901 struct SGDescriptor *curr_sg;
3902
3903 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
3904
3905 use_sg = scsi_dma_map(cmd);
3906 if (use_sg < 0)
3907 return use_sg;
3908
3909 if (!use_sg)
3910 goto sglist_finished;
3911
3912 /*
3913 * If the number of entries is greater than the max for a single list,
3914 * then we have a chained list; we will set up all but one entry in the
3915 * first list (the last entry is saved for link information);
3916 * otherwise, we don't have a chained list and we'll set up at each of
3917 * the entries in the one list.
3918 */
3919 curr_sg = cp->SG;
3920 chained = use_sg > h->max_cmd_sg_entries;
3921 sg_limit = chained ? h->max_cmd_sg_entries - 1 : use_sg;
3922 last_sg = scsi_sg_count(cmd) - 1;
3923 scsi_for_each_sg(cmd, sg, sg_limit, i) {
3924 hpsa_set_sg_descriptor(curr_sg, sg);
3925 curr_sg++;
3926 }
3927
3928 if (chained) {
3929 /*
3930 * Continue with the chained list. Set curr_sg to the chained
3931 * list. Modify the limit to the total count less the entries
3932 * we've already set up. Resume the scan at the list entry
3933 * where the previous loop left off.
3934 */
3935 curr_sg = h->cmd_sg_list[cp->cmdindex];
3936 sg_limit = use_sg - sg_limit;
3937 for_each_sg(sg, sg, sg_limit, i) {
3938 hpsa_set_sg_descriptor(curr_sg, sg);
3939 curr_sg++;
3940 }
3941 }
3942
3943 /* Back the pointer up to the last entry and mark it as "last". */
3944 (curr_sg - 1)->Ext = cpu_to_le32(HPSA_SG_LAST);
3945
3946 if (use_sg + chained > h->maxSG)
3947 h->maxSG = use_sg + chained;
3948
3949 if (chained) {
3950 cp->Header.SGList = h->max_cmd_sg_entries;
3951 cp->Header.SGTotal = cpu_to_le16(use_sg + 1);
3952 if (hpsa_map_sg_chain_block(h, cp)) {
3953 scsi_dma_unmap(cmd);
3954 return -1;
3955 }
3956 return 0;
3957 }
3958
3959 sglist_finished:
3960
3961 cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
3962 cp->Header.SGTotal = cpu_to_le16(use_sg); /* total sgs in cmd list */
3963 return 0;
3964 }
3965
3966 #define IO_ACCEL_INELIGIBLE (1)
3967 static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
3968 {
3969 int is_write = 0;
3970 u32 block;
3971 u32 block_cnt;
3972
3973 /* Perform some CDB fixups if needed using 10 byte reads/writes only */
3974 switch (cdb[0]) {
3975 case WRITE_6:
3976 case WRITE_12:
3977 is_write = 1;
3978 case READ_6:
3979 case READ_12:
3980 if (*cdb_len == 6) {
3981 block = (((u32) cdb[2]) << 8) | cdb[3];
3982 block_cnt = cdb[4];
3983 } else {
3984 BUG_ON(*cdb_len != 12);
3985 block = (((u32) cdb[2]) << 24) |
3986 (((u32) cdb[3]) << 16) |
3987 (((u32) cdb[4]) << 8) |
3988 cdb[5];
3989 block_cnt =
3990 (((u32) cdb[6]) << 24) |
3991 (((u32) cdb[7]) << 16) |
3992 (((u32) cdb[8]) << 8) |
3993 cdb[9];
3994 }
3995 if (block_cnt > 0xffff)
3996 return IO_ACCEL_INELIGIBLE;
3997
3998 cdb[0] = is_write ? WRITE_10 : READ_10;
3999 cdb[1] = 0;
4000 cdb[2] = (u8) (block >> 24);
4001 cdb[3] = (u8) (block >> 16);
4002 cdb[4] = (u8) (block >> 8);
4003 cdb[5] = (u8) (block);
4004 cdb[6] = 0;
4005 cdb[7] = (u8) (block_cnt >> 8);
4006 cdb[8] = (u8) (block_cnt);
4007 cdb[9] = 0;
4008 *cdb_len = 10;
4009 break;
4010 }
4011 return 0;
4012 }
4013
4014 static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h,
4015 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
4016 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
4017 {
4018 struct scsi_cmnd *cmd = c->scsi_cmd;
4019 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
4020 unsigned int len;
4021 unsigned int total_len = 0;
4022 struct scatterlist *sg;
4023 u64 addr64;
4024 int use_sg, i;
4025 struct SGDescriptor *curr_sg;
4026 u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
4027
4028 /* TODO: implement chaining support */
4029 if (scsi_sg_count(cmd) > h->ioaccel_maxsg) {
4030 atomic_dec(&phys_disk->ioaccel_cmds_out);
4031 return IO_ACCEL_INELIGIBLE;
4032 }
4033
4034 BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
4035
4036 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
4037 atomic_dec(&phys_disk->ioaccel_cmds_out);
4038 return IO_ACCEL_INELIGIBLE;
4039 }
4040
4041 c->cmd_type = CMD_IOACCEL1;
4042
4043 /* Adjust the DMA address to point to the accelerated command buffer */
4044 c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
4045 (c->cmdindex * sizeof(*cp));
4046 BUG_ON(c->busaddr & 0x0000007F);
4047
4048 use_sg = scsi_dma_map(cmd);
4049 if (use_sg < 0) {
4050 atomic_dec(&phys_disk->ioaccel_cmds_out);
4051 return use_sg;
4052 }
4053
4054 if (use_sg) {
4055 curr_sg = cp->SG;
4056 scsi_for_each_sg(cmd, sg, use_sg, i) {
4057 addr64 = (u64) sg_dma_address(sg);
4058 len = sg_dma_len(sg);
4059 total_len += len;
4060 curr_sg->Addr = cpu_to_le64(addr64);
4061 curr_sg->Len = cpu_to_le32(len);
4062 curr_sg->Ext = cpu_to_le32(0);
4063 curr_sg++;
4064 }
4065 (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST);
4066
4067 switch (cmd->sc_data_direction) {
4068 case DMA_TO_DEVICE:
4069 control |= IOACCEL1_CONTROL_DATA_OUT;
4070 break;
4071 case DMA_FROM_DEVICE:
4072 control |= IOACCEL1_CONTROL_DATA_IN;
4073 break;
4074 case DMA_NONE:
4075 control |= IOACCEL1_CONTROL_NODATAXFER;
4076 break;
4077 default:
4078 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4079 cmd->sc_data_direction);
4080 BUG();
4081 break;
4082 }
4083 } else {
4084 control |= IOACCEL1_CONTROL_NODATAXFER;
4085 }
4086
4087 c->Header.SGList = use_sg;
4088 /* Fill out the command structure to submit */
4089 cp->dev_handle = cpu_to_le16(ioaccel_handle & 0xFFFF);
4090 cp->transfer_len = cpu_to_le32(total_len);
4091 cp->io_flags = cpu_to_le16(IOACCEL1_IOFLAGS_IO_REQ |
4092 (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK));
4093 cp->control = cpu_to_le32(control);
4094 memcpy(cp->CDB, cdb, cdb_len);
4095 memcpy(cp->CISS_LUN, scsi3addr, 8);
4096 /* Tag was already set at init time. */
4097 enqueue_cmd_and_start_io(h, c);
4098 return 0;
4099 }
4100
4101 /*
4102 * Queue a command directly to a device behind the controller using the
4103 * I/O accelerator path.
4104 */
4105 static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
4106 struct CommandList *c)
4107 {
4108 struct scsi_cmnd *cmd = c->scsi_cmd;
4109 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4110
4111 c->phys_disk = dev;
4112
4113 return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
4114 cmd->cmnd, cmd->cmd_len, dev->scsi3addr, dev);
4115 }
4116
4117 /*
4118 * Set encryption parameters for the ioaccel2 request
4119 */
4120 static void set_encrypt_ioaccel2(struct ctlr_info *h,
4121 struct CommandList *c, struct io_accel2_cmd *cp)
4122 {
4123 struct scsi_cmnd *cmd = c->scsi_cmd;
4124 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4125 struct raid_map_data *map = &dev->raid_map;
4126 u64 first_block;
4127
4128 /* Are we doing encryption on this device */
4129 if (!(le16_to_cpu(map->flags) & RAID_MAP_FLAG_ENCRYPT_ON))
4130 return;
4131 /* Set the data encryption key index. */
4132 cp->dekindex = map->dekindex;
4133
4134 /* Set the encryption enable flag, encoded into direction field. */
4135 cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK;
4136
4137 /* Set encryption tweak values based on logical block address
4138 * If block size is 512, tweak value is LBA.
4139 * For other block sizes, tweak is (LBA * block size)/ 512)
4140 */
4141 switch (cmd->cmnd[0]) {
4142 /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */
4143 case WRITE_6:
4144 case READ_6:
4145 first_block = get_unaligned_be16(&cmd->cmnd[2]);
4146 break;
4147 case WRITE_10:
4148 case READ_10:
4149 /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */
4150 case WRITE_12:
4151 case READ_12:
4152 first_block = get_unaligned_be32(&cmd->cmnd[2]);
4153 break;
4154 case WRITE_16:
4155 case READ_16:
4156 first_block = get_unaligned_be64(&cmd->cmnd[2]);
4157 break;
4158 default:
4159 dev_err(&h->pdev->dev,
4160 "ERROR: %s: size (0x%x) not supported for encryption\n",
4161 __func__, cmd->cmnd[0]);
4162 BUG();
4163 break;
4164 }
4165
4166 if (le32_to_cpu(map->volume_blk_size) != 512)
4167 first_block = first_block *
4168 le32_to_cpu(map->volume_blk_size)/512;
4169
4170 cp->tweak_lower = cpu_to_le32(first_block);
4171 cp->tweak_upper = cpu_to_le32(first_block >> 32);
4172 }
4173
4174 static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h,
4175 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
4176 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
4177 {
4178 struct scsi_cmnd *cmd = c->scsi_cmd;
4179 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
4180 struct ioaccel2_sg_element *curr_sg;
4181 int use_sg, i;
4182 struct scatterlist *sg;
4183 u64 addr64;
4184 u32 len;
4185 u32 total_len = 0;
4186
4187 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
4188
4189 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
4190 atomic_dec(&phys_disk->ioaccel_cmds_out);
4191 return IO_ACCEL_INELIGIBLE;
4192 }
4193
4194 c->cmd_type = CMD_IOACCEL2;
4195 /* Adjust the DMA address to point to the accelerated command buffer */
4196 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
4197 (c->cmdindex * sizeof(*cp));
4198 BUG_ON(c->busaddr & 0x0000007F);
4199
4200 memset(cp, 0, sizeof(*cp));
4201 cp->IU_type = IOACCEL2_IU_TYPE;
4202
4203 use_sg = scsi_dma_map(cmd);
4204 if (use_sg < 0) {
4205 atomic_dec(&phys_disk->ioaccel_cmds_out);
4206 return use_sg;
4207 }
4208
4209 if (use_sg) {
4210 curr_sg = cp->sg;
4211 if (use_sg > h->ioaccel_maxsg) {
4212 addr64 = le64_to_cpu(
4213 h->ioaccel2_cmd_sg_list[c->cmdindex]->address);
4214 curr_sg->address = cpu_to_le64(addr64);
4215 curr_sg->length = 0;
4216 curr_sg->reserved[0] = 0;
4217 curr_sg->reserved[1] = 0;
4218 curr_sg->reserved[2] = 0;
4219 curr_sg->chain_indicator = 0x80;
4220
4221 curr_sg = h->ioaccel2_cmd_sg_list[c->cmdindex];
4222 }
4223 scsi_for_each_sg(cmd, sg, use_sg, i) {
4224 addr64 = (u64) sg_dma_address(sg);
4225 len = sg_dma_len(sg);
4226 total_len += len;
4227 curr_sg->address = cpu_to_le64(addr64);
4228 curr_sg->length = cpu_to_le32(len);
4229 curr_sg->reserved[0] = 0;
4230 curr_sg->reserved[1] = 0;
4231 curr_sg->reserved[2] = 0;
4232 curr_sg->chain_indicator = 0;
4233 curr_sg++;
4234 }
4235
4236 switch (cmd->sc_data_direction) {
4237 case DMA_TO_DEVICE:
4238 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4239 cp->direction |= IOACCEL2_DIR_DATA_OUT;
4240 break;
4241 case DMA_FROM_DEVICE:
4242 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4243 cp->direction |= IOACCEL2_DIR_DATA_IN;
4244 break;
4245 case DMA_NONE:
4246 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4247 cp->direction |= IOACCEL2_DIR_NO_DATA;
4248 break;
4249 default:
4250 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4251 cmd->sc_data_direction);
4252 BUG();
4253 break;
4254 }
4255 } else {
4256 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4257 cp->direction |= IOACCEL2_DIR_NO_DATA;
4258 }
4259
4260 /* Set encryption parameters, if necessary */
4261 set_encrypt_ioaccel2(h, c, cp);
4262
4263 cp->scsi_nexus = cpu_to_le32(ioaccel_handle);
4264 cp->Tag = cpu_to_le32(c->cmdindex << DIRECT_LOOKUP_SHIFT);
4265 memcpy(cp->cdb, cdb, sizeof(cp->cdb));
4266
4267 cp->data_len = cpu_to_le32(total_len);
4268 cp->err_ptr = cpu_to_le64(c->busaddr +
4269 offsetof(struct io_accel2_cmd, error_data));
4270 cp->err_len = cpu_to_le32(sizeof(cp->error_data));
4271
4272 /* fill in sg elements */
4273 if (use_sg > h->ioaccel_maxsg) {
4274 cp->sg_count = 1;
4275 if (hpsa_map_ioaccel2_sg_chain_block(h, cp, c)) {
4276 atomic_dec(&phys_disk->ioaccel_cmds_out);
4277 scsi_dma_unmap(cmd);
4278 return -1;
4279 }
4280 } else
4281 cp->sg_count = (u8) use_sg;
4282
4283 enqueue_cmd_and_start_io(h, c);
4284 return 0;
4285 }
4286
4287 /*
4288 * Queue a command to the correct I/O accelerator path.
4289 */
4290 static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
4291 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
4292 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
4293 {
4294 /* Try to honor the device's queue depth */
4295 if (atomic_inc_return(&phys_disk->ioaccel_cmds_out) >
4296 phys_disk->queue_depth) {
4297 atomic_dec(&phys_disk->ioaccel_cmds_out);
4298 return IO_ACCEL_INELIGIBLE;
4299 }
4300 if (h->transMethod & CFGTBL_Trans_io_accel1)
4301 return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle,
4302 cdb, cdb_len, scsi3addr,
4303 phys_disk);
4304 else
4305 return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle,
4306 cdb, cdb_len, scsi3addr,
4307 phys_disk);
4308 }
4309
4310 static void raid_map_helper(struct raid_map_data *map,
4311 int offload_to_mirror, u32 *map_index, u32 *current_group)
4312 {
4313 if (offload_to_mirror == 0) {
4314 /* use physical disk in the first mirrored group. */
4315 *map_index %= le16_to_cpu(map->data_disks_per_row);
4316 return;
4317 }
4318 do {
4319 /* determine mirror group that *map_index indicates */
4320 *current_group = *map_index /
4321 le16_to_cpu(map->data_disks_per_row);
4322 if (offload_to_mirror == *current_group)
4323 continue;
4324 if (*current_group < le16_to_cpu(map->layout_map_count) - 1) {
4325 /* select map index from next group */
4326 *map_index += le16_to_cpu(map->data_disks_per_row);
4327 (*current_group)++;
4328 } else {
4329 /* select map index from first group */
4330 *map_index %= le16_to_cpu(map->data_disks_per_row);
4331 *current_group = 0;
4332 }
4333 } while (offload_to_mirror != *current_group);
4334 }
4335
4336 /*
4337 * Attempt to perform offload RAID mapping for a logical volume I/O.
4338 */
4339 static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
4340 struct CommandList *c)
4341 {
4342 struct scsi_cmnd *cmd = c->scsi_cmd;
4343 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4344 struct raid_map_data *map = &dev->raid_map;
4345 struct raid_map_disk_data *dd = &map->data[0];
4346 int is_write = 0;
4347 u32 map_index;
4348 u64 first_block, last_block;
4349 u32 block_cnt;
4350 u32 blocks_per_row;
4351 u64 first_row, last_row;
4352 u32 first_row_offset, last_row_offset;
4353 u32 first_column, last_column;
4354 u64 r0_first_row, r0_last_row;
4355 u32 r5or6_blocks_per_row;
4356 u64 r5or6_first_row, r5or6_last_row;
4357 u32 r5or6_first_row_offset, r5or6_last_row_offset;
4358 u32 r5or6_first_column, r5or6_last_column;
4359 u32 total_disks_per_row;
4360 u32 stripesize;
4361 u32 first_group, last_group, current_group;
4362 u32 map_row;
4363 u32 disk_handle;
4364 u64 disk_block;
4365 u32 disk_block_cnt;
4366 u8 cdb[16];
4367 u8 cdb_len;
4368 u16 strip_size;
4369 #if BITS_PER_LONG == 32
4370 u64 tmpdiv;
4371 #endif
4372 int offload_to_mirror;
4373
4374 /* check for valid opcode, get LBA and block count */
4375 switch (cmd->cmnd[0]) {
4376 case WRITE_6:
4377 is_write = 1;
4378 case READ_6:
4379 first_block =
4380 (((u64) cmd->cmnd[2]) << 8) |
4381 cmd->cmnd[3];
4382 block_cnt = cmd->cmnd[4];
4383 if (block_cnt == 0)
4384 block_cnt = 256;
4385 break;
4386 case WRITE_10:
4387 is_write = 1;
4388 case READ_10:
4389 first_block =
4390 (((u64) cmd->cmnd[2]) << 24) |
4391 (((u64) cmd->cmnd[3]) << 16) |
4392 (((u64) cmd->cmnd[4]) << 8) |
4393 cmd->cmnd[5];
4394 block_cnt =
4395 (((u32) cmd->cmnd[7]) << 8) |
4396 cmd->cmnd[8];
4397 break;
4398 case WRITE_12:
4399 is_write = 1;
4400 case READ_12:
4401 first_block =
4402 (((u64) cmd->cmnd[2]) << 24) |
4403 (((u64) cmd->cmnd[3]) << 16) |
4404 (((u64) cmd->cmnd[4]) << 8) |
4405 cmd->cmnd[5];
4406 block_cnt =
4407 (((u32) cmd->cmnd[6]) << 24) |
4408 (((u32) cmd->cmnd[7]) << 16) |
4409 (((u32) cmd->cmnd[8]) << 8) |
4410 cmd->cmnd[9];
4411 break;
4412 case WRITE_16:
4413 is_write = 1;
4414 case READ_16:
4415 first_block =
4416 (((u64) cmd->cmnd[2]) << 56) |
4417 (((u64) cmd->cmnd[3]) << 48) |
4418 (((u64) cmd->cmnd[4]) << 40) |
4419 (((u64) cmd->cmnd[5]) << 32) |
4420 (((u64) cmd->cmnd[6]) << 24) |
4421 (((u64) cmd->cmnd[7]) << 16) |
4422 (((u64) cmd->cmnd[8]) << 8) |
4423 cmd->cmnd[9];
4424 block_cnt =
4425 (((u32) cmd->cmnd[10]) << 24) |
4426 (((u32) cmd->cmnd[11]) << 16) |
4427 (((u32) cmd->cmnd[12]) << 8) |
4428 cmd->cmnd[13];
4429 break;
4430 default:
4431 return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
4432 }
4433 last_block = first_block + block_cnt - 1;
4434
4435 /* check for write to non-RAID-0 */
4436 if (is_write && dev->raid_level != 0)
4437 return IO_ACCEL_INELIGIBLE;
4438
4439 /* check for invalid block or wraparound */
4440 if (last_block >= le64_to_cpu(map->volume_blk_cnt) ||
4441 last_block < first_block)
4442 return IO_ACCEL_INELIGIBLE;
4443
4444 /* calculate stripe information for the request */
4445 blocks_per_row = le16_to_cpu(map->data_disks_per_row) *
4446 le16_to_cpu(map->strip_size);
4447 strip_size = le16_to_cpu(map->strip_size);
4448 #if BITS_PER_LONG == 32
4449 tmpdiv = first_block;
4450 (void) do_div(tmpdiv, blocks_per_row);
4451 first_row = tmpdiv;
4452 tmpdiv = last_block;
4453 (void) do_div(tmpdiv, blocks_per_row);
4454 last_row = tmpdiv;
4455 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
4456 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
4457 tmpdiv = first_row_offset;
4458 (void) do_div(tmpdiv, strip_size);
4459 first_column = tmpdiv;
4460 tmpdiv = last_row_offset;
4461 (void) do_div(tmpdiv, strip_size);
4462 last_column = tmpdiv;
4463 #else
4464 first_row = first_block / blocks_per_row;
4465 last_row = last_block / blocks_per_row;
4466 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
4467 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
4468 first_column = first_row_offset / strip_size;
4469 last_column = last_row_offset / strip_size;
4470 #endif
4471
4472 /* if this isn't a single row/column then give to the controller */
4473 if ((first_row != last_row) || (first_column != last_column))
4474 return IO_ACCEL_INELIGIBLE;
4475
4476 /* proceeding with driver mapping */
4477 total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
4478 le16_to_cpu(map->metadata_disks_per_row);
4479 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
4480 le16_to_cpu(map->row_cnt);
4481 map_index = (map_row * total_disks_per_row) + first_column;
4482
4483 switch (dev->raid_level) {
4484 case HPSA_RAID_0:
4485 break; /* nothing special to do */
4486 case HPSA_RAID_1:
4487 /* Handles load balance across RAID 1 members.
4488 * (2-drive R1 and R10 with even # of drives.)
4489 * Appropriate for SSDs, not optimal for HDDs
4490 */
4491 BUG_ON(le16_to_cpu(map->layout_map_count) != 2);
4492 if (dev->offload_to_mirror)
4493 map_index += le16_to_cpu(map->data_disks_per_row);
4494 dev->offload_to_mirror = !dev->offload_to_mirror;
4495 break;
4496 case HPSA_RAID_ADM:
4497 /* Handles N-way mirrors (R1-ADM)
4498 * and R10 with # of drives divisible by 3.)
4499 */
4500 BUG_ON(le16_to_cpu(map->layout_map_count) != 3);
4501
4502 offload_to_mirror = dev->offload_to_mirror;
4503 raid_map_helper(map, offload_to_mirror,
4504 &map_index, &current_group);
4505 /* set mirror group to use next time */
4506 offload_to_mirror =
4507 (offload_to_mirror >=
4508 le16_to_cpu(map->layout_map_count) - 1)
4509 ? 0 : offload_to_mirror + 1;
4510 dev->offload_to_mirror = offload_to_mirror;
4511 /* Avoid direct use of dev->offload_to_mirror within this
4512 * function since multiple threads might simultaneously
4513 * increment it beyond the range of dev->layout_map_count -1.
4514 */
4515 break;
4516 case HPSA_RAID_5:
4517 case HPSA_RAID_6:
4518 if (le16_to_cpu(map->layout_map_count) <= 1)
4519 break;
4520
4521 /* Verify first and last block are in same RAID group */
4522 r5or6_blocks_per_row =
4523 le16_to_cpu(map->strip_size) *
4524 le16_to_cpu(map->data_disks_per_row);
4525 BUG_ON(r5or6_blocks_per_row == 0);
4526 stripesize = r5or6_blocks_per_row *
4527 le16_to_cpu(map->layout_map_count);
4528 #if BITS_PER_LONG == 32
4529 tmpdiv = first_block;
4530 first_group = do_div(tmpdiv, stripesize);
4531 tmpdiv = first_group;
4532 (void) do_div(tmpdiv, r5or6_blocks_per_row);
4533 first_group = tmpdiv;
4534 tmpdiv = last_block;
4535 last_group = do_div(tmpdiv, stripesize);
4536 tmpdiv = last_group;
4537 (void) do_div(tmpdiv, r5or6_blocks_per_row);
4538 last_group = tmpdiv;
4539 #else
4540 first_group = (first_block % stripesize) / r5or6_blocks_per_row;
4541 last_group = (last_block % stripesize) / r5or6_blocks_per_row;
4542 #endif
4543 if (first_group != last_group)
4544 return IO_ACCEL_INELIGIBLE;
4545
4546 /* Verify request is in a single row of RAID 5/6 */
4547 #if BITS_PER_LONG == 32
4548 tmpdiv = first_block;
4549 (void) do_div(tmpdiv, stripesize);
4550 first_row = r5or6_first_row = r0_first_row = tmpdiv;
4551 tmpdiv = last_block;
4552 (void) do_div(tmpdiv, stripesize);
4553 r5or6_last_row = r0_last_row = tmpdiv;
4554 #else
4555 first_row = r5or6_first_row = r0_first_row =
4556 first_block / stripesize;
4557 r5or6_last_row = r0_last_row = last_block / stripesize;
4558 #endif
4559 if (r5or6_first_row != r5or6_last_row)
4560 return IO_ACCEL_INELIGIBLE;
4561
4562
4563 /* Verify request is in a single column */
4564 #if BITS_PER_LONG == 32
4565 tmpdiv = first_block;
4566 first_row_offset = do_div(tmpdiv, stripesize);
4567 tmpdiv = first_row_offset;
4568 first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row);
4569 r5or6_first_row_offset = first_row_offset;
4570 tmpdiv = last_block;
4571 r5or6_last_row_offset = do_div(tmpdiv, stripesize);
4572 tmpdiv = r5or6_last_row_offset;
4573 r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row);
4574 tmpdiv = r5or6_first_row_offset;
4575 (void) do_div(tmpdiv, map->strip_size);
4576 first_column = r5or6_first_column = tmpdiv;
4577 tmpdiv = r5or6_last_row_offset;
4578 (void) do_div(tmpdiv, map->strip_size);
4579 r5or6_last_column = tmpdiv;
4580 #else
4581 first_row_offset = r5or6_first_row_offset =
4582 (u32)((first_block % stripesize) %
4583 r5or6_blocks_per_row);
4584
4585 r5or6_last_row_offset =
4586 (u32)((last_block % stripesize) %
4587 r5or6_blocks_per_row);
4588
4589 first_column = r5or6_first_column =
4590 r5or6_first_row_offset / le16_to_cpu(map->strip_size);
4591 r5or6_last_column =
4592 r5or6_last_row_offset / le16_to_cpu(map->strip_size);
4593 #endif
4594 if (r5or6_first_column != r5or6_last_column)
4595 return IO_ACCEL_INELIGIBLE;
4596
4597 /* Request is eligible */
4598 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
4599 le16_to_cpu(map->row_cnt);
4600
4601 map_index = (first_group *
4602 (le16_to_cpu(map->row_cnt) * total_disks_per_row)) +
4603 (map_row * total_disks_per_row) + first_column;
4604 break;
4605 default:
4606 return IO_ACCEL_INELIGIBLE;
4607 }
4608
4609 if (unlikely(map_index >= RAID_MAP_MAX_ENTRIES))
4610 return IO_ACCEL_INELIGIBLE;
4611
4612 c->phys_disk = dev->phys_disk[map_index];
4613
4614 disk_handle = dd[map_index].ioaccel_handle;
4615 disk_block = le64_to_cpu(map->disk_starting_blk) +
4616 first_row * le16_to_cpu(map->strip_size) +
4617 (first_row_offset - first_column *
4618 le16_to_cpu(map->strip_size));
4619 disk_block_cnt = block_cnt;
4620
4621 /* handle differing logical/physical block sizes */
4622 if (map->phys_blk_shift) {
4623 disk_block <<= map->phys_blk_shift;
4624 disk_block_cnt <<= map->phys_blk_shift;
4625 }
4626 BUG_ON(disk_block_cnt > 0xffff);
4627
4628 /* build the new CDB for the physical disk I/O */
4629 if (disk_block > 0xffffffff) {
4630 cdb[0] = is_write ? WRITE_16 : READ_16;
4631 cdb[1] = 0;
4632 cdb[2] = (u8) (disk_block >> 56);
4633 cdb[3] = (u8) (disk_block >> 48);
4634 cdb[4] = (u8) (disk_block >> 40);
4635 cdb[5] = (u8) (disk_block >> 32);
4636 cdb[6] = (u8) (disk_block >> 24);
4637 cdb[7] = (u8) (disk_block >> 16);
4638 cdb[8] = (u8) (disk_block >> 8);
4639 cdb[9] = (u8) (disk_block);
4640 cdb[10] = (u8) (disk_block_cnt >> 24);
4641 cdb[11] = (u8) (disk_block_cnt >> 16);
4642 cdb[12] = (u8) (disk_block_cnt >> 8);
4643 cdb[13] = (u8) (disk_block_cnt);
4644 cdb[14] = 0;
4645 cdb[15] = 0;
4646 cdb_len = 16;
4647 } else {
4648 cdb[0] = is_write ? WRITE_10 : READ_10;
4649 cdb[1] = 0;
4650 cdb[2] = (u8) (disk_block >> 24);
4651 cdb[3] = (u8) (disk_block >> 16);
4652 cdb[4] = (u8) (disk_block >> 8);
4653 cdb[5] = (u8) (disk_block);
4654 cdb[6] = 0;
4655 cdb[7] = (u8) (disk_block_cnt >> 8);
4656 cdb[8] = (u8) (disk_block_cnt);
4657 cdb[9] = 0;
4658 cdb_len = 10;
4659 }
4660 return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
4661 dev->scsi3addr,
4662 dev->phys_disk[map_index]);
4663 }
4664
4665 /*
4666 * Submit commands down the "normal" RAID stack path
4667 * All callers to hpsa_ciss_submit must check lockup_detected
4668 * beforehand, before (opt.) and after calling cmd_alloc
4669 */
4670 static int hpsa_ciss_submit(struct ctlr_info *h,
4671 struct CommandList *c, struct scsi_cmnd *cmd,
4672 unsigned char scsi3addr[])
4673 {
4674 cmd->host_scribble = (unsigned char *) c;
4675 c->cmd_type = CMD_SCSI;
4676 c->scsi_cmd = cmd;
4677 c->Header.ReplyQueue = 0; /* unused in simple mode */
4678 memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
4679 c->Header.tag = cpu_to_le64((c->cmdindex << DIRECT_LOOKUP_SHIFT));
4680
4681 /* Fill in the request block... */
4682
4683 c->Request.Timeout = 0;
4684 BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
4685 c->Request.CDBLen = cmd->cmd_len;
4686 memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
4687 switch (cmd->sc_data_direction) {
4688 case DMA_TO_DEVICE:
4689 c->Request.type_attr_dir =
4690 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_WRITE);
4691 break;
4692 case DMA_FROM_DEVICE:
4693 c->Request.type_attr_dir =
4694 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_READ);
4695 break;
4696 case DMA_NONE:
4697 c->Request.type_attr_dir =
4698 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_NONE);
4699 break;
4700 case DMA_BIDIRECTIONAL:
4701 /* This can happen if a buggy application does a scsi passthru
4702 * and sets both inlen and outlen to non-zero. ( see
4703 * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
4704 */
4705
4706 c->Request.type_attr_dir =
4707 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_RSVD);
4708 /* This is technically wrong, and hpsa controllers should
4709 * reject it with CMD_INVALID, which is the most correct
4710 * response, but non-fibre backends appear to let it
4711 * slide by, and give the same results as if this field
4712 * were set correctly. Either way is acceptable for
4713 * our purposes here.
4714 */
4715
4716 break;
4717
4718 default:
4719 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4720 cmd->sc_data_direction);
4721 BUG();
4722 break;
4723 }
4724
4725 if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
4726 hpsa_cmd_resolve_and_free(h, c);
4727 return SCSI_MLQUEUE_HOST_BUSY;
4728 }
4729 enqueue_cmd_and_start_io(h, c);
4730 /* the cmd'll come back via intr handler in complete_scsi_command() */
4731 return 0;
4732 }
4733
4734 static void hpsa_cmd_init(struct ctlr_info *h, int index,
4735 struct CommandList *c)
4736 {
4737 dma_addr_t cmd_dma_handle, err_dma_handle;
4738
4739 /* Zero out all of commandlist except the last field, refcount */
4740 memset(c, 0, offsetof(struct CommandList, refcount));
4741 c->Header.tag = cpu_to_le64((u64) (index << DIRECT_LOOKUP_SHIFT));
4742 cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
4743 c->err_info = h->errinfo_pool + index;
4744 memset(c->err_info, 0, sizeof(*c->err_info));
4745 err_dma_handle = h->errinfo_pool_dhandle
4746 + index * sizeof(*c->err_info);
4747 c->cmdindex = index;
4748 c->busaddr = (u32) cmd_dma_handle;
4749 c->ErrDesc.Addr = cpu_to_le64((u64) err_dma_handle);
4750 c->ErrDesc.Len = cpu_to_le32((u32) sizeof(*c->err_info));
4751 c->h = h;
4752 c->scsi_cmd = SCSI_CMD_IDLE;
4753 }
4754
4755 static void hpsa_preinitialize_commands(struct ctlr_info *h)
4756 {
4757 int i;
4758
4759 for (i = 0; i < h->nr_cmds; i++) {
4760 struct CommandList *c = h->cmd_pool + i;
4761
4762 hpsa_cmd_init(h, i, c);
4763 atomic_set(&c->refcount, 0);
4764 }
4765 }
4766
4767 static inline void hpsa_cmd_partial_init(struct ctlr_info *h, int index,
4768 struct CommandList *c)
4769 {
4770 dma_addr_t cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
4771
4772 BUG_ON(c->cmdindex != index);
4773
4774 memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
4775 memset(c->err_info, 0, sizeof(*c->err_info));
4776 c->busaddr = (u32) cmd_dma_handle;
4777 }
4778
4779 static int hpsa_ioaccel_submit(struct ctlr_info *h,
4780 struct CommandList *c, struct scsi_cmnd *cmd,
4781 unsigned char *scsi3addr)
4782 {
4783 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4784 int rc = IO_ACCEL_INELIGIBLE;
4785
4786 cmd->host_scribble = (unsigned char *) c;
4787
4788 if (dev->offload_enabled) {
4789 hpsa_cmd_init(h, c->cmdindex, c);
4790 c->cmd_type = CMD_SCSI;
4791 c->scsi_cmd = cmd;
4792 rc = hpsa_scsi_ioaccel_raid_map(h, c);
4793 if (rc < 0) /* scsi_dma_map failed. */
4794 rc = SCSI_MLQUEUE_HOST_BUSY;
4795 } else if (dev->hba_ioaccel_enabled) {
4796 hpsa_cmd_init(h, c->cmdindex, c);
4797 c->cmd_type = CMD_SCSI;
4798 c->scsi_cmd = cmd;
4799 rc = hpsa_scsi_ioaccel_direct_map(h, c);
4800 if (rc < 0) /* scsi_dma_map failed. */
4801 rc = SCSI_MLQUEUE_HOST_BUSY;
4802 }
4803 return rc;
4804 }
4805
4806 static void hpsa_command_resubmit_worker(struct work_struct *work)
4807 {
4808 struct scsi_cmnd *cmd;
4809 struct hpsa_scsi_dev_t *dev;
4810 struct CommandList *c = container_of(work, struct CommandList, work);
4811
4812 cmd = c->scsi_cmd;
4813 dev = cmd->device->hostdata;
4814 if (!dev) {
4815 cmd->result = DID_NO_CONNECT << 16;
4816 return hpsa_cmd_free_and_done(c->h, c, cmd);
4817 }
4818 if (c->reset_pending)
4819 return hpsa_cmd_resolve_and_free(c->h, c);
4820 if (c->abort_pending)
4821 return hpsa_cmd_abort_and_free(c->h, c, cmd);
4822 if (c->cmd_type == CMD_IOACCEL2) {
4823 struct ctlr_info *h = c->h;
4824 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
4825 int rc;
4826
4827 if (c2->error_data.serv_response ==
4828 IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL) {
4829 rc = hpsa_ioaccel_submit(h, c, cmd, dev->scsi3addr);
4830 if (rc == 0)
4831 return;
4832 if (rc == SCSI_MLQUEUE_HOST_BUSY) {
4833 /*
4834 * If we get here, it means dma mapping failed.
4835 * Try again via scsi mid layer, which will
4836 * then get SCSI_MLQUEUE_HOST_BUSY.
4837 */
4838 cmd->result = DID_IMM_RETRY << 16;
4839 return hpsa_cmd_free_and_done(h, c, cmd);
4840 }
4841 /* else, fall thru and resubmit down CISS path */
4842 }
4843 }
4844 hpsa_cmd_partial_init(c->h, c->cmdindex, c);
4845 if (hpsa_ciss_submit(c->h, c, cmd, dev->scsi3addr)) {
4846 /*
4847 * If we get here, it means dma mapping failed. Try
4848 * again via scsi mid layer, which will then get
4849 * SCSI_MLQUEUE_HOST_BUSY.
4850 *
4851 * hpsa_ciss_submit will have already freed c
4852 * if it encountered a dma mapping failure.
4853 */
4854 cmd->result = DID_IMM_RETRY << 16;
4855 cmd->scsi_done(cmd);
4856 }
4857 }
4858
4859 /* Running in struct Scsi_Host->host_lock less mode */
4860 static int hpsa_scsi_queue_command(struct Scsi_Host *sh, struct scsi_cmnd *cmd)
4861 {
4862 struct ctlr_info *h;
4863 struct hpsa_scsi_dev_t *dev;
4864 unsigned char scsi3addr[8];
4865 struct CommandList *c;
4866 int rc = 0;
4867
4868 /* Get the ptr to our adapter structure out of cmd->host. */
4869 h = sdev_to_hba(cmd->device);
4870
4871 BUG_ON(cmd->request->tag < 0);
4872
4873 dev = cmd->device->hostdata;
4874 if (!dev) {
4875 cmd->result = DID_NO_CONNECT << 16;
4876 cmd->scsi_done(cmd);
4877 return 0;
4878 }
4879
4880 memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
4881
4882 if (unlikely(lockup_detected(h))) {
4883 cmd->result = DID_NO_CONNECT << 16;
4884 cmd->scsi_done(cmd);
4885 return 0;
4886 }
4887 c = cmd_tagged_alloc(h, cmd);
4888
4889 /*
4890 * Call alternate submit routine for I/O accelerated commands.
4891 * Retries always go down the normal I/O path.
4892 */
4893 if (likely(cmd->retries == 0 &&
4894 cmd->request->cmd_type == REQ_TYPE_FS &&
4895 h->acciopath_status)) {
4896 rc = hpsa_ioaccel_submit(h, c, cmd, scsi3addr);
4897 if (rc == 0)
4898 return 0;
4899 if (rc == SCSI_MLQUEUE_HOST_BUSY) {
4900 hpsa_cmd_resolve_and_free(h, c);
4901 return SCSI_MLQUEUE_HOST_BUSY;
4902 }
4903 }
4904 return hpsa_ciss_submit(h, c, cmd, scsi3addr);
4905 }
4906
4907 static void hpsa_scan_complete(struct ctlr_info *h)
4908 {
4909 unsigned long flags;
4910
4911 spin_lock_irqsave(&h->scan_lock, flags);
4912 h->scan_finished = 1;
4913 wake_up_all(&h->scan_wait_queue);
4914 spin_unlock_irqrestore(&h->scan_lock, flags);
4915 }
4916
4917 static void hpsa_scan_start(struct Scsi_Host *sh)
4918 {
4919 struct ctlr_info *h = shost_to_hba(sh);
4920 unsigned long flags;
4921
4922 /*
4923 * Don't let rescans be initiated on a controller known to be locked
4924 * up. If the controller locks up *during* a rescan, that thread is
4925 * probably hosed, but at least we can prevent new rescan threads from
4926 * piling up on a locked up controller.
4927 */
4928 if (unlikely(lockup_detected(h)))
4929 return hpsa_scan_complete(h);
4930
4931 /* wait until any scan already in progress is finished. */
4932 while (1) {
4933 spin_lock_irqsave(&h->scan_lock, flags);
4934 if (h->scan_finished)
4935 break;
4936 spin_unlock_irqrestore(&h->scan_lock, flags);
4937 wait_event(h->scan_wait_queue, h->scan_finished);
4938 /* Note: We don't need to worry about a race between this
4939 * thread and driver unload because the midlayer will
4940 * have incremented the reference count, so unload won't
4941 * happen if we're in here.
4942 */
4943 }
4944 h->scan_finished = 0; /* mark scan as in progress */
4945 spin_unlock_irqrestore(&h->scan_lock, flags);
4946
4947 if (unlikely(lockup_detected(h)))
4948 return hpsa_scan_complete(h);
4949
4950 hpsa_update_scsi_devices(h, h->scsi_host->host_no);
4951
4952 hpsa_scan_complete(h);
4953 }
4954
4955 static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth)
4956 {
4957 struct hpsa_scsi_dev_t *logical_drive = sdev->hostdata;
4958
4959 if (!logical_drive)
4960 return -ENODEV;
4961
4962 if (qdepth < 1)
4963 qdepth = 1;
4964 else if (qdepth > logical_drive->queue_depth)
4965 qdepth = logical_drive->queue_depth;
4966
4967 return scsi_change_queue_depth(sdev, qdepth);
4968 }
4969
4970 static int hpsa_scan_finished(struct Scsi_Host *sh,
4971 unsigned long elapsed_time)
4972 {
4973 struct ctlr_info *h = shost_to_hba(sh);
4974 unsigned long flags;
4975 int finished;
4976
4977 spin_lock_irqsave(&h->scan_lock, flags);
4978 finished = h->scan_finished;
4979 spin_unlock_irqrestore(&h->scan_lock, flags);
4980 return finished;
4981 }
4982
4983 static int hpsa_scsi_host_alloc(struct ctlr_info *h)
4984 {
4985 struct Scsi_Host *sh;
4986 int error;
4987
4988 sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
4989 if (sh == NULL) {
4990 dev_err(&h->pdev->dev, "scsi_host_alloc failed\n");
4991 return -ENOMEM;
4992 }
4993
4994 sh->io_port = 0;
4995 sh->n_io_port = 0;
4996 sh->this_id = -1;
4997 sh->max_channel = 3;
4998 sh->max_cmd_len = MAX_COMMAND_SIZE;
4999 sh->max_lun = HPSA_MAX_LUN;
5000 sh->max_id = HPSA_MAX_LUN;
5001 sh->can_queue = h->nr_cmds - HPSA_NRESERVED_CMDS;
5002 sh->cmd_per_lun = sh->can_queue;
5003 sh->sg_tablesize = h->maxsgentries;
5004 sh->hostdata[0] = (unsigned long) h;
5005 sh->irq = h->intr[h->intr_mode];
5006 sh->unique_id = sh->irq;
5007 error = scsi_init_shared_tag_map(sh, sh->can_queue);
5008 if (error) {
5009 dev_err(&h->pdev->dev,
5010 "%s: scsi_init_shared_tag_map failed for controller %d\n",
5011 __func__, h->ctlr);
5012 scsi_host_put(sh);
5013 return error;
5014 }
5015 h->scsi_host = sh;
5016 return 0;
5017 }
5018
5019 static int hpsa_scsi_add_host(struct ctlr_info *h)
5020 {
5021 int rv;
5022
5023 rv = scsi_add_host(h->scsi_host, &h->pdev->dev);
5024 if (rv) {
5025 dev_err(&h->pdev->dev, "scsi_add_host failed\n");
5026 return rv;
5027 }
5028 scsi_scan_host(h->scsi_host);
5029 return 0;
5030 }
5031
5032 /*
5033 * The block layer has already gone to the trouble of picking out a unique,
5034 * small-integer tag for this request. We use an offset from that value as
5035 * an index to select our command block. (The offset allows us to reserve the
5036 * low-numbered entries for our own uses.)
5037 */
5038 static int hpsa_get_cmd_index(struct scsi_cmnd *scmd)
5039 {
5040 int idx = scmd->request->tag;
5041
5042 if (idx < 0)
5043 return idx;
5044
5045 /* Offset to leave space for internal cmds. */
5046 return idx += HPSA_NRESERVED_CMDS;
5047 }
5048
5049 /*
5050 * Send a TEST_UNIT_READY command to the specified LUN using the specified
5051 * reply queue; returns zero if the unit is ready, and non-zero otherwise.
5052 */
5053 static int hpsa_send_test_unit_ready(struct ctlr_info *h,
5054 struct CommandList *c, unsigned char lunaddr[],
5055 int reply_queue)
5056 {
5057 int rc;
5058
5059 /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
5060 (void) fill_cmd(c, TEST_UNIT_READY, h,
5061 NULL, 0, 0, lunaddr, TYPE_CMD);
5062 rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
5063 if (rc)
5064 return rc;
5065 /* no unmap needed here because no data xfer. */
5066
5067 /* Check if the unit is already ready. */
5068 if (c->err_info->CommandStatus == CMD_SUCCESS)
5069 return 0;
5070
5071 /*
5072 * The first command sent after reset will receive "unit attention" to
5073 * indicate that the LUN has been reset...this is actually what we're
5074 * looking for (but, success is good too).
5075 */
5076 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
5077 c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
5078 (c->err_info->SenseInfo[2] == NO_SENSE ||
5079 c->err_info->SenseInfo[2] == UNIT_ATTENTION))
5080 return 0;
5081
5082 return 1;
5083 }
5084
5085 /*
5086 * Wait for a TEST_UNIT_READY command to complete, retrying as necessary;
5087 * returns zero when the unit is ready, and non-zero when giving up.
5088 */
5089 static int hpsa_wait_for_test_unit_ready(struct ctlr_info *h,
5090 struct CommandList *c,
5091 unsigned char lunaddr[], int reply_queue)
5092 {
5093 int rc;
5094 int count = 0;
5095 int waittime = 1; /* seconds */
5096
5097 /* Send test unit ready until device ready, or give up. */
5098 for (count = 0; count < HPSA_TUR_RETRY_LIMIT; count++) {
5099
5100 /*
5101 * Wait for a bit. do this first, because if we send
5102 * the TUR right away, the reset will just abort it.
5103 */
5104 msleep(1000 * waittime);
5105
5106 rc = hpsa_send_test_unit_ready(h, c, lunaddr, reply_queue);
5107 if (!rc)
5108 break;
5109
5110 /* Increase wait time with each try, up to a point. */
5111 if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
5112 waittime *= 2;
5113
5114 dev_warn(&h->pdev->dev,
5115 "waiting %d secs for device to become ready.\n",
5116 waittime);
5117 }
5118
5119 return rc;
5120 }
5121
5122 static int wait_for_device_to_become_ready(struct ctlr_info *h,
5123 unsigned char lunaddr[],
5124 int reply_queue)
5125 {
5126 int first_queue;
5127 int last_queue;
5128 int rq;
5129 int rc = 0;
5130 struct CommandList *c;
5131
5132 c = cmd_alloc(h);
5133
5134 /*
5135 * If no specific reply queue was requested, then send the TUR
5136 * repeatedly, requesting a reply on each reply queue; otherwise execute
5137 * the loop exactly once using only the specified queue.
5138 */
5139 if (reply_queue == DEFAULT_REPLY_QUEUE) {
5140 first_queue = 0;
5141 last_queue = h->nreply_queues - 1;
5142 } else {
5143 first_queue = reply_queue;
5144 last_queue = reply_queue;
5145 }
5146
5147 for (rq = first_queue; rq <= last_queue; rq++) {
5148 rc = hpsa_wait_for_test_unit_ready(h, c, lunaddr, rq);
5149 if (rc)
5150 break;
5151 }
5152
5153 if (rc)
5154 dev_warn(&h->pdev->dev, "giving up on device.\n");
5155 else
5156 dev_warn(&h->pdev->dev, "device is ready.\n");
5157
5158 cmd_free(h, c);
5159 return rc;
5160 }
5161
5162 /* Need at least one of these error handlers to keep ../scsi/hosts.c from
5163 * complaining. Doing a host- or bus-reset can't do anything good here.
5164 */
5165 static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
5166 {
5167 int rc;
5168 struct ctlr_info *h;
5169 struct hpsa_scsi_dev_t *dev;
5170 char msg[48];
5171
5172 /* find the controller to which the command to be aborted was sent */
5173 h = sdev_to_hba(scsicmd->device);
5174 if (h == NULL) /* paranoia */
5175 return FAILED;
5176
5177 if (lockup_detected(h))
5178 return FAILED;
5179
5180 dev = scsicmd->device->hostdata;
5181 if (!dev) {
5182 dev_err(&h->pdev->dev, "%s: device lookup failed\n", __func__);
5183 return FAILED;
5184 }
5185
5186 /* if controller locked up, we can guarantee command won't complete */
5187 if (lockup_detected(h)) {
5188 snprintf(msg, sizeof(msg),
5189 "cmd %d RESET FAILED, lockup detected",
5190 hpsa_get_cmd_index(scsicmd));
5191 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
5192 return FAILED;
5193 }
5194
5195 /* this reset request might be the result of a lockup; check */
5196 if (detect_controller_lockup(h)) {
5197 snprintf(msg, sizeof(msg),
5198 "cmd %d RESET FAILED, new lockup detected",
5199 hpsa_get_cmd_index(scsicmd));
5200 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
5201 return FAILED;
5202 }
5203
5204 /* Do not attempt on controller */
5205 if (is_hba_lunid(dev->scsi3addr))
5206 return SUCCESS;
5207
5208 hpsa_show_dev_msg(KERN_WARNING, h, dev, "resetting");
5209
5210 /* send a reset to the SCSI LUN which the command was sent to */
5211 rc = hpsa_do_reset(h, dev, dev->scsi3addr, HPSA_RESET_TYPE_LUN,
5212 DEFAULT_REPLY_QUEUE);
5213 snprintf(msg, sizeof(msg), "reset %s",
5214 rc == 0 ? "completed successfully" : "failed");
5215 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
5216 return rc == 0 ? SUCCESS : FAILED;
5217 }
5218
5219 static void swizzle_abort_tag(u8 *tag)
5220 {
5221 u8 original_tag[8];
5222
5223 memcpy(original_tag, tag, 8);
5224 tag[0] = original_tag[3];
5225 tag[1] = original_tag[2];
5226 tag[2] = original_tag[1];
5227 tag[3] = original_tag[0];
5228 tag[4] = original_tag[7];
5229 tag[5] = original_tag[6];
5230 tag[6] = original_tag[5];
5231 tag[7] = original_tag[4];
5232 }
5233
5234 static void hpsa_get_tag(struct ctlr_info *h,
5235 struct CommandList *c, __le32 *taglower, __le32 *tagupper)
5236 {
5237 u64 tag;
5238 if (c->cmd_type == CMD_IOACCEL1) {
5239 struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *)
5240 &h->ioaccel_cmd_pool[c->cmdindex];
5241 tag = le64_to_cpu(cm1->tag);
5242 *tagupper = cpu_to_le32(tag >> 32);
5243 *taglower = cpu_to_le32(tag);
5244 return;
5245 }
5246 if (c->cmd_type == CMD_IOACCEL2) {
5247 struct io_accel2_cmd *cm2 = (struct io_accel2_cmd *)
5248 &h->ioaccel2_cmd_pool[c->cmdindex];
5249 /* upper tag not used in ioaccel2 mode */
5250 memset(tagupper, 0, sizeof(*tagupper));
5251 *taglower = cm2->Tag;
5252 return;
5253 }
5254 tag = le64_to_cpu(c->Header.tag);
5255 *tagupper = cpu_to_le32(tag >> 32);
5256 *taglower = cpu_to_le32(tag);
5257 }
5258
5259 static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr,
5260 struct CommandList *abort, int reply_queue)
5261 {
5262 int rc = IO_OK;
5263 struct CommandList *c;
5264 struct ErrorInfo *ei;
5265 __le32 tagupper, taglower;
5266
5267 c = cmd_alloc(h);
5268
5269 /* fill_cmd can't fail here, no buffer to map */
5270 (void) fill_cmd(c, HPSA_ABORT_MSG, h, &abort->Header.tag,
5271 0, 0, scsi3addr, TYPE_MSG);
5272 if (h->needs_abort_tags_swizzled)
5273 swizzle_abort_tag(&c->Request.CDB[4]);
5274 (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
5275 hpsa_get_tag(h, abort, &taglower, &tagupper);
5276 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd(abort) completed.\n",
5277 __func__, tagupper, taglower);
5278 /* no unmap needed here because no data xfer. */
5279
5280 ei = c->err_info;
5281 switch (ei->CommandStatus) {
5282 case CMD_SUCCESS:
5283 break;
5284 case CMD_TMF_STATUS:
5285 rc = hpsa_evaluate_tmf_status(h, c);
5286 break;
5287 case CMD_UNABORTABLE: /* Very common, don't make noise. */
5288 rc = -1;
5289 break;
5290 default:
5291 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n",
5292 __func__, tagupper, taglower);
5293 hpsa_scsi_interpret_error(h, c);
5294 rc = -1;
5295 break;
5296 }
5297 cmd_free(h, c);
5298 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n",
5299 __func__, tagupper, taglower);
5300 return rc;
5301 }
5302
5303 static void setup_ioaccel2_abort_cmd(struct CommandList *c, struct ctlr_info *h,
5304 struct CommandList *command_to_abort, int reply_queue)
5305 {
5306 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
5307 struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2;
5308 struct io_accel2_cmd *c2a =
5309 &h->ioaccel2_cmd_pool[command_to_abort->cmdindex];
5310 struct scsi_cmnd *scmd = command_to_abort->scsi_cmd;
5311 struct hpsa_scsi_dev_t *dev = scmd->device->hostdata;
5312
5313 /*
5314 * We're overlaying struct hpsa_tmf_struct on top of something which
5315 * was allocated as a struct io_accel2_cmd, so we better be sure it
5316 * actually fits, and doesn't overrun the error info space.
5317 */
5318 BUILD_BUG_ON(sizeof(struct hpsa_tmf_struct) >
5319 sizeof(struct io_accel2_cmd));
5320 BUG_ON(offsetof(struct io_accel2_cmd, error_data) <
5321 offsetof(struct hpsa_tmf_struct, error_len) +
5322 sizeof(ac->error_len));
5323
5324 c->cmd_type = IOACCEL2_TMF;
5325 c->scsi_cmd = SCSI_CMD_BUSY;
5326
5327 /* Adjust the DMA address to point to the accelerated command buffer */
5328 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
5329 (c->cmdindex * sizeof(struct io_accel2_cmd));
5330 BUG_ON(c->busaddr & 0x0000007F);
5331
5332 memset(ac, 0, sizeof(*c2)); /* yes this is correct */
5333 ac->iu_type = IOACCEL2_IU_TMF_TYPE;
5334 ac->reply_queue = reply_queue;
5335 ac->tmf = IOACCEL2_TMF_ABORT;
5336 ac->it_nexus = cpu_to_le32(dev->ioaccel_handle);
5337 memset(ac->lun_id, 0, sizeof(ac->lun_id));
5338 ac->tag = cpu_to_le64(c->cmdindex << DIRECT_LOOKUP_SHIFT);
5339 ac->abort_tag = cpu_to_le64(le32_to_cpu(c2a->Tag));
5340 ac->error_ptr = cpu_to_le64(c->busaddr +
5341 offsetof(struct io_accel2_cmd, error_data));
5342 ac->error_len = cpu_to_le32(sizeof(c2->error_data));
5343 }
5344
5345 /* ioaccel2 path firmware cannot handle abort task requests.
5346 * Change abort requests to physical target reset, and send to the
5347 * address of the physical disk used for the ioaccel 2 command.
5348 * Return 0 on success (IO_OK)
5349 * -1 on failure
5350 */
5351
5352 static int hpsa_send_reset_as_abort_ioaccel2(struct ctlr_info *h,
5353 unsigned char *scsi3addr, struct CommandList *abort, int reply_queue)
5354 {
5355 int rc = IO_OK;
5356 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
5357 struct hpsa_scsi_dev_t *dev; /* device to which scsi cmd was sent */
5358 unsigned char phys_scsi3addr[8]; /* addr of phys disk with volume */
5359 unsigned char *psa = &phys_scsi3addr[0];
5360
5361 /* Get a pointer to the hpsa logical device. */
5362 scmd = abort->scsi_cmd;
5363 dev = (struct hpsa_scsi_dev_t *)(scmd->device->hostdata);
5364 if (dev == NULL) {
5365 dev_warn(&h->pdev->dev,
5366 "Cannot abort: no device pointer for command.\n");
5367 return -1; /* not abortable */
5368 }
5369
5370 if (h->raid_offload_debug > 0)
5371 dev_info(&h->pdev->dev,
5372 "scsi %d:%d:%d:%d %s scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5373 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
5374 "Reset as abort",
5375 scsi3addr[0], scsi3addr[1], scsi3addr[2], scsi3addr[3],
5376 scsi3addr[4], scsi3addr[5], scsi3addr[6], scsi3addr[7]);
5377
5378 if (!dev->offload_enabled) {
5379 dev_warn(&h->pdev->dev,
5380 "Can't abort: device is not operating in HP SSD Smart Path mode.\n");
5381 return -1; /* not abortable */
5382 }
5383
5384 /* Incoming scsi3addr is logical addr. We need physical disk addr. */
5385 if (!hpsa_get_pdisk_of_ioaccel2(h, abort, psa)) {
5386 dev_warn(&h->pdev->dev, "Can't abort: Failed lookup of physical address.\n");
5387 return -1; /* not abortable */
5388 }
5389
5390 /* send the reset */
5391 if (h->raid_offload_debug > 0)
5392 dev_info(&h->pdev->dev,
5393 "Reset as abort: Resetting physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5394 psa[0], psa[1], psa[2], psa[3],
5395 psa[4], psa[5], psa[6], psa[7]);
5396 rc = hpsa_do_reset(h, dev, psa, HPSA_RESET_TYPE_TARGET, reply_queue);
5397 if (rc != 0) {
5398 dev_warn(&h->pdev->dev,
5399 "Reset as abort: Failed on physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5400 psa[0], psa[1], psa[2], psa[3],
5401 psa[4], psa[5], psa[6], psa[7]);
5402 return rc; /* failed to reset */
5403 }
5404
5405 /* wait for device to recover */
5406 if (wait_for_device_to_become_ready(h, psa, reply_queue) != 0) {
5407 dev_warn(&h->pdev->dev,
5408 "Reset as abort: Failed: Device never recovered from reset: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5409 psa[0], psa[1], psa[2], psa[3],
5410 psa[4], psa[5], psa[6], psa[7]);
5411 return -1; /* failed to recover */
5412 }
5413
5414 /* device recovered */
5415 dev_info(&h->pdev->dev,
5416 "Reset as abort: Device recovered from reset: scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5417 psa[0], psa[1], psa[2], psa[3],
5418 psa[4], psa[5], psa[6], psa[7]);
5419
5420 return rc; /* success */
5421 }
5422
5423 static int hpsa_send_abort_ioaccel2(struct ctlr_info *h,
5424 struct CommandList *abort, int reply_queue)
5425 {
5426 int rc = IO_OK;
5427 struct CommandList *c;
5428 __le32 taglower, tagupper;
5429 struct hpsa_scsi_dev_t *dev;
5430 struct io_accel2_cmd *c2;
5431
5432 dev = abort->scsi_cmd->device->hostdata;
5433 if (!dev->offload_enabled && !dev->hba_ioaccel_enabled)
5434 return -1;
5435
5436 c = cmd_alloc(h);
5437 setup_ioaccel2_abort_cmd(c, h, abort, reply_queue);
5438 c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
5439 (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
5440 hpsa_get_tag(h, abort, &taglower, &tagupper);
5441 dev_dbg(&h->pdev->dev,
5442 "%s: Tag:0x%08x:%08x: do_simple_cmd(ioaccel2 abort) completed.\n",
5443 __func__, tagupper, taglower);
5444 /* no unmap needed here because no data xfer. */
5445
5446 dev_dbg(&h->pdev->dev,
5447 "%s: Tag:0x%08x:%08x: abort service response = 0x%02x.\n",
5448 __func__, tagupper, taglower, c2->error_data.serv_response);
5449 switch (c2->error_data.serv_response) {
5450 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
5451 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
5452 rc = 0;
5453 break;
5454 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
5455 case IOACCEL2_SERV_RESPONSE_FAILURE:
5456 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
5457 rc = -1;
5458 break;
5459 default:
5460 dev_warn(&h->pdev->dev,
5461 "%s: Tag:0x%08x:%08x: unknown abort service response 0x%02x\n",
5462 __func__, tagupper, taglower,
5463 c2->error_data.serv_response);
5464 rc = -1;
5465 }
5466 cmd_free(h, c);
5467 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n", __func__,
5468 tagupper, taglower);
5469 return rc;
5470 }
5471
5472 static int hpsa_send_abort_both_ways(struct ctlr_info *h,
5473 unsigned char *scsi3addr, struct CommandList *abort, int reply_queue)
5474 {
5475 /*
5476 * ioccelerator mode 2 commands should be aborted via the
5477 * accelerated path, since RAID path is unaware of these commands,
5478 * but not all underlying firmware can handle abort TMF.
5479 * Change abort to physical device reset when abort TMF is unsupported.
5480 */
5481 if (abort->cmd_type == CMD_IOACCEL2) {
5482 if (HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags)
5483 return hpsa_send_abort_ioaccel2(h, abort,
5484 reply_queue);
5485 else
5486 return hpsa_send_reset_as_abort_ioaccel2(h, scsi3addr,
5487 abort, reply_queue);
5488 }
5489 return hpsa_send_abort(h, scsi3addr, abort, reply_queue);
5490 }
5491
5492 /* Find out which reply queue a command was meant to return on */
5493 static int hpsa_extract_reply_queue(struct ctlr_info *h,
5494 struct CommandList *c)
5495 {
5496 if (c->cmd_type == CMD_IOACCEL2)
5497 return h->ioaccel2_cmd_pool[c->cmdindex].reply_queue;
5498 return c->Header.ReplyQueue;
5499 }
5500
5501 /*
5502 * Limit concurrency of abort commands to prevent
5503 * over-subscription of commands
5504 */
5505 static inline int wait_for_available_abort_cmd(struct ctlr_info *h)
5506 {
5507 #define ABORT_CMD_WAIT_MSECS 5000
5508 return !wait_event_timeout(h->abort_cmd_wait_queue,
5509 atomic_dec_if_positive(&h->abort_cmds_available) >= 0,
5510 msecs_to_jiffies(ABORT_CMD_WAIT_MSECS));
5511 }
5512
5513 /* Send an abort for the specified command.
5514 * If the device and controller support it,
5515 * send a task abort request.
5516 */
5517 static int hpsa_eh_abort_handler(struct scsi_cmnd *sc)
5518 {
5519
5520 int rc;
5521 struct ctlr_info *h;
5522 struct hpsa_scsi_dev_t *dev;
5523 struct CommandList *abort; /* pointer to command to be aborted */
5524 struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */
5525 char msg[256]; /* For debug messaging. */
5526 int ml = 0;
5527 __le32 tagupper, taglower;
5528 int refcount, reply_queue;
5529
5530 if (sc == NULL)
5531 return FAILED;
5532
5533 if (sc->device == NULL)
5534 return FAILED;
5535
5536 /* Find the controller of the command to be aborted */
5537 h = sdev_to_hba(sc->device);
5538 if (h == NULL)
5539 return FAILED;
5540
5541 /* Find the device of the command to be aborted */
5542 dev = sc->device->hostdata;
5543 if (!dev) {
5544 dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n",
5545 msg);
5546 return FAILED;
5547 }
5548
5549 /* If controller locked up, we can guarantee command won't complete */
5550 if (lockup_detected(h)) {
5551 hpsa_show_dev_msg(KERN_WARNING, h, dev,
5552 "ABORT FAILED, lockup detected");
5553 return FAILED;
5554 }
5555
5556 /* This is a good time to check if controller lockup has occurred */
5557 if (detect_controller_lockup(h)) {
5558 hpsa_show_dev_msg(KERN_WARNING, h, dev,
5559 "ABORT FAILED, new lockup detected");
5560 return FAILED;
5561 }
5562
5563 /* Check that controller supports some kind of task abort */
5564 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) &&
5565 !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
5566 return FAILED;
5567
5568 memset(msg, 0, sizeof(msg));
5569 ml += sprintf(msg+ml, "scsi %d:%d:%d:%llu %s %p",
5570 h->scsi_host->host_no, sc->device->channel,
5571 sc->device->id, sc->device->lun,
5572 "Aborting command", sc);
5573
5574 /* Get SCSI command to be aborted */
5575 abort = (struct CommandList *) sc->host_scribble;
5576 if (abort == NULL) {
5577 /* This can happen if the command already completed. */
5578 return SUCCESS;
5579 }
5580 refcount = atomic_inc_return(&abort->refcount);
5581 if (refcount == 1) { /* Command is done already. */
5582 cmd_free(h, abort);
5583 return SUCCESS;
5584 }
5585
5586 /* Don't bother trying the abort if we know it won't work. */
5587 if (abort->cmd_type != CMD_IOACCEL2 &&
5588 abort->cmd_type != CMD_IOACCEL1 && !dev->supports_aborts) {
5589 cmd_free(h, abort);
5590 return FAILED;
5591 }
5592
5593 /*
5594 * Check that we're aborting the right command.
5595 * It's possible the CommandList already completed and got re-used.
5596 */
5597 if (abort->scsi_cmd != sc) {
5598 cmd_free(h, abort);
5599 return SUCCESS;
5600 }
5601
5602 abort->abort_pending = true;
5603 hpsa_get_tag(h, abort, &taglower, &tagupper);
5604 reply_queue = hpsa_extract_reply_queue(h, abort);
5605 ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower);
5606 as = abort->scsi_cmd;
5607 if (as != NULL)
5608 ml += sprintf(msg+ml,
5609 "CDBLen: %d CDB: 0x%02x%02x... SN: 0x%lx ",
5610 as->cmd_len, as->cmnd[0], as->cmnd[1],
5611 as->serial_number);
5612 dev_warn(&h->pdev->dev, "%s BEING SENT\n", msg);
5613 hpsa_show_dev_msg(KERN_WARNING, h, dev, "Aborting command");
5614
5615 /*
5616 * Command is in flight, or possibly already completed
5617 * by the firmware (but not to the scsi mid layer) but we can't
5618 * distinguish which. Send the abort down.
5619 */
5620 if (wait_for_available_abort_cmd(h)) {
5621 dev_warn(&h->pdev->dev,
5622 "%s FAILED, timeout waiting for an abort command to become available.\n",
5623 msg);
5624 cmd_free(h, abort);
5625 return FAILED;
5626 }
5627 rc = hpsa_send_abort_both_ways(h, dev->scsi3addr, abort, reply_queue);
5628 atomic_inc(&h->abort_cmds_available);
5629 wake_up_all(&h->abort_cmd_wait_queue);
5630 if (rc != 0) {
5631 dev_warn(&h->pdev->dev, "%s SENT, FAILED\n", msg);
5632 hpsa_show_dev_msg(KERN_WARNING, h, dev,
5633 "FAILED to abort command");
5634 cmd_free(h, abort);
5635 return FAILED;
5636 }
5637 dev_info(&h->pdev->dev, "%s SENT, SUCCESS\n", msg);
5638 wait_event(h->event_sync_wait_queue,
5639 abort->scsi_cmd != sc || lockup_detected(h));
5640 cmd_free(h, abort);
5641 return !lockup_detected(h) ? SUCCESS : FAILED;
5642 }
5643
5644 /*
5645 * For operations with an associated SCSI command, a command block is allocated
5646 * at init, and managed by cmd_tagged_alloc() and cmd_tagged_free() using the
5647 * block request tag as an index into a table of entries. cmd_tagged_free() is
5648 * the complement, although cmd_free() may be called instead.
5649 */
5650 static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h,
5651 struct scsi_cmnd *scmd)
5652 {
5653 int idx = hpsa_get_cmd_index(scmd);
5654 struct CommandList *c = h->cmd_pool + idx;
5655
5656 if (idx < HPSA_NRESERVED_CMDS || idx >= h->nr_cmds) {
5657 dev_err(&h->pdev->dev, "Bad block tag: %d not in [%d..%d]\n",
5658 idx, HPSA_NRESERVED_CMDS, h->nr_cmds - 1);
5659 /* The index value comes from the block layer, so if it's out of
5660 * bounds, it's probably not our bug.
5661 */
5662 BUG();
5663 }
5664
5665 atomic_inc(&c->refcount);
5666 if (unlikely(!hpsa_is_cmd_idle(c))) {
5667 /*
5668 * We expect that the SCSI layer will hand us a unique tag
5669 * value. Thus, there should never be a collision here between
5670 * two requests...because if the selected command isn't idle
5671 * then someone is going to be very disappointed.
5672 */
5673 dev_err(&h->pdev->dev,
5674 "tag collision (tag=%d) in cmd_tagged_alloc().\n",
5675 idx);
5676 if (c->scsi_cmd != NULL)
5677 scsi_print_command(c->scsi_cmd);
5678 scsi_print_command(scmd);
5679 }
5680
5681 hpsa_cmd_partial_init(h, idx, c);
5682 return c;
5683 }
5684
5685 static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c)
5686 {
5687 /*
5688 * Release our reference to the block. We don't need to do anything
5689 * else to free it, because it is accessed by index. (There's no point
5690 * in checking the result of the decrement, since we cannot guarantee
5691 * that there isn't a concurrent abort which is also accessing it.)
5692 */
5693 (void)atomic_dec(&c->refcount);
5694 }
5695
5696 /*
5697 * For operations that cannot sleep, a command block is allocated at init,
5698 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
5699 * which ones are free or in use. Lock must be held when calling this.
5700 * cmd_free() is the complement.
5701 * This function never gives up and returns NULL. If it hangs,
5702 * another thread must call cmd_free() to free some tags.
5703 */
5704
5705 static struct CommandList *cmd_alloc(struct ctlr_info *h)
5706 {
5707 struct CommandList *c;
5708 int refcount, i;
5709 int offset = 0;
5710
5711 /*
5712 * There is some *extremely* small but non-zero chance that that
5713 * multiple threads could get in here, and one thread could
5714 * be scanning through the list of bits looking for a free
5715 * one, but the free ones are always behind him, and other
5716 * threads sneak in behind him and eat them before he can
5717 * get to them, so that while there is always a free one, a
5718 * very unlucky thread might be starved anyway, never able to
5719 * beat the other threads. In reality, this happens so
5720 * infrequently as to be indistinguishable from never.
5721 *
5722 * Note that we start allocating commands before the SCSI host structure
5723 * is initialized. Since the search starts at bit zero, this
5724 * all works, since we have at least one command structure available;
5725 * however, it means that the structures with the low indexes have to be
5726 * reserved for driver-initiated requests, while requests from the block
5727 * layer will use the higher indexes.
5728 */
5729
5730 for (;;) {
5731 i = find_next_zero_bit(h->cmd_pool_bits,
5732 HPSA_NRESERVED_CMDS,
5733 offset);
5734 if (unlikely(i >= HPSA_NRESERVED_CMDS)) {
5735 offset = 0;
5736 continue;
5737 }
5738 c = h->cmd_pool + i;
5739 refcount = atomic_inc_return(&c->refcount);
5740 if (unlikely(refcount > 1)) {
5741 cmd_free(h, c); /* already in use */
5742 offset = (i + 1) % HPSA_NRESERVED_CMDS;
5743 continue;
5744 }
5745 set_bit(i & (BITS_PER_LONG - 1),
5746 h->cmd_pool_bits + (i / BITS_PER_LONG));
5747 break; /* it's ours now. */
5748 }
5749 hpsa_cmd_partial_init(h, i, c);
5750 return c;
5751 }
5752
5753 /*
5754 * This is the complementary operation to cmd_alloc(). Note, however, in some
5755 * corner cases it may also be used to free blocks allocated by
5756 * cmd_tagged_alloc() in which case the ref-count decrement does the trick and
5757 * the clear-bit is harmless.
5758 */
5759 static void cmd_free(struct ctlr_info *h, struct CommandList *c)
5760 {
5761 if (atomic_dec_and_test(&c->refcount)) {
5762 int i;
5763
5764 i = c - h->cmd_pool;
5765 clear_bit(i & (BITS_PER_LONG - 1),
5766 h->cmd_pool_bits + (i / BITS_PER_LONG));
5767 }
5768 }
5769
5770 #ifdef CONFIG_COMPAT
5771
5772 static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd,
5773 void __user *arg)
5774 {
5775 IOCTL32_Command_struct __user *arg32 =
5776 (IOCTL32_Command_struct __user *) arg;
5777 IOCTL_Command_struct arg64;
5778 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
5779 int err;
5780 u32 cp;
5781
5782 memset(&arg64, 0, sizeof(arg64));
5783 err = 0;
5784 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
5785 sizeof(arg64.LUN_info));
5786 err |= copy_from_user(&arg64.Request, &arg32->Request,
5787 sizeof(arg64.Request));
5788 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
5789 sizeof(arg64.error_info));
5790 err |= get_user(arg64.buf_size, &arg32->buf_size);
5791 err |= get_user(cp, &arg32->buf);
5792 arg64.buf = compat_ptr(cp);
5793 err |= copy_to_user(p, &arg64, sizeof(arg64));
5794
5795 if (err)
5796 return -EFAULT;
5797
5798 err = hpsa_ioctl(dev, CCISS_PASSTHRU, p);
5799 if (err)
5800 return err;
5801 err |= copy_in_user(&arg32->error_info, &p->error_info,
5802 sizeof(arg32->error_info));
5803 if (err)
5804 return -EFAULT;
5805 return err;
5806 }
5807
5808 static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
5809 int cmd, void __user *arg)
5810 {
5811 BIG_IOCTL32_Command_struct __user *arg32 =
5812 (BIG_IOCTL32_Command_struct __user *) arg;
5813 BIG_IOCTL_Command_struct arg64;
5814 BIG_IOCTL_Command_struct __user *p =
5815 compat_alloc_user_space(sizeof(arg64));
5816 int err;
5817 u32 cp;
5818
5819 memset(&arg64, 0, sizeof(arg64));
5820 err = 0;
5821 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
5822 sizeof(arg64.LUN_info));
5823 err |= copy_from_user(&arg64.Request, &arg32->Request,
5824 sizeof(arg64.Request));
5825 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
5826 sizeof(arg64.error_info));
5827 err |= get_user(arg64.buf_size, &arg32->buf_size);
5828 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
5829 err |= get_user(cp, &arg32->buf);
5830 arg64.buf = compat_ptr(cp);
5831 err |= copy_to_user(p, &arg64, sizeof(arg64));
5832
5833 if (err)
5834 return -EFAULT;
5835
5836 err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, p);
5837 if (err)
5838 return err;
5839 err |= copy_in_user(&arg32->error_info, &p->error_info,
5840 sizeof(arg32->error_info));
5841 if (err)
5842 return -EFAULT;
5843 return err;
5844 }
5845
5846 static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
5847 {
5848 switch (cmd) {
5849 case CCISS_GETPCIINFO:
5850 case CCISS_GETINTINFO:
5851 case CCISS_SETINTINFO:
5852 case CCISS_GETNODENAME:
5853 case CCISS_SETNODENAME:
5854 case CCISS_GETHEARTBEAT:
5855 case CCISS_GETBUSTYPES:
5856 case CCISS_GETFIRMVER:
5857 case CCISS_GETDRIVVER:
5858 case CCISS_REVALIDVOLS:
5859 case CCISS_DEREGDISK:
5860 case CCISS_REGNEWDISK:
5861 case CCISS_REGNEWD:
5862 case CCISS_RESCANDISK:
5863 case CCISS_GETLUNINFO:
5864 return hpsa_ioctl(dev, cmd, arg);
5865
5866 case CCISS_PASSTHRU32:
5867 return hpsa_ioctl32_passthru(dev, cmd, arg);
5868 case CCISS_BIG_PASSTHRU32:
5869 return hpsa_ioctl32_big_passthru(dev, cmd, arg);
5870
5871 default:
5872 return -ENOIOCTLCMD;
5873 }
5874 }
5875 #endif
5876
5877 static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
5878 {
5879 struct hpsa_pci_info pciinfo;
5880
5881 if (!argp)
5882 return -EINVAL;
5883 pciinfo.domain = pci_domain_nr(h->pdev->bus);
5884 pciinfo.bus = h->pdev->bus->number;
5885 pciinfo.dev_fn = h->pdev->devfn;
5886 pciinfo.board_id = h->board_id;
5887 if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
5888 return -EFAULT;
5889 return 0;
5890 }
5891
5892 static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
5893 {
5894 DriverVer_type DriverVer;
5895 unsigned char vmaj, vmin, vsubmin;
5896 int rc;
5897
5898 rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
5899 &vmaj, &vmin, &vsubmin);
5900 if (rc != 3) {
5901 dev_info(&h->pdev->dev, "driver version string '%s' "
5902 "unrecognized.", HPSA_DRIVER_VERSION);
5903 vmaj = 0;
5904 vmin = 0;
5905 vsubmin = 0;
5906 }
5907 DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
5908 if (!argp)
5909 return -EINVAL;
5910 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
5911 return -EFAULT;
5912 return 0;
5913 }
5914
5915 static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
5916 {
5917 IOCTL_Command_struct iocommand;
5918 struct CommandList *c;
5919 char *buff = NULL;
5920 u64 temp64;
5921 int rc = 0;
5922
5923 if (!argp)
5924 return -EINVAL;
5925 if (!capable(CAP_SYS_RAWIO))
5926 return -EPERM;
5927 if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
5928 return -EFAULT;
5929 if ((iocommand.buf_size < 1) &&
5930 (iocommand.Request.Type.Direction != XFER_NONE)) {
5931 return -EINVAL;
5932 }
5933 if (iocommand.buf_size > 0) {
5934 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
5935 if (buff == NULL)
5936 return -ENOMEM;
5937 if (iocommand.Request.Type.Direction & XFER_WRITE) {
5938 /* Copy the data into the buffer we created */
5939 if (copy_from_user(buff, iocommand.buf,
5940 iocommand.buf_size)) {
5941 rc = -EFAULT;
5942 goto out_kfree;
5943 }
5944 } else {
5945 memset(buff, 0, iocommand.buf_size);
5946 }
5947 }
5948 c = cmd_alloc(h);
5949
5950 /* Fill in the command type */
5951 c->cmd_type = CMD_IOCTL_PEND;
5952 c->scsi_cmd = SCSI_CMD_BUSY;
5953 /* Fill in Command Header */
5954 c->Header.ReplyQueue = 0; /* unused in simple mode */
5955 if (iocommand.buf_size > 0) { /* buffer to fill */
5956 c->Header.SGList = 1;
5957 c->Header.SGTotal = cpu_to_le16(1);
5958 } else { /* no buffers to fill */
5959 c->Header.SGList = 0;
5960 c->Header.SGTotal = cpu_to_le16(0);
5961 }
5962 memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
5963
5964 /* Fill in Request block */
5965 memcpy(&c->Request, &iocommand.Request,
5966 sizeof(c->Request));
5967
5968 /* Fill in the scatter gather information */
5969 if (iocommand.buf_size > 0) {
5970 temp64 = pci_map_single(h->pdev, buff,
5971 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
5972 if (dma_mapping_error(&h->pdev->dev, (dma_addr_t) temp64)) {
5973 c->SG[0].Addr = cpu_to_le64(0);
5974 c->SG[0].Len = cpu_to_le32(0);
5975 rc = -ENOMEM;
5976 goto out;
5977 }
5978 c->SG[0].Addr = cpu_to_le64(temp64);
5979 c->SG[0].Len = cpu_to_le32(iocommand.buf_size);
5980 c->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* not chaining */
5981 }
5982 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
5983 if (iocommand.buf_size > 0)
5984 hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
5985 check_ioctl_unit_attention(h, c);
5986 if (rc) {
5987 rc = -EIO;
5988 goto out;
5989 }
5990
5991 /* Copy the error information out */
5992 memcpy(&iocommand.error_info, c->err_info,
5993 sizeof(iocommand.error_info));
5994 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
5995 rc = -EFAULT;
5996 goto out;
5997 }
5998 if ((iocommand.Request.Type.Direction & XFER_READ) &&
5999 iocommand.buf_size > 0) {
6000 /* Copy the data out of the buffer we created */
6001 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
6002 rc = -EFAULT;
6003 goto out;
6004 }
6005 }
6006 out:
6007 cmd_free(h, c);
6008 out_kfree:
6009 kfree(buff);
6010 return rc;
6011 }
6012
6013 static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
6014 {
6015 BIG_IOCTL_Command_struct *ioc;
6016 struct CommandList *c;
6017 unsigned char **buff = NULL;
6018 int *buff_size = NULL;
6019 u64 temp64;
6020 BYTE sg_used = 0;
6021 int status = 0;
6022 u32 left;
6023 u32 sz;
6024 BYTE __user *data_ptr;
6025
6026 if (!argp)
6027 return -EINVAL;
6028 if (!capable(CAP_SYS_RAWIO))
6029 return -EPERM;
6030 ioc = (BIG_IOCTL_Command_struct *)
6031 kmalloc(sizeof(*ioc), GFP_KERNEL);
6032 if (!ioc) {
6033 status = -ENOMEM;
6034 goto cleanup1;
6035 }
6036 if (copy_from_user(ioc, argp, sizeof(*ioc))) {
6037 status = -EFAULT;
6038 goto cleanup1;
6039 }
6040 if ((ioc->buf_size < 1) &&
6041 (ioc->Request.Type.Direction != XFER_NONE)) {
6042 status = -EINVAL;
6043 goto cleanup1;
6044 }
6045 /* Check kmalloc limits using all SGs */
6046 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
6047 status = -EINVAL;
6048 goto cleanup1;
6049 }
6050 if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) {
6051 status = -EINVAL;
6052 goto cleanup1;
6053 }
6054 buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL);
6055 if (!buff) {
6056 status = -ENOMEM;
6057 goto cleanup1;
6058 }
6059 buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL);
6060 if (!buff_size) {
6061 status = -ENOMEM;
6062 goto cleanup1;
6063 }
6064 left = ioc->buf_size;
6065 data_ptr = ioc->buf;
6066 while (left) {
6067 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
6068 buff_size[sg_used] = sz;
6069 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
6070 if (buff[sg_used] == NULL) {
6071 status = -ENOMEM;
6072 goto cleanup1;
6073 }
6074 if (ioc->Request.Type.Direction & XFER_WRITE) {
6075 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
6076 status = -EFAULT;
6077 goto cleanup1;
6078 }
6079 } else
6080 memset(buff[sg_used], 0, sz);
6081 left -= sz;
6082 data_ptr += sz;
6083 sg_used++;
6084 }
6085 c = cmd_alloc(h);
6086
6087 c->cmd_type = CMD_IOCTL_PEND;
6088 c->scsi_cmd = SCSI_CMD_BUSY;
6089 c->Header.ReplyQueue = 0;
6090 c->Header.SGList = (u8) sg_used;
6091 c->Header.SGTotal = cpu_to_le16(sg_used);
6092 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
6093 memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
6094 if (ioc->buf_size > 0) {
6095 int i;
6096 for (i = 0; i < sg_used; i++) {
6097 temp64 = pci_map_single(h->pdev, buff[i],
6098 buff_size[i], PCI_DMA_BIDIRECTIONAL);
6099 if (dma_mapping_error(&h->pdev->dev,
6100 (dma_addr_t) temp64)) {
6101 c->SG[i].Addr = cpu_to_le64(0);
6102 c->SG[i].Len = cpu_to_le32(0);
6103 hpsa_pci_unmap(h->pdev, c, i,
6104 PCI_DMA_BIDIRECTIONAL);
6105 status = -ENOMEM;
6106 goto cleanup0;
6107 }
6108 c->SG[i].Addr = cpu_to_le64(temp64);
6109 c->SG[i].Len = cpu_to_le32(buff_size[i]);
6110 c->SG[i].Ext = cpu_to_le32(0);
6111 }
6112 c->SG[--i].Ext = cpu_to_le32(HPSA_SG_LAST);
6113 }
6114 status = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
6115 if (sg_used)
6116 hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
6117 check_ioctl_unit_attention(h, c);
6118 if (status) {
6119 status = -EIO;
6120 goto cleanup0;
6121 }
6122
6123 /* Copy the error information out */
6124 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
6125 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
6126 status = -EFAULT;
6127 goto cleanup0;
6128 }
6129 if ((ioc->Request.Type.Direction & XFER_READ) && ioc->buf_size > 0) {
6130 int i;
6131
6132 /* Copy the data out of the buffer we created */
6133 BYTE __user *ptr = ioc->buf;
6134 for (i = 0; i < sg_used; i++) {
6135 if (copy_to_user(ptr, buff[i], buff_size[i])) {
6136 status = -EFAULT;
6137 goto cleanup0;
6138 }
6139 ptr += buff_size[i];
6140 }
6141 }
6142 status = 0;
6143 cleanup0:
6144 cmd_free(h, c);
6145 cleanup1:
6146 if (buff) {
6147 int i;
6148
6149 for (i = 0; i < sg_used; i++)
6150 kfree(buff[i]);
6151 kfree(buff);
6152 }
6153 kfree(buff_size);
6154 kfree(ioc);
6155 return status;
6156 }
6157
6158 static void check_ioctl_unit_attention(struct ctlr_info *h,
6159 struct CommandList *c)
6160 {
6161 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
6162 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
6163 (void) check_for_unit_attention(h, c);
6164 }
6165
6166 /*
6167 * ioctl
6168 */
6169 static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
6170 {
6171 struct ctlr_info *h;
6172 void __user *argp = (void __user *)arg;
6173 int rc;
6174
6175 h = sdev_to_hba(dev);
6176
6177 switch (cmd) {
6178 case CCISS_DEREGDISK:
6179 case CCISS_REGNEWDISK:
6180 case CCISS_REGNEWD:
6181 hpsa_scan_start(h->scsi_host);
6182 return 0;
6183 case CCISS_GETPCIINFO:
6184 return hpsa_getpciinfo_ioctl(h, argp);
6185 case CCISS_GETDRIVVER:
6186 return hpsa_getdrivver_ioctl(h, argp);
6187 case CCISS_PASSTHRU:
6188 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
6189 return -EAGAIN;
6190 rc = hpsa_passthru_ioctl(h, argp);
6191 atomic_inc(&h->passthru_cmds_avail);
6192 return rc;
6193 case CCISS_BIG_PASSTHRU:
6194 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
6195 return -EAGAIN;
6196 rc = hpsa_big_passthru_ioctl(h, argp);
6197 atomic_inc(&h->passthru_cmds_avail);
6198 return rc;
6199 default:
6200 return -ENOTTY;
6201 }
6202 }
6203
6204 static void hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr,
6205 u8 reset_type)
6206 {
6207 struct CommandList *c;
6208
6209 c = cmd_alloc(h);
6210
6211 /* fill_cmd can't fail here, no data buffer to map */
6212 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
6213 RAID_CTLR_LUNID, TYPE_MSG);
6214 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
6215 c->waiting = NULL;
6216 enqueue_cmd_and_start_io(h, c);
6217 /* Don't wait for completion, the reset won't complete. Don't free
6218 * the command either. This is the last command we will send before
6219 * re-initializing everything, so it doesn't matter and won't leak.
6220 */
6221 return;
6222 }
6223
6224 static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
6225 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
6226 int cmd_type)
6227 {
6228 int pci_dir = XFER_NONE;
6229 u64 tag; /* for commands to be aborted */
6230
6231 c->cmd_type = CMD_IOCTL_PEND;
6232 c->scsi_cmd = SCSI_CMD_BUSY;
6233 c->Header.ReplyQueue = 0;
6234 if (buff != NULL && size > 0) {
6235 c->Header.SGList = 1;
6236 c->Header.SGTotal = cpu_to_le16(1);
6237 } else {
6238 c->Header.SGList = 0;
6239 c->Header.SGTotal = cpu_to_le16(0);
6240 }
6241 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
6242
6243 if (cmd_type == TYPE_CMD) {
6244 switch (cmd) {
6245 case HPSA_INQUIRY:
6246 /* are we trying to read a vital product page */
6247 if (page_code & VPD_PAGE) {
6248 c->Request.CDB[1] = 0x01;
6249 c->Request.CDB[2] = (page_code & 0xff);
6250 }
6251 c->Request.CDBLen = 6;
6252 c->Request.type_attr_dir =
6253 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6254 c->Request.Timeout = 0;
6255 c->Request.CDB[0] = HPSA_INQUIRY;
6256 c->Request.CDB[4] = size & 0xFF;
6257 break;
6258 case HPSA_REPORT_LOG:
6259 case HPSA_REPORT_PHYS:
6260 /* Talking to controller so It's a physical command
6261 mode = 00 target = 0. Nothing to write.
6262 */
6263 c->Request.CDBLen = 12;
6264 c->Request.type_attr_dir =
6265 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6266 c->Request.Timeout = 0;
6267 c->Request.CDB[0] = cmd;
6268 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
6269 c->Request.CDB[7] = (size >> 16) & 0xFF;
6270 c->Request.CDB[8] = (size >> 8) & 0xFF;
6271 c->Request.CDB[9] = size & 0xFF;
6272 break;
6273 case HPSA_CACHE_FLUSH:
6274 c->Request.CDBLen = 12;
6275 c->Request.type_attr_dir =
6276 TYPE_ATTR_DIR(cmd_type,
6277 ATTR_SIMPLE, XFER_WRITE);
6278 c->Request.Timeout = 0;
6279 c->Request.CDB[0] = BMIC_WRITE;
6280 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
6281 c->Request.CDB[7] = (size >> 8) & 0xFF;
6282 c->Request.CDB[8] = size & 0xFF;
6283 break;
6284 case TEST_UNIT_READY:
6285 c->Request.CDBLen = 6;
6286 c->Request.type_attr_dir =
6287 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
6288 c->Request.Timeout = 0;
6289 break;
6290 case HPSA_GET_RAID_MAP:
6291 c->Request.CDBLen = 12;
6292 c->Request.type_attr_dir =
6293 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6294 c->Request.Timeout = 0;
6295 c->Request.CDB[0] = HPSA_CISS_READ;
6296 c->Request.CDB[1] = cmd;
6297 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
6298 c->Request.CDB[7] = (size >> 16) & 0xFF;
6299 c->Request.CDB[8] = (size >> 8) & 0xFF;
6300 c->Request.CDB[9] = size & 0xFF;
6301 break;
6302 case BMIC_SENSE_CONTROLLER_PARAMETERS:
6303 c->Request.CDBLen = 10;
6304 c->Request.type_attr_dir =
6305 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6306 c->Request.Timeout = 0;
6307 c->Request.CDB[0] = BMIC_READ;
6308 c->Request.CDB[6] = BMIC_SENSE_CONTROLLER_PARAMETERS;
6309 c->Request.CDB[7] = (size >> 16) & 0xFF;
6310 c->Request.CDB[8] = (size >> 8) & 0xFF;
6311 break;
6312 case BMIC_IDENTIFY_PHYSICAL_DEVICE:
6313 c->Request.CDBLen = 10;
6314 c->Request.type_attr_dir =
6315 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6316 c->Request.Timeout = 0;
6317 c->Request.CDB[0] = BMIC_READ;
6318 c->Request.CDB[6] = BMIC_IDENTIFY_PHYSICAL_DEVICE;
6319 c->Request.CDB[7] = (size >> 16) & 0xFF;
6320 c->Request.CDB[8] = (size >> 8) & 0XFF;
6321 break;
6322 default:
6323 dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
6324 BUG();
6325 return -1;
6326 }
6327 } else if (cmd_type == TYPE_MSG) {
6328 switch (cmd) {
6329
6330 case HPSA_DEVICE_RESET_MSG:
6331 c->Request.CDBLen = 16;
6332 c->Request.type_attr_dir =
6333 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
6334 c->Request.Timeout = 0; /* Don't time out */
6335 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
6336 c->Request.CDB[0] = cmd;
6337 c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
6338 /* If bytes 4-7 are zero, it means reset the */
6339 /* LunID device */
6340 c->Request.CDB[4] = 0x00;
6341 c->Request.CDB[5] = 0x00;
6342 c->Request.CDB[6] = 0x00;
6343 c->Request.CDB[7] = 0x00;
6344 break;
6345 case HPSA_ABORT_MSG:
6346 memcpy(&tag, buff, sizeof(tag));
6347 dev_dbg(&h->pdev->dev,
6348 "Abort Tag:0x%016llx using rqst Tag:0x%016llx",
6349 tag, c->Header.tag);
6350 c->Request.CDBLen = 16;
6351 c->Request.type_attr_dir =
6352 TYPE_ATTR_DIR(cmd_type,
6353 ATTR_SIMPLE, XFER_WRITE);
6354 c->Request.Timeout = 0; /* Don't time out */
6355 c->Request.CDB[0] = HPSA_TASK_MANAGEMENT;
6356 c->Request.CDB[1] = HPSA_TMF_ABORT_TASK;
6357 c->Request.CDB[2] = 0x00; /* reserved */
6358 c->Request.CDB[3] = 0x00; /* reserved */
6359 /* Tag to abort goes in CDB[4]-CDB[11] */
6360 memcpy(&c->Request.CDB[4], &tag, sizeof(tag));
6361 c->Request.CDB[12] = 0x00; /* reserved */
6362 c->Request.CDB[13] = 0x00; /* reserved */
6363 c->Request.CDB[14] = 0x00; /* reserved */
6364 c->Request.CDB[15] = 0x00; /* reserved */
6365 break;
6366 default:
6367 dev_warn(&h->pdev->dev, "unknown message type %d\n",
6368 cmd);
6369 BUG();
6370 }
6371 } else {
6372 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
6373 BUG();
6374 }
6375
6376 switch (GET_DIR(c->Request.type_attr_dir)) {
6377 case XFER_READ:
6378 pci_dir = PCI_DMA_FROMDEVICE;
6379 break;
6380 case XFER_WRITE:
6381 pci_dir = PCI_DMA_TODEVICE;
6382 break;
6383 case XFER_NONE:
6384 pci_dir = PCI_DMA_NONE;
6385 break;
6386 default:
6387 pci_dir = PCI_DMA_BIDIRECTIONAL;
6388 }
6389 if (hpsa_map_one(h->pdev, c, buff, size, pci_dir))
6390 return -1;
6391 return 0;
6392 }
6393
6394 /*
6395 * Map (physical) PCI mem into (virtual) kernel space
6396 */
6397 static void __iomem *remap_pci_mem(ulong base, ulong size)
6398 {
6399 ulong page_base = ((ulong) base) & PAGE_MASK;
6400 ulong page_offs = ((ulong) base) - page_base;
6401 void __iomem *page_remapped = ioremap_nocache(page_base,
6402 page_offs + size);
6403
6404 return page_remapped ? (page_remapped + page_offs) : NULL;
6405 }
6406
6407 static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
6408 {
6409 return h->access.command_completed(h, q);
6410 }
6411
6412 static inline bool interrupt_pending(struct ctlr_info *h)
6413 {
6414 return h->access.intr_pending(h);
6415 }
6416
6417 static inline long interrupt_not_for_us(struct ctlr_info *h)
6418 {
6419 return (h->access.intr_pending(h) == 0) ||
6420 (h->interrupts_enabled == 0);
6421 }
6422
6423 static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
6424 u32 raw_tag)
6425 {
6426 if (unlikely(tag_index >= h->nr_cmds)) {
6427 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
6428 return 1;
6429 }
6430 return 0;
6431 }
6432
6433 static inline void finish_cmd(struct CommandList *c)
6434 {
6435 dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
6436 if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI
6437 || c->cmd_type == CMD_IOACCEL2))
6438 complete_scsi_command(c);
6439 else if (c->cmd_type == CMD_IOCTL_PEND || c->cmd_type == IOACCEL2_TMF)
6440 complete(c->waiting);
6441 }
6442
6443
6444 static inline u32 hpsa_tag_discard_error_bits(struct ctlr_info *h, u32 tag)
6445 {
6446 #define HPSA_PERF_ERROR_BITS ((1 << DIRECT_LOOKUP_SHIFT) - 1)
6447 #define HPSA_SIMPLE_ERROR_BITS 0x03
6448 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
6449 return tag & ~HPSA_SIMPLE_ERROR_BITS;
6450 return tag & ~HPSA_PERF_ERROR_BITS;
6451 }
6452
6453 /* process completion of an indexed ("direct lookup") command */
6454 static inline void process_indexed_cmd(struct ctlr_info *h,
6455 u32 raw_tag)
6456 {
6457 u32 tag_index;
6458 struct CommandList *c;
6459
6460 tag_index = raw_tag >> DIRECT_LOOKUP_SHIFT;
6461 if (!bad_tag(h, tag_index, raw_tag)) {
6462 c = h->cmd_pool + tag_index;
6463 finish_cmd(c);
6464 }
6465 }
6466
6467 /* Some controllers, like p400, will give us one interrupt
6468 * after a soft reset, even if we turned interrupts off.
6469 * Only need to check for this in the hpsa_xxx_discard_completions
6470 * functions.
6471 */
6472 static int ignore_bogus_interrupt(struct ctlr_info *h)
6473 {
6474 if (likely(!reset_devices))
6475 return 0;
6476
6477 if (likely(h->interrupts_enabled))
6478 return 0;
6479
6480 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
6481 "(known firmware bug.) Ignoring.\n");
6482
6483 return 1;
6484 }
6485
6486 /*
6487 * Convert &h->q[x] (passed to interrupt handlers) back to h.
6488 * Relies on (h-q[x] == x) being true for x such that
6489 * 0 <= x < MAX_REPLY_QUEUES.
6490 */
6491 static struct ctlr_info *queue_to_hba(u8 *queue)
6492 {
6493 return container_of((queue - *queue), struct ctlr_info, q[0]);
6494 }
6495
6496 static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
6497 {
6498 struct ctlr_info *h = queue_to_hba(queue);
6499 u8 q = *(u8 *) queue;
6500 u32 raw_tag;
6501
6502 if (ignore_bogus_interrupt(h))
6503 return IRQ_NONE;
6504
6505 if (interrupt_not_for_us(h))
6506 return IRQ_NONE;
6507 h->last_intr_timestamp = get_jiffies_64();
6508 while (interrupt_pending(h)) {
6509 raw_tag = get_next_completion(h, q);
6510 while (raw_tag != FIFO_EMPTY)
6511 raw_tag = next_command(h, q);
6512 }
6513 return IRQ_HANDLED;
6514 }
6515
6516 static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
6517 {
6518 struct ctlr_info *h = queue_to_hba(queue);
6519 u32 raw_tag;
6520 u8 q = *(u8 *) queue;
6521
6522 if (ignore_bogus_interrupt(h))
6523 return IRQ_NONE;
6524
6525 h->last_intr_timestamp = get_jiffies_64();
6526 raw_tag = get_next_completion(h, q);
6527 while (raw_tag != FIFO_EMPTY)
6528 raw_tag = next_command(h, q);
6529 return IRQ_HANDLED;
6530 }
6531
6532 static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
6533 {
6534 struct ctlr_info *h = queue_to_hba((u8 *) queue);
6535 u32 raw_tag;
6536 u8 q = *(u8 *) queue;
6537
6538 if (interrupt_not_for_us(h))
6539 return IRQ_NONE;
6540 h->last_intr_timestamp = get_jiffies_64();
6541 while (interrupt_pending(h)) {
6542 raw_tag = get_next_completion(h, q);
6543 while (raw_tag != FIFO_EMPTY) {
6544 process_indexed_cmd(h, raw_tag);
6545 raw_tag = next_command(h, q);
6546 }
6547 }
6548 return IRQ_HANDLED;
6549 }
6550
6551 static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
6552 {
6553 struct ctlr_info *h = queue_to_hba(queue);
6554 u32 raw_tag;
6555 u8 q = *(u8 *) queue;
6556
6557 h->last_intr_timestamp = get_jiffies_64();
6558 raw_tag = get_next_completion(h, q);
6559 while (raw_tag != FIFO_EMPTY) {
6560 process_indexed_cmd(h, raw_tag);
6561 raw_tag = next_command(h, q);
6562 }
6563 return IRQ_HANDLED;
6564 }
6565
6566 /* Send a message CDB to the firmware. Careful, this only works
6567 * in simple mode, not performant mode due to the tag lookup.
6568 * We only ever use this immediately after a controller reset.
6569 */
6570 static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
6571 unsigned char type)
6572 {
6573 struct Command {
6574 struct CommandListHeader CommandHeader;
6575 struct RequestBlock Request;
6576 struct ErrDescriptor ErrorDescriptor;
6577 };
6578 struct Command *cmd;
6579 static const size_t cmd_sz = sizeof(*cmd) +
6580 sizeof(cmd->ErrorDescriptor);
6581 dma_addr_t paddr64;
6582 __le32 paddr32;
6583 u32 tag;
6584 void __iomem *vaddr;
6585 int i, err;
6586
6587 vaddr = pci_ioremap_bar(pdev, 0);
6588 if (vaddr == NULL)
6589 return -ENOMEM;
6590
6591 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
6592 * CCISS commands, so they must be allocated from the lower 4GiB of
6593 * memory.
6594 */
6595 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
6596 if (err) {
6597 iounmap(vaddr);
6598 return err;
6599 }
6600
6601 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
6602 if (cmd == NULL) {
6603 iounmap(vaddr);
6604 return -ENOMEM;
6605 }
6606
6607 /* This must fit, because of the 32-bit consistent DMA mask. Also,
6608 * although there's no guarantee, we assume that the address is at
6609 * least 4-byte aligned (most likely, it's page-aligned).
6610 */
6611 paddr32 = cpu_to_le32(paddr64);
6612
6613 cmd->CommandHeader.ReplyQueue = 0;
6614 cmd->CommandHeader.SGList = 0;
6615 cmd->CommandHeader.SGTotal = cpu_to_le16(0);
6616 cmd->CommandHeader.tag = cpu_to_le64(paddr64);
6617 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
6618
6619 cmd->Request.CDBLen = 16;
6620 cmd->Request.type_attr_dir =
6621 TYPE_ATTR_DIR(TYPE_MSG, ATTR_HEADOFQUEUE, XFER_NONE);
6622 cmd->Request.Timeout = 0; /* Don't time out */
6623 cmd->Request.CDB[0] = opcode;
6624 cmd->Request.CDB[1] = type;
6625 memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
6626 cmd->ErrorDescriptor.Addr =
6627 cpu_to_le64((le32_to_cpu(paddr32) + sizeof(*cmd)));
6628 cmd->ErrorDescriptor.Len = cpu_to_le32(sizeof(struct ErrorInfo));
6629
6630 writel(le32_to_cpu(paddr32), vaddr + SA5_REQUEST_PORT_OFFSET);
6631
6632 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
6633 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
6634 if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr64)
6635 break;
6636 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
6637 }
6638
6639 iounmap(vaddr);
6640
6641 /* we leak the DMA buffer here ... no choice since the controller could
6642 * still complete the command.
6643 */
6644 if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
6645 dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
6646 opcode, type);
6647 return -ETIMEDOUT;
6648 }
6649
6650 pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
6651
6652 if (tag & HPSA_ERROR_BIT) {
6653 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
6654 opcode, type);
6655 return -EIO;
6656 }
6657
6658 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
6659 opcode, type);
6660 return 0;
6661 }
6662
6663 #define hpsa_noop(p) hpsa_message(p, 3, 0)
6664
6665 static int hpsa_controller_hard_reset(struct pci_dev *pdev,
6666 void __iomem *vaddr, u32 use_doorbell)
6667 {
6668
6669 if (use_doorbell) {
6670 /* For everything after the P600, the PCI power state method
6671 * of resetting the controller doesn't work, so we have this
6672 * other way using the doorbell register.
6673 */
6674 dev_info(&pdev->dev, "using doorbell to reset controller\n");
6675 writel(use_doorbell, vaddr + SA5_DOORBELL);
6676
6677 /* PMC hardware guys tell us we need a 10 second delay after
6678 * doorbell reset and before any attempt to talk to the board
6679 * at all to ensure that this actually works and doesn't fall
6680 * over in some weird corner cases.
6681 */
6682 msleep(10000);
6683 } else { /* Try to do it the PCI power state way */
6684
6685 /* Quoting from the Open CISS Specification: "The Power
6686 * Management Control/Status Register (CSR) controls the power
6687 * state of the device. The normal operating state is D0,
6688 * CSR=00h. The software off state is D3, CSR=03h. To reset
6689 * the controller, place the interface device in D3 then to D0,
6690 * this causes a secondary PCI reset which will reset the
6691 * controller." */
6692
6693 int rc = 0;
6694
6695 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
6696
6697 /* enter the D3hot power management state */
6698 rc = pci_set_power_state(pdev, PCI_D3hot);
6699 if (rc)
6700 return rc;
6701
6702 msleep(500);
6703
6704 /* enter the D0 power management state */
6705 rc = pci_set_power_state(pdev, PCI_D0);
6706 if (rc)
6707 return rc;
6708
6709 /*
6710 * The P600 requires a small delay when changing states.
6711 * Otherwise we may think the board did not reset and we bail.
6712 * This for kdump only and is particular to the P600.
6713 */
6714 msleep(500);
6715 }
6716 return 0;
6717 }
6718
6719 static void init_driver_version(char *driver_version, int len)
6720 {
6721 memset(driver_version, 0, len);
6722 strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
6723 }
6724
6725 static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
6726 {
6727 char *driver_version;
6728 int i, size = sizeof(cfgtable->driver_version);
6729
6730 driver_version = kmalloc(size, GFP_KERNEL);
6731 if (!driver_version)
6732 return -ENOMEM;
6733
6734 init_driver_version(driver_version, size);
6735 for (i = 0; i < size; i++)
6736 writeb(driver_version[i], &cfgtable->driver_version[i]);
6737 kfree(driver_version);
6738 return 0;
6739 }
6740
6741 static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
6742 unsigned char *driver_ver)
6743 {
6744 int i;
6745
6746 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
6747 driver_ver[i] = readb(&cfgtable->driver_version[i]);
6748 }
6749
6750 static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
6751 {
6752
6753 char *driver_ver, *old_driver_ver;
6754 int rc, size = sizeof(cfgtable->driver_version);
6755
6756 old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
6757 if (!old_driver_ver)
6758 return -ENOMEM;
6759 driver_ver = old_driver_ver + size;
6760
6761 /* After a reset, the 32 bytes of "driver version" in the cfgtable
6762 * should have been changed, otherwise we know the reset failed.
6763 */
6764 init_driver_version(old_driver_ver, size);
6765 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
6766 rc = !memcmp(driver_ver, old_driver_ver, size);
6767 kfree(old_driver_ver);
6768 return rc;
6769 }
6770 /* This does a hard reset of the controller using PCI power management
6771 * states or the using the doorbell register.
6772 */
6773 static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev, u32 board_id)
6774 {
6775 u64 cfg_offset;
6776 u32 cfg_base_addr;
6777 u64 cfg_base_addr_index;
6778 void __iomem *vaddr;
6779 unsigned long paddr;
6780 u32 misc_fw_support;
6781 int rc;
6782 struct CfgTable __iomem *cfgtable;
6783 u32 use_doorbell;
6784 u16 command_register;
6785
6786 /* For controllers as old as the P600, this is very nearly
6787 * the same thing as
6788 *
6789 * pci_save_state(pci_dev);
6790 * pci_set_power_state(pci_dev, PCI_D3hot);
6791 * pci_set_power_state(pci_dev, PCI_D0);
6792 * pci_restore_state(pci_dev);
6793 *
6794 * For controllers newer than the P600, the pci power state
6795 * method of resetting doesn't work so we have another way
6796 * using the doorbell register.
6797 */
6798
6799 if (!ctlr_is_resettable(board_id)) {
6800 dev_warn(&pdev->dev, "Controller not resettable\n");
6801 return -ENODEV;
6802 }
6803
6804 /* if controller is soft- but not hard resettable... */
6805 if (!ctlr_is_hard_resettable(board_id))
6806 return -ENOTSUPP; /* try soft reset later. */
6807
6808 /* Save the PCI command register */
6809 pci_read_config_word(pdev, 4, &command_register);
6810 pci_save_state(pdev);
6811
6812 /* find the first memory BAR, so we can find the cfg table */
6813 rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
6814 if (rc)
6815 return rc;
6816 vaddr = remap_pci_mem(paddr, 0x250);
6817 if (!vaddr)
6818 return -ENOMEM;
6819
6820 /* find cfgtable in order to check if reset via doorbell is supported */
6821 rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
6822 &cfg_base_addr_index, &cfg_offset);
6823 if (rc)
6824 goto unmap_vaddr;
6825 cfgtable = remap_pci_mem(pci_resource_start(pdev,
6826 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
6827 if (!cfgtable) {
6828 rc = -ENOMEM;
6829 goto unmap_vaddr;
6830 }
6831 rc = write_driver_ver_to_cfgtable(cfgtable);
6832 if (rc)
6833 goto unmap_cfgtable;
6834
6835 /* If reset via doorbell register is supported, use that.
6836 * There are two such methods. Favor the newest method.
6837 */
6838 misc_fw_support = readl(&cfgtable->misc_fw_support);
6839 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
6840 if (use_doorbell) {
6841 use_doorbell = DOORBELL_CTLR_RESET2;
6842 } else {
6843 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
6844 if (use_doorbell) {
6845 dev_warn(&pdev->dev,
6846 "Soft reset not supported. Firmware update is required.\n");
6847 rc = -ENOTSUPP; /* try soft reset */
6848 goto unmap_cfgtable;
6849 }
6850 }
6851
6852 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
6853 if (rc)
6854 goto unmap_cfgtable;
6855
6856 pci_restore_state(pdev);
6857 pci_write_config_word(pdev, 4, command_register);
6858
6859 /* Some devices (notably the HP Smart Array 5i Controller)
6860 need a little pause here */
6861 msleep(HPSA_POST_RESET_PAUSE_MSECS);
6862
6863 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
6864 if (rc) {
6865 dev_warn(&pdev->dev,
6866 "Failed waiting for board to become ready after hard reset\n");
6867 goto unmap_cfgtable;
6868 }
6869
6870 rc = controller_reset_failed(vaddr);
6871 if (rc < 0)
6872 goto unmap_cfgtable;
6873 if (rc) {
6874 dev_warn(&pdev->dev, "Unable to successfully reset "
6875 "controller. Will try soft reset.\n");
6876 rc = -ENOTSUPP;
6877 } else {
6878 dev_info(&pdev->dev, "board ready after hard reset.\n");
6879 }
6880
6881 unmap_cfgtable:
6882 iounmap(cfgtable);
6883
6884 unmap_vaddr:
6885 iounmap(vaddr);
6886 return rc;
6887 }
6888
6889 /*
6890 * We cannot read the structure directly, for portability we must use
6891 * the io functions.
6892 * This is for debug only.
6893 */
6894 static void print_cfg_table(struct device *dev, struct CfgTable __iomem *tb)
6895 {
6896 #ifdef HPSA_DEBUG
6897 int i;
6898 char temp_name[17];
6899
6900 dev_info(dev, "Controller Configuration information\n");
6901 dev_info(dev, "------------------------------------\n");
6902 for (i = 0; i < 4; i++)
6903 temp_name[i] = readb(&(tb->Signature[i]));
6904 temp_name[4] = '\0';
6905 dev_info(dev, " Signature = %s\n", temp_name);
6906 dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
6907 dev_info(dev, " Transport methods supported = 0x%x\n",
6908 readl(&(tb->TransportSupport)));
6909 dev_info(dev, " Transport methods active = 0x%x\n",
6910 readl(&(tb->TransportActive)));
6911 dev_info(dev, " Requested transport Method = 0x%x\n",
6912 readl(&(tb->HostWrite.TransportRequest)));
6913 dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
6914 readl(&(tb->HostWrite.CoalIntDelay)));
6915 dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
6916 readl(&(tb->HostWrite.CoalIntCount)));
6917 dev_info(dev, " Max outstanding commands = %d\n",
6918 readl(&(tb->CmdsOutMax)));
6919 dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
6920 for (i = 0; i < 16; i++)
6921 temp_name[i] = readb(&(tb->ServerName[i]));
6922 temp_name[16] = '\0';
6923 dev_info(dev, " Server Name = %s\n", temp_name);
6924 dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
6925 readl(&(tb->HeartBeat)));
6926 #endif /* HPSA_DEBUG */
6927 }
6928
6929 static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
6930 {
6931 int i, offset, mem_type, bar_type;
6932
6933 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
6934 return 0;
6935 offset = 0;
6936 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
6937 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
6938 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
6939 offset += 4;
6940 else {
6941 mem_type = pci_resource_flags(pdev, i) &
6942 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
6943 switch (mem_type) {
6944 case PCI_BASE_ADDRESS_MEM_TYPE_32:
6945 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
6946 offset += 4; /* 32 bit */
6947 break;
6948 case PCI_BASE_ADDRESS_MEM_TYPE_64:
6949 offset += 8;
6950 break;
6951 default: /* reserved in PCI 2.2 */
6952 dev_warn(&pdev->dev,
6953 "base address is invalid\n");
6954 return -1;
6955 break;
6956 }
6957 }
6958 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
6959 return i + 1;
6960 }
6961 return -1;
6962 }
6963
6964 static void hpsa_disable_interrupt_mode(struct ctlr_info *h)
6965 {
6966 if (h->msix_vector) {
6967 if (h->pdev->msix_enabled)
6968 pci_disable_msix(h->pdev);
6969 h->msix_vector = 0;
6970 } else if (h->msi_vector) {
6971 if (h->pdev->msi_enabled)
6972 pci_disable_msi(h->pdev);
6973 h->msi_vector = 0;
6974 }
6975 }
6976
6977 /* If MSI/MSI-X is supported by the kernel we will try to enable it on
6978 * controllers that are capable. If not, we use legacy INTx mode.
6979 */
6980 static void hpsa_interrupt_mode(struct ctlr_info *h)
6981 {
6982 #ifdef CONFIG_PCI_MSI
6983 int err, i;
6984 struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
6985
6986 for (i = 0; i < MAX_REPLY_QUEUES; i++) {
6987 hpsa_msix_entries[i].vector = 0;
6988 hpsa_msix_entries[i].entry = i;
6989 }
6990
6991 /* Some boards advertise MSI but don't really support it */
6992 if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
6993 (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
6994 goto default_int_mode;
6995 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
6996 dev_info(&h->pdev->dev, "MSI-X capable controller\n");
6997 h->msix_vector = MAX_REPLY_QUEUES;
6998 if (h->msix_vector > num_online_cpus())
6999 h->msix_vector = num_online_cpus();
7000 err = pci_enable_msix_range(h->pdev, hpsa_msix_entries,
7001 1, h->msix_vector);
7002 if (err < 0) {
7003 dev_warn(&h->pdev->dev, "MSI-X init failed %d\n", err);
7004 h->msix_vector = 0;
7005 goto single_msi_mode;
7006 } else if (err < h->msix_vector) {
7007 dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
7008 "available\n", err);
7009 }
7010 h->msix_vector = err;
7011 for (i = 0; i < h->msix_vector; i++)
7012 h->intr[i] = hpsa_msix_entries[i].vector;
7013 return;
7014 }
7015 single_msi_mode:
7016 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
7017 dev_info(&h->pdev->dev, "MSI capable controller\n");
7018 if (!pci_enable_msi(h->pdev))
7019 h->msi_vector = 1;
7020 else
7021 dev_warn(&h->pdev->dev, "MSI init failed\n");
7022 }
7023 default_int_mode:
7024 #endif /* CONFIG_PCI_MSI */
7025 /* if we get here we're going to use the default interrupt mode */
7026 h->intr[h->intr_mode] = h->pdev->irq;
7027 }
7028
7029 static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
7030 {
7031 int i;
7032 u32 subsystem_vendor_id, subsystem_device_id;
7033
7034 subsystem_vendor_id = pdev->subsystem_vendor;
7035 subsystem_device_id = pdev->subsystem_device;
7036 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
7037 subsystem_vendor_id;
7038
7039 for (i = 0; i < ARRAY_SIZE(products); i++)
7040 if (*board_id == products[i].board_id)
7041 return i;
7042
7043 if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
7044 subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
7045 !hpsa_allow_any) {
7046 dev_warn(&pdev->dev, "unrecognized board ID: "
7047 "0x%08x, ignoring.\n", *board_id);
7048 return -ENODEV;
7049 }
7050 return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
7051 }
7052
7053 static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
7054 unsigned long *memory_bar)
7055 {
7056 int i;
7057
7058 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
7059 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
7060 /* addressing mode bits already removed */
7061 *memory_bar = pci_resource_start(pdev, i);
7062 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
7063 *memory_bar);
7064 return 0;
7065 }
7066 dev_warn(&pdev->dev, "no memory BAR found\n");
7067 return -ENODEV;
7068 }
7069
7070 static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
7071 int wait_for_ready)
7072 {
7073 int i, iterations;
7074 u32 scratchpad;
7075 if (wait_for_ready)
7076 iterations = HPSA_BOARD_READY_ITERATIONS;
7077 else
7078 iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
7079
7080 for (i = 0; i < iterations; i++) {
7081 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
7082 if (wait_for_ready) {
7083 if (scratchpad == HPSA_FIRMWARE_READY)
7084 return 0;
7085 } else {
7086 if (scratchpad != HPSA_FIRMWARE_READY)
7087 return 0;
7088 }
7089 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
7090 }
7091 dev_warn(&pdev->dev, "board not ready, timed out.\n");
7092 return -ENODEV;
7093 }
7094
7095 static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
7096 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
7097 u64 *cfg_offset)
7098 {
7099 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
7100 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
7101 *cfg_base_addr &= (u32) 0x0000ffff;
7102 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
7103 if (*cfg_base_addr_index == -1) {
7104 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
7105 return -ENODEV;
7106 }
7107 return 0;
7108 }
7109
7110 static void hpsa_free_cfgtables(struct ctlr_info *h)
7111 {
7112 if (h->transtable) {
7113 iounmap(h->transtable);
7114 h->transtable = NULL;
7115 }
7116 if (h->cfgtable) {
7117 iounmap(h->cfgtable);
7118 h->cfgtable = NULL;
7119 }
7120 }
7121
7122 /* Find and map CISS config table and transfer table
7123 + * several items must be unmapped (freed) later
7124 + * */
7125 static int hpsa_find_cfgtables(struct ctlr_info *h)
7126 {
7127 u64 cfg_offset;
7128 u32 cfg_base_addr;
7129 u64 cfg_base_addr_index;
7130 u32 trans_offset;
7131 int rc;
7132
7133 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
7134 &cfg_base_addr_index, &cfg_offset);
7135 if (rc)
7136 return rc;
7137 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
7138 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
7139 if (!h->cfgtable) {
7140 dev_err(&h->pdev->dev, "Failed mapping cfgtable\n");
7141 return -ENOMEM;
7142 }
7143 rc = write_driver_ver_to_cfgtable(h->cfgtable);
7144 if (rc)
7145 return rc;
7146 /* Find performant mode table. */
7147 trans_offset = readl(&h->cfgtable->TransMethodOffset);
7148 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
7149 cfg_base_addr_index)+cfg_offset+trans_offset,
7150 sizeof(*h->transtable));
7151 if (!h->transtable) {
7152 dev_err(&h->pdev->dev, "Failed mapping transfer table\n");
7153 hpsa_free_cfgtables(h);
7154 return -ENOMEM;
7155 }
7156 return 0;
7157 }
7158
7159 static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
7160 {
7161 #define MIN_MAX_COMMANDS 16
7162 BUILD_BUG_ON(MIN_MAX_COMMANDS <= HPSA_NRESERVED_CMDS);
7163
7164 h->max_commands = readl(&h->cfgtable->MaxPerformantModeCommands);
7165
7166 /* Limit commands in memory limited kdump scenario. */
7167 if (reset_devices && h->max_commands > 32)
7168 h->max_commands = 32;
7169
7170 if (h->max_commands < MIN_MAX_COMMANDS) {
7171 dev_warn(&h->pdev->dev,
7172 "Controller reports max supported commands of %d Using %d instead. Ensure that firmware is up to date.\n",
7173 h->max_commands,
7174 MIN_MAX_COMMANDS);
7175 h->max_commands = MIN_MAX_COMMANDS;
7176 }
7177 }
7178
7179 /* If the controller reports that the total max sg entries is greater than 512,
7180 * then we know that chained SG blocks work. (Original smart arrays did not
7181 * support chained SG blocks and would return zero for max sg entries.)
7182 */
7183 static int hpsa_supports_chained_sg_blocks(struct ctlr_info *h)
7184 {
7185 return h->maxsgentries > 512;
7186 }
7187
7188 /* Interrogate the hardware for some limits:
7189 * max commands, max SG elements without chaining, and with chaining,
7190 * SG chain block size, etc.
7191 */
7192 static void hpsa_find_board_params(struct ctlr_info *h)
7193 {
7194 hpsa_get_max_perf_mode_cmds(h);
7195 h->nr_cmds = h->max_commands;
7196 h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
7197 h->fw_support = readl(&(h->cfgtable->misc_fw_support));
7198 if (hpsa_supports_chained_sg_blocks(h)) {
7199 /* Limit in-command s/g elements to 32 save dma'able memory. */
7200 h->max_cmd_sg_entries = 32;
7201 h->chainsize = h->maxsgentries - h->max_cmd_sg_entries;
7202 h->maxsgentries--; /* save one for chain pointer */
7203 } else {
7204 /*
7205 * Original smart arrays supported at most 31 s/g entries
7206 * embedded inline in the command (trying to use more
7207 * would lock up the controller)
7208 */
7209 h->max_cmd_sg_entries = 31;
7210 h->maxsgentries = 31; /* default to traditional values */
7211 h->chainsize = 0;
7212 }
7213
7214 /* Find out what task management functions are supported and cache */
7215 h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
7216 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags))
7217 dev_warn(&h->pdev->dev, "Physical aborts not supported\n");
7218 if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
7219 dev_warn(&h->pdev->dev, "Logical aborts not supported\n");
7220 if (!(HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags))
7221 dev_warn(&h->pdev->dev, "HP SSD Smart Path aborts not supported\n");
7222 }
7223
7224 static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
7225 {
7226 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
7227 dev_err(&h->pdev->dev, "not a valid CISS config table\n");
7228 return false;
7229 }
7230 return true;
7231 }
7232
7233 static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
7234 {
7235 u32 driver_support;
7236
7237 driver_support = readl(&(h->cfgtable->driver_support));
7238 /* Need to enable prefetch in the SCSI core for 6400 in x86 */
7239 #ifdef CONFIG_X86
7240 driver_support |= ENABLE_SCSI_PREFETCH;
7241 #endif
7242 driver_support |= ENABLE_UNIT_ATTN;
7243 writel(driver_support, &(h->cfgtable->driver_support));
7244 }
7245
7246 /* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
7247 * in a prefetch beyond physical memory.
7248 */
7249 static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
7250 {
7251 u32 dma_prefetch;
7252
7253 if (h->board_id != 0x3225103C)
7254 return;
7255 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
7256 dma_prefetch |= 0x8000;
7257 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
7258 }
7259
7260 static int hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h)
7261 {
7262 int i;
7263 u32 doorbell_value;
7264 unsigned long flags;
7265 /* wait until the clear_event_notify bit 6 is cleared by controller. */
7266 for (i = 0; i < MAX_CLEAR_EVENT_WAIT; i++) {
7267 spin_lock_irqsave(&h->lock, flags);
7268 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
7269 spin_unlock_irqrestore(&h->lock, flags);
7270 if (!(doorbell_value & DOORBELL_CLEAR_EVENTS))
7271 goto done;
7272 /* delay and try again */
7273 msleep(CLEAR_EVENT_WAIT_INTERVAL);
7274 }
7275 return -ENODEV;
7276 done:
7277 return 0;
7278 }
7279
7280 static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
7281 {
7282 int i;
7283 u32 doorbell_value;
7284 unsigned long flags;
7285
7286 /* under certain very rare conditions, this can take awhile.
7287 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
7288 * as we enter this code.)
7289 */
7290 for (i = 0; i < MAX_MODE_CHANGE_WAIT; i++) {
7291 if (h->remove_in_progress)
7292 goto done;
7293 spin_lock_irqsave(&h->lock, flags);
7294 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
7295 spin_unlock_irqrestore(&h->lock, flags);
7296 if (!(doorbell_value & CFGTBL_ChangeReq))
7297 goto done;
7298 /* delay and try again */
7299 msleep(MODE_CHANGE_WAIT_INTERVAL);
7300 }
7301 return -ENODEV;
7302 done:
7303 return 0;
7304 }
7305
7306 /* return -ENODEV or other reason on error, 0 on success */
7307 static int hpsa_enter_simple_mode(struct ctlr_info *h)
7308 {
7309 u32 trans_support;
7310
7311 trans_support = readl(&(h->cfgtable->TransportSupport));
7312 if (!(trans_support & SIMPLE_MODE))
7313 return -ENOTSUPP;
7314
7315 h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
7316
7317 /* Update the field, and then ring the doorbell */
7318 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
7319 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
7320 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
7321 if (hpsa_wait_for_mode_change_ack(h))
7322 goto error;
7323 print_cfg_table(&h->pdev->dev, h->cfgtable);
7324 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
7325 goto error;
7326 h->transMethod = CFGTBL_Trans_Simple;
7327 return 0;
7328 error:
7329 dev_err(&h->pdev->dev, "failed to enter simple mode\n");
7330 return -ENODEV;
7331 }
7332
7333 /* free items allocated or mapped by hpsa_pci_init */
7334 static void hpsa_free_pci_init(struct ctlr_info *h)
7335 {
7336 hpsa_free_cfgtables(h); /* pci_init 4 */
7337 iounmap(h->vaddr); /* pci_init 3 */
7338 h->vaddr = NULL;
7339 hpsa_disable_interrupt_mode(h); /* pci_init 2 */
7340 /*
7341 * call pci_disable_device before pci_release_regions per
7342 * Documentation/PCI/pci.txt
7343 */
7344 pci_disable_device(h->pdev); /* pci_init 1 */
7345 pci_release_regions(h->pdev); /* pci_init 2 */
7346 }
7347
7348 /* several items must be freed later */
7349 static int hpsa_pci_init(struct ctlr_info *h)
7350 {
7351 int prod_index, err;
7352
7353 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
7354 if (prod_index < 0)
7355 return prod_index;
7356 h->product_name = products[prod_index].product_name;
7357 h->access = *(products[prod_index].access);
7358
7359 h->needs_abort_tags_swizzled =
7360 ctlr_needs_abort_tags_swizzled(h->board_id);
7361
7362 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
7363 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
7364
7365 err = pci_enable_device(h->pdev);
7366 if (err) {
7367 dev_err(&h->pdev->dev, "failed to enable PCI device\n");
7368 pci_disable_device(h->pdev);
7369 return err;
7370 }
7371
7372 err = pci_request_regions(h->pdev, HPSA);
7373 if (err) {
7374 dev_err(&h->pdev->dev,
7375 "failed to obtain PCI resources\n");
7376 pci_disable_device(h->pdev);
7377 return err;
7378 }
7379
7380 pci_set_master(h->pdev);
7381
7382 hpsa_interrupt_mode(h);
7383 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
7384 if (err)
7385 goto clean2; /* intmode+region, pci */
7386 h->vaddr = remap_pci_mem(h->paddr, 0x250);
7387 if (!h->vaddr) {
7388 dev_err(&h->pdev->dev, "failed to remap PCI mem\n");
7389 err = -ENOMEM;
7390 goto clean2; /* intmode+region, pci */
7391 }
7392 err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
7393 if (err)
7394 goto clean3; /* vaddr, intmode+region, pci */
7395 err = hpsa_find_cfgtables(h);
7396 if (err)
7397 goto clean3; /* vaddr, intmode+region, pci */
7398 hpsa_find_board_params(h);
7399
7400 if (!hpsa_CISS_signature_present(h)) {
7401 err = -ENODEV;
7402 goto clean4; /* cfgtables, vaddr, intmode+region, pci */
7403 }
7404 hpsa_set_driver_support_bits(h);
7405 hpsa_p600_dma_prefetch_quirk(h);
7406 err = hpsa_enter_simple_mode(h);
7407 if (err)
7408 goto clean4; /* cfgtables, vaddr, intmode+region, pci */
7409 return 0;
7410
7411 clean4: /* cfgtables, vaddr, intmode+region, pci */
7412 hpsa_free_cfgtables(h);
7413 clean3: /* vaddr, intmode+region, pci */
7414 iounmap(h->vaddr);
7415 h->vaddr = NULL;
7416 clean2: /* intmode+region, pci */
7417 hpsa_disable_interrupt_mode(h);
7418 /*
7419 * call pci_disable_device before pci_release_regions per
7420 * Documentation/PCI/pci.txt
7421 */
7422 pci_disable_device(h->pdev);
7423 pci_release_regions(h->pdev);
7424 return err;
7425 }
7426
7427 static void hpsa_hba_inquiry(struct ctlr_info *h)
7428 {
7429 int rc;
7430
7431 #define HBA_INQUIRY_BYTE_COUNT 64
7432 h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
7433 if (!h->hba_inquiry_data)
7434 return;
7435 rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
7436 h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
7437 if (rc != 0) {
7438 kfree(h->hba_inquiry_data);
7439 h->hba_inquiry_data = NULL;
7440 }
7441 }
7442
7443 static int hpsa_init_reset_devices(struct pci_dev *pdev, u32 board_id)
7444 {
7445 int rc, i;
7446 void __iomem *vaddr;
7447
7448 if (!reset_devices)
7449 return 0;
7450
7451 /* kdump kernel is loading, we don't know in which state is
7452 * the pci interface. The dev->enable_cnt is equal zero
7453 * so we call enable+disable, wait a while and switch it on.
7454 */
7455 rc = pci_enable_device(pdev);
7456 if (rc) {
7457 dev_warn(&pdev->dev, "Failed to enable PCI device\n");
7458 return -ENODEV;
7459 }
7460 pci_disable_device(pdev);
7461 msleep(260); /* a randomly chosen number */
7462 rc = pci_enable_device(pdev);
7463 if (rc) {
7464 dev_warn(&pdev->dev, "failed to enable device.\n");
7465 return -ENODEV;
7466 }
7467
7468 pci_set_master(pdev);
7469
7470 vaddr = pci_ioremap_bar(pdev, 0);
7471 if (vaddr == NULL) {
7472 rc = -ENOMEM;
7473 goto out_disable;
7474 }
7475 writel(SA5_INTR_OFF, vaddr + SA5_REPLY_INTR_MASK_OFFSET);
7476 iounmap(vaddr);
7477
7478 /* Reset the controller with a PCI power-cycle or via doorbell */
7479 rc = hpsa_kdump_hard_reset_controller(pdev, board_id);
7480
7481 /* -ENOTSUPP here means we cannot reset the controller
7482 * but it's already (and still) up and running in
7483 * "performant mode". Or, it might be 640x, which can't reset
7484 * due to concerns about shared bbwc between 6402/6404 pair.
7485 */
7486 if (rc)
7487 goto out_disable;
7488
7489 /* Now try to get the controller to respond to a no-op */
7490 dev_info(&pdev->dev, "Waiting for controller to respond to no-op\n");
7491 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
7492 if (hpsa_noop(pdev) == 0)
7493 break;
7494 else
7495 dev_warn(&pdev->dev, "no-op failed%s\n",
7496 (i < 11 ? "; re-trying" : ""));
7497 }
7498
7499 out_disable:
7500
7501 pci_disable_device(pdev);
7502 return rc;
7503 }
7504
7505 static void hpsa_free_cmd_pool(struct ctlr_info *h)
7506 {
7507 kfree(h->cmd_pool_bits);
7508 h->cmd_pool_bits = NULL;
7509 if (h->cmd_pool) {
7510 pci_free_consistent(h->pdev,
7511 h->nr_cmds * sizeof(struct CommandList),
7512 h->cmd_pool,
7513 h->cmd_pool_dhandle);
7514 h->cmd_pool = NULL;
7515 h->cmd_pool_dhandle = 0;
7516 }
7517 if (h->errinfo_pool) {
7518 pci_free_consistent(h->pdev,
7519 h->nr_cmds * sizeof(struct ErrorInfo),
7520 h->errinfo_pool,
7521 h->errinfo_pool_dhandle);
7522 h->errinfo_pool = NULL;
7523 h->errinfo_pool_dhandle = 0;
7524 }
7525 }
7526
7527 static int hpsa_alloc_cmd_pool(struct ctlr_info *h)
7528 {
7529 h->cmd_pool_bits = kzalloc(
7530 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
7531 sizeof(unsigned long), GFP_KERNEL);
7532 h->cmd_pool = pci_alloc_consistent(h->pdev,
7533 h->nr_cmds * sizeof(*h->cmd_pool),
7534 &(h->cmd_pool_dhandle));
7535 h->errinfo_pool = pci_alloc_consistent(h->pdev,
7536 h->nr_cmds * sizeof(*h->errinfo_pool),
7537 &(h->errinfo_pool_dhandle));
7538 if ((h->cmd_pool_bits == NULL)
7539 || (h->cmd_pool == NULL)
7540 || (h->errinfo_pool == NULL)) {
7541 dev_err(&h->pdev->dev, "out of memory in %s", __func__);
7542 goto clean_up;
7543 }
7544 hpsa_preinitialize_commands(h);
7545 return 0;
7546 clean_up:
7547 hpsa_free_cmd_pool(h);
7548 return -ENOMEM;
7549 }
7550
7551 static void hpsa_irq_affinity_hints(struct ctlr_info *h)
7552 {
7553 int i, cpu;
7554
7555 cpu = cpumask_first(cpu_online_mask);
7556 for (i = 0; i < h->msix_vector; i++) {
7557 irq_set_affinity_hint(h->intr[i], get_cpu_mask(cpu));
7558 cpu = cpumask_next(cpu, cpu_online_mask);
7559 }
7560 }
7561
7562 /* clear affinity hints and free MSI-X, MSI, or legacy INTx vectors */
7563 static void hpsa_free_irqs(struct ctlr_info *h)
7564 {
7565 int i;
7566
7567 if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
7568 /* Single reply queue, only one irq to free */
7569 i = h->intr_mode;
7570 irq_set_affinity_hint(h->intr[i], NULL);
7571 free_irq(h->intr[i], &h->q[i]);
7572 h->q[i] = 0;
7573 return;
7574 }
7575
7576 for (i = 0; i < h->msix_vector; i++) {
7577 irq_set_affinity_hint(h->intr[i], NULL);
7578 free_irq(h->intr[i], &h->q[i]);
7579 h->q[i] = 0;
7580 }
7581 for (; i < MAX_REPLY_QUEUES; i++)
7582 h->q[i] = 0;
7583 }
7584
7585 /* returns 0 on success; cleans up and returns -Enn on error */
7586 static int hpsa_request_irqs(struct ctlr_info *h,
7587 irqreturn_t (*msixhandler)(int, void *),
7588 irqreturn_t (*intxhandler)(int, void *))
7589 {
7590 int rc, i;
7591
7592 /*
7593 * initialize h->q[x] = x so that interrupt handlers know which
7594 * queue to process.
7595 */
7596 for (i = 0; i < MAX_REPLY_QUEUES; i++)
7597 h->q[i] = (u8) i;
7598
7599 if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) {
7600 /* If performant mode and MSI-X, use multiple reply queues */
7601 for (i = 0; i < h->msix_vector; i++) {
7602 sprintf(h->intrname[i], "%s-msix%d", h->devname, i);
7603 rc = request_irq(h->intr[i], msixhandler,
7604 0, h->intrname[i],
7605 &h->q[i]);
7606 if (rc) {
7607 int j;
7608
7609 dev_err(&h->pdev->dev,
7610 "failed to get irq %d for %s\n",
7611 h->intr[i], h->devname);
7612 for (j = 0; j < i; j++) {
7613 free_irq(h->intr[j], &h->q[j]);
7614 h->q[j] = 0;
7615 }
7616 for (; j < MAX_REPLY_QUEUES; j++)
7617 h->q[j] = 0;
7618 return rc;
7619 }
7620 }
7621 hpsa_irq_affinity_hints(h);
7622 } else {
7623 /* Use single reply pool */
7624 if (h->msix_vector > 0 || h->msi_vector) {
7625 if (h->msix_vector)
7626 sprintf(h->intrname[h->intr_mode],
7627 "%s-msix", h->devname);
7628 else
7629 sprintf(h->intrname[h->intr_mode],
7630 "%s-msi", h->devname);
7631 rc = request_irq(h->intr[h->intr_mode],
7632 msixhandler, 0,
7633 h->intrname[h->intr_mode],
7634 &h->q[h->intr_mode]);
7635 } else {
7636 sprintf(h->intrname[h->intr_mode],
7637 "%s-intx", h->devname);
7638 rc = request_irq(h->intr[h->intr_mode],
7639 intxhandler, IRQF_SHARED,
7640 h->intrname[h->intr_mode],
7641 &h->q[h->intr_mode]);
7642 }
7643 irq_set_affinity_hint(h->intr[h->intr_mode], NULL);
7644 }
7645 if (rc) {
7646 dev_err(&h->pdev->dev, "failed to get irq %d for %s\n",
7647 h->intr[h->intr_mode], h->devname);
7648 hpsa_free_irqs(h);
7649 return -ENODEV;
7650 }
7651 return 0;
7652 }
7653
7654 static int hpsa_kdump_soft_reset(struct ctlr_info *h)
7655 {
7656 int rc;
7657 hpsa_send_host_reset(h, RAID_CTLR_LUNID, HPSA_RESET_TYPE_CONTROLLER);
7658
7659 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
7660 rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY);
7661 if (rc) {
7662 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
7663 return rc;
7664 }
7665
7666 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
7667 rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
7668 if (rc) {
7669 dev_warn(&h->pdev->dev, "Board failed to become ready "
7670 "after soft reset.\n");
7671 return rc;
7672 }
7673
7674 return 0;
7675 }
7676
7677 static void hpsa_free_reply_queues(struct ctlr_info *h)
7678 {
7679 int i;
7680
7681 for (i = 0; i < h->nreply_queues; i++) {
7682 if (!h->reply_queue[i].head)
7683 continue;
7684 pci_free_consistent(h->pdev,
7685 h->reply_queue_size,
7686 h->reply_queue[i].head,
7687 h->reply_queue[i].busaddr);
7688 h->reply_queue[i].head = NULL;
7689 h->reply_queue[i].busaddr = 0;
7690 }
7691 h->reply_queue_size = 0;
7692 }
7693
7694 static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
7695 {
7696 hpsa_free_performant_mode(h); /* init_one 7 */
7697 hpsa_free_sg_chain_blocks(h); /* init_one 6 */
7698 hpsa_free_cmd_pool(h); /* init_one 5 */
7699 hpsa_free_irqs(h); /* init_one 4 */
7700 scsi_host_put(h->scsi_host); /* init_one 3 */
7701 h->scsi_host = NULL; /* init_one 3 */
7702 hpsa_free_pci_init(h); /* init_one 2_5 */
7703 free_percpu(h->lockup_detected); /* init_one 2 */
7704 h->lockup_detected = NULL; /* init_one 2 */
7705 if (h->resubmit_wq) {
7706 destroy_workqueue(h->resubmit_wq); /* init_one 1 */
7707 h->resubmit_wq = NULL;
7708 }
7709 if (h->rescan_ctlr_wq) {
7710 destroy_workqueue(h->rescan_ctlr_wq);
7711 h->rescan_ctlr_wq = NULL;
7712 }
7713 kfree(h); /* init_one 1 */
7714 }
7715
7716 /* Called when controller lockup detected. */
7717 static void fail_all_outstanding_cmds(struct ctlr_info *h)
7718 {
7719 int i, refcount;
7720 struct CommandList *c;
7721 int failcount = 0;
7722
7723 flush_workqueue(h->resubmit_wq); /* ensure all cmds are fully built */
7724 for (i = 0; i < h->nr_cmds; i++) {
7725 c = h->cmd_pool + i;
7726 refcount = atomic_inc_return(&c->refcount);
7727 if (refcount > 1) {
7728 c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
7729 finish_cmd(c);
7730 atomic_dec(&h->commands_outstanding);
7731 failcount++;
7732 }
7733 cmd_free(h, c);
7734 }
7735 dev_warn(&h->pdev->dev,
7736 "failed %d commands in fail_all\n", failcount);
7737 }
7738
7739 static void set_lockup_detected_for_all_cpus(struct ctlr_info *h, u32 value)
7740 {
7741 int cpu;
7742
7743 for_each_online_cpu(cpu) {
7744 u32 *lockup_detected;
7745 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
7746 *lockup_detected = value;
7747 }
7748 wmb(); /* be sure the per-cpu variables are out to memory */
7749 }
7750
7751 static void controller_lockup_detected(struct ctlr_info *h)
7752 {
7753 unsigned long flags;
7754 u32 lockup_detected;
7755
7756 h->access.set_intr_mask(h, HPSA_INTR_OFF);
7757 spin_lock_irqsave(&h->lock, flags);
7758 lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
7759 if (!lockup_detected) {
7760 /* no heartbeat, but controller gave us a zero. */
7761 dev_warn(&h->pdev->dev,
7762 "lockup detected after %d but scratchpad register is zero\n",
7763 h->heartbeat_sample_interval / HZ);
7764 lockup_detected = 0xffffffff;
7765 }
7766 set_lockup_detected_for_all_cpus(h, lockup_detected);
7767 spin_unlock_irqrestore(&h->lock, flags);
7768 dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x after %d\n",
7769 lockup_detected, h->heartbeat_sample_interval / HZ);
7770 pci_disable_device(h->pdev);
7771 fail_all_outstanding_cmds(h);
7772 }
7773
7774 static int detect_controller_lockup(struct ctlr_info *h)
7775 {
7776 u64 now;
7777 u32 heartbeat;
7778 unsigned long flags;
7779
7780 now = get_jiffies_64();
7781 /* If we've received an interrupt recently, we're ok. */
7782 if (time_after64(h->last_intr_timestamp +
7783 (h->heartbeat_sample_interval), now))
7784 return false;
7785
7786 /*
7787 * If we've already checked the heartbeat recently, we're ok.
7788 * This could happen if someone sends us a signal. We
7789 * otherwise don't care about signals in this thread.
7790 */
7791 if (time_after64(h->last_heartbeat_timestamp +
7792 (h->heartbeat_sample_interval), now))
7793 return false;
7794
7795 /* If heartbeat has not changed since we last looked, we're not ok. */
7796 spin_lock_irqsave(&h->lock, flags);
7797 heartbeat = readl(&h->cfgtable->HeartBeat);
7798 spin_unlock_irqrestore(&h->lock, flags);
7799 if (h->last_heartbeat == heartbeat) {
7800 controller_lockup_detected(h);
7801 return true;
7802 }
7803
7804 /* We're ok. */
7805 h->last_heartbeat = heartbeat;
7806 h->last_heartbeat_timestamp = now;
7807 return false;
7808 }
7809
7810 static void hpsa_ack_ctlr_events(struct ctlr_info *h)
7811 {
7812 int i;
7813 char *event_type;
7814
7815 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
7816 return;
7817
7818 /* Ask the controller to clear the events we're handling. */
7819 if ((h->transMethod & (CFGTBL_Trans_io_accel1
7820 | CFGTBL_Trans_io_accel2)) &&
7821 (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE ||
7822 h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) {
7823
7824 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE)
7825 event_type = "state change";
7826 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)
7827 event_type = "configuration change";
7828 /* Stop sending new RAID offload reqs via the IO accelerator */
7829 scsi_block_requests(h->scsi_host);
7830 for (i = 0; i < h->ndevices; i++)
7831 h->dev[i]->offload_enabled = 0;
7832 hpsa_drain_accel_commands(h);
7833 /* Set 'accelerator path config change' bit */
7834 dev_warn(&h->pdev->dev,
7835 "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n",
7836 h->events, event_type);
7837 writel(h->events, &(h->cfgtable->clear_event_notify));
7838 /* Set the "clear event notify field update" bit 6 */
7839 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
7840 /* Wait until ctlr clears 'clear event notify field', bit 6 */
7841 hpsa_wait_for_clear_event_notify_ack(h);
7842 scsi_unblock_requests(h->scsi_host);
7843 } else {
7844 /* Acknowledge controller notification events. */
7845 writel(h->events, &(h->cfgtable->clear_event_notify));
7846 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
7847 hpsa_wait_for_clear_event_notify_ack(h);
7848 #if 0
7849 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
7850 hpsa_wait_for_mode_change_ack(h);
7851 #endif
7852 }
7853 return;
7854 }
7855
7856 /* Check a register on the controller to see if there are configuration
7857 * changes (added/changed/removed logical drives, etc.) which mean that
7858 * we should rescan the controller for devices.
7859 * Also check flag for driver-initiated rescan.
7860 */
7861 static int hpsa_ctlr_needs_rescan(struct ctlr_info *h)
7862 {
7863 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
7864 return 0;
7865
7866 h->events = readl(&(h->cfgtable->event_notify));
7867 return h->events & RESCAN_REQUIRED_EVENT_BITS;
7868 }
7869
7870 /*
7871 * Check if any of the offline devices have become ready
7872 */
7873 static int hpsa_offline_devices_ready(struct ctlr_info *h)
7874 {
7875 unsigned long flags;
7876 struct offline_device_entry *d;
7877 struct list_head *this, *tmp;
7878
7879 spin_lock_irqsave(&h->offline_device_lock, flags);
7880 list_for_each_safe(this, tmp, &h->offline_device_list) {
7881 d = list_entry(this, struct offline_device_entry,
7882 offline_list);
7883 spin_unlock_irqrestore(&h->offline_device_lock, flags);
7884 if (!hpsa_volume_offline(h, d->scsi3addr)) {
7885 spin_lock_irqsave(&h->offline_device_lock, flags);
7886 list_del(&d->offline_list);
7887 spin_unlock_irqrestore(&h->offline_device_lock, flags);
7888 return 1;
7889 }
7890 spin_lock_irqsave(&h->offline_device_lock, flags);
7891 }
7892 spin_unlock_irqrestore(&h->offline_device_lock, flags);
7893 return 0;
7894 }
7895
7896 static void hpsa_rescan_ctlr_worker(struct work_struct *work)
7897 {
7898 unsigned long flags;
7899 struct ctlr_info *h = container_of(to_delayed_work(work),
7900 struct ctlr_info, rescan_ctlr_work);
7901
7902
7903 if (h->remove_in_progress)
7904 return;
7905
7906 if (hpsa_ctlr_needs_rescan(h) || hpsa_offline_devices_ready(h)) {
7907 scsi_host_get(h->scsi_host);
7908 hpsa_ack_ctlr_events(h);
7909 hpsa_scan_start(h->scsi_host);
7910 scsi_host_put(h->scsi_host);
7911 }
7912 spin_lock_irqsave(&h->lock, flags);
7913 if (!h->remove_in_progress)
7914 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
7915 h->heartbeat_sample_interval);
7916 spin_unlock_irqrestore(&h->lock, flags);
7917 }
7918
7919 static void hpsa_monitor_ctlr_worker(struct work_struct *work)
7920 {
7921 unsigned long flags;
7922 struct ctlr_info *h = container_of(to_delayed_work(work),
7923 struct ctlr_info, monitor_ctlr_work);
7924
7925 detect_controller_lockup(h);
7926 if (lockup_detected(h))
7927 return;
7928
7929 spin_lock_irqsave(&h->lock, flags);
7930 if (!h->remove_in_progress)
7931 schedule_delayed_work(&h->monitor_ctlr_work,
7932 h->heartbeat_sample_interval);
7933 spin_unlock_irqrestore(&h->lock, flags);
7934 }
7935
7936 static struct workqueue_struct *hpsa_create_controller_wq(struct ctlr_info *h,
7937 char *name)
7938 {
7939 struct workqueue_struct *wq = NULL;
7940
7941 wq = alloc_ordered_workqueue("%s_%d_hpsa", 0, name, h->ctlr);
7942 if (!wq)
7943 dev_err(&h->pdev->dev, "failed to create %s workqueue\n", name);
7944
7945 return wq;
7946 }
7947
7948 static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7949 {
7950 int dac, rc;
7951 struct ctlr_info *h;
7952 int try_soft_reset = 0;
7953 unsigned long flags;
7954 u32 board_id;
7955
7956 if (number_of_controllers == 0)
7957 printk(KERN_INFO DRIVER_NAME "\n");
7958
7959 rc = hpsa_lookup_board_id(pdev, &board_id);
7960 if (rc < 0) {
7961 dev_warn(&pdev->dev, "Board ID not found\n");
7962 return rc;
7963 }
7964
7965 rc = hpsa_init_reset_devices(pdev, board_id);
7966 if (rc) {
7967 if (rc != -ENOTSUPP)
7968 return rc;
7969 /* If the reset fails in a particular way (it has no way to do
7970 * a proper hard reset, so returns -ENOTSUPP) we can try to do
7971 * a soft reset once we get the controller configured up to the
7972 * point that it can accept a command.
7973 */
7974 try_soft_reset = 1;
7975 rc = 0;
7976 }
7977
7978 reinit_after_soft_reset:
7979
7980 /* Command structures must be aligned on a 32-byte boundary because
7981 * the 5 lower bits of the address are used by the hardware. and by
7982 * the driver. See comments in hpsa.h for more info.
7983 */
7984 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
7985 h = kzalloc(sizeof(*h), GFP_KERNEL);
7986 if (!h) {
7987 dev_err(&pdev->dev, "Failed to allocate controller head\n");
7988 return -ENOMEM;
7989 }
7990
7991 h->pdev = pdev;
7992
7993 h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
7994 INIT_LIST_HEAD(&h->offline_device_list);
7995 spin_lock_init(&h->lock);
7996 spin_lock_init(&h->offline_device_lock);
7997 spin_lock_init(&h->scan_lock);
7998 atomic_set(&h->passthru_cmds_avail, HPSA_MAX_CONCURRENT_PASSTHRUS);
7999 atomic_set(&h->abort_cmds_available, HPSA_CMDS_RESERVED_FOR_ABORTS);
8000
8001 /* Allocate and clear per-cpu variable lockup_detected */
8002 h->lockup_detected = alloc_percpu(u32);
8003 if (!h->lockup_detected) {
8004 dev_err(&h->pdev->dev, "Failed to allocate lockup detector\n");
8005 rc = -ENOMEM;
8006 goto clean1; /* aer/h */
8007 }
8008 set_lockup_detected_for_all_cpus(h, 0);
8009
8010 rc = hpsa_pci_init(h);
8011 if (rc)
8012 goto clean2; /* lu, aer/h */
8013
8014 /* relies on h-> settings made by hpsa_pci_init, including
8015 * interrupt_mode h->intr */
8016 rc = hpsa_scsi_host_alloc(h);
8017 if (rc)
8018 goto clean2_5; /* pci, lu, aer/h */
8019
8020 sprintf(h->devname, HPSA "%d", h->scsi_host->host_no);
8021 h->ctlr = number_of_controllers;
8022 number_of_controllers++;
8023
8024 /* configure PCI DMA stuff */
8025 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
8026 if (rc == 0) {
8027 dac = 1;
8028 } else {
8029 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8030 if (rc == 0) {
8031 dac = 0;
8032 } else {
8033 dev_err(&pdev->dev, "no suitable DMA available\n");
8034 goto clean3; /* shost, pci, lu, aer/h */
8035 }
8036 }
8037
8038 /* make sure the board interrupts are off */
8039 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8040
8041 rc = hpsa_request_irqs(h, do_hpsa_intr_msi, do_hpsa_intr_intx);
8042 if (rc)
8043 goto clean3; /* shost, pci, lu, aer/h */
8044 rc = hpsa_alloc_cmd_pool(h);
8045 if (rc)
8046 goto clean4; /* irq, shost, pci, lu, aer/h */
8047 rc = hpsa_alloc_sg_chain_blocks(h);
8048 if (rc)
8049 goto clean5; /* cmd, irq, shost, pci, lu, aer/h */
8050 init_waitqueue_head(&h->scan_wait_queue);
8051 init_waitqueue_head(&h->abort_cmd_wait_queue);
8052 init_waitqueue_head(&h->event_sync_wait_queue);
8053 mutex_init(&h->reset_mutex);
8054 h->scan_finished = 1; /* no scan currently in progress */
8055
8056 pci_set_drvdata(pdev, h);
8057 h->ndevices = 0;
8058
8059 spin_lock_init(&h->devlock);
8060 rc = hpsa_put_ctlr_into_performant_mode(h);
8061 if (rc)
8062 goto clean6; /* sg, cmd, irq, shost, pci, lu, aer/h */
8063
8064 /* hook into SCSI subsystem */
8065 rc = hpsa_scsi_add_host(h);
8066 if (rc)
8067 goto clean7; /* perf, sg, cmd, irq, shost, pci, lu, aer/h */
8068
8069 /* create the resubmit workqueue */
8070 h->rescan_ctlr_wq = hpsa_create_controller_wq(h, "rescan");
8071 if (!h->rescan_ctlr_wq) {
8072 rc = -ENOMEM;
8073 goto clean7;
8074 }
8075
8076 h->resubmit_wq = hpsa_create_controller_wq(h, "resubmit");
8077 if (!h->resubmit_wq) {
8078 rc = -ENOMEM;
8079 goto clean7; /* aer/h */
8080 }
8081
8082 /*
8083 * At this point, the controller is ready to take commands.
8084 * Now, if reset_devices and the hard reset didn't work, try
8085 * the soft reset and see if that works.
8086 */
8087 if (try_soft_reset) {
8088
8089 /* This is kind of gross. We may or may not get a completion
8090 * from the soft reset command, and if we do, then the value
8091 * from the fifo may or may not be valid. So, we wait 10 secs
8092 * after the reset throwing away any completions we get during
8093 * that time. Unregister the interrupt handler and register
8094 * fake ones to scoop up any residual completions.
8095 */
8096 spin_lock_irqsave(&h->lock, flags);
8097 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8098 spin_unlock_irqrestore(&h->lock, flags);
8099 hpsa_free_irqs(h);
8100 rc = hpsa_request_irqs(h, hpsa_msix_discard_completions,
8101 hpsa_intx_discard_completions);
8102 if (rc) {
8103 dev_warn(&h->pdev->dev,
8104 "Failed to request_irq after soft reset.\n");
8105 /*
8106 * cannot goto clean7 or free_irqs will be called
8107 * again. Instead, do its work
8108 */
8109 hpsa_free_performant_mode(h); /* clean7 */
8110 hpsa_free_sg_chain_blocks(h); /* clean6 */
8111 hpsa_free_cmd_pool(h); /* clean5 */
8112 /*
8113 * skip hpsa_free_irqs(h) clean4 since that
8114 * was just called before request_irqs failed
8115 */
8116 goto clean3;
8117 }
8118
8119 rc = hpsa_kdump_soft_reset(h);
8120 if (rc)
8121 /* Neither hard nor soft reset worked, we're hosed. */
8122 goto clean7;
8123
8124 dev_info(&h->pdev->dev, "Board READY.\n");
8125 dev_info(&h->pdev->dev,
8126 "Waiting for stale completions to drain.\n");
8127 h->access.set_intr_mask(h, HPSA_INTR_ON);
8128 msleep(10000);
8129 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8130
8131 rc = controller_reset_failed(h->cfgtable);
8132 if (rc)
8133 dev_info(&h->pdev->dev,
8134 "Soft reset appears to have failed.\n");
8135
8136 /* since the controller's reset, we have to go back and re-init
8137 * everything. Easiest to just forget what we've done and do it
8138 * all over again.
8139 */
8140 hpsa_undo_allocations_after_kdump_soft_reset(h);
8141 try_soft_reset = 0;
8142 if (rc)
8143 /* don't goto clean, we already unallocated */
8144 return -ENODEV;
8145
8146 goto reinit_after_soft_reset;
8147 }
8148
8149 /* Enable Accelerated IO path at driver layer */
8150 h->acciopath_status = 1;
8151
8152
8153 /* Turn the interrupts on so we can service requests */
8154 h->access.set_intr_mask(h, HPSA_INTR_ON);
8155
8156 hpsa_hba_inquiry(h);
8157
8158 /* Monitor the controller for firmware lockups */
8159 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
8160 INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
8161 schedule_delayed_work(&h->monitor_ctlr_work,
8162 h->heartbeat_sample_interval);
8163 INIT_DELAYED_WORK(&h->rescan_ctlr_work, hpsa_rescan_ctlr_worker);
8164 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
8165 h->heartbeat_sample_interval);
8166 return 0;
8167
8168 clean7: /* perf, sg, cmd, irq, shost, pci, lu, aer/h */
8169 hpsa_free_performant_mode(h);
8170 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8171 clean6: /* sg, cmd, irq, pci, lockup, wq/aer/h */
8172 hpsa_free_sg_chain_blocks(h);
8173 clean5: /* cmd, irq, shost, pci, lu, aer/h */
8174 hpsa_free_cmd_pool(h);
8175 clean4: /* irq, shost, pci, lu, aer/h */
8176 hpsa_free_irqs(h);
8177 clean3: /* shost, pci, lu, aer/h */
8178 scsi_host_put(h->scsi_host);
8179 h->scsi_host = NULL;
8180 clean2_5: /* pci, lu, aer/h */
8181 hpsa_free_pci_init(h);
8182 clean2: /* lu, aer/h */
8183 if (h->lockup_detected) {
8184 free_percpu(h->lockup_detected);
8185 h->lockup_detected = NULL;
8186 }
8187 clean1: /* wq/aer/h */
8188 if (h->resubmit_wq) {
8189 destroy_workqueue(h->resubmit_wq);
8190 h->resubmit_wq = NULL;
8191 }
8192 if (h->rescan_ctlr_wq) {
8193 destroy_workqueue(h->rescan_ctlr_wq);
8194 h->rescan_ctlr_wq = NULL;
8195 }
8196 kfree(h);
8197 return rc;
8198 }
8199
8200 static void hpsa_flush_cache(struct ctlr_info *h)
8201 {
8202 char *flush_buf;
8203 struct CommandList *c;
8204 int rc;
8205
8206 if (unlikely(lockup_detected(h)))
8207 return;
8208 flush_buf = kzalloc(4, GFP_KERNEL);
8209 if (!flush_buf)
8210 return;
8211
8212 c = cmd_alloc(h);
8213
8214 if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
8215 RAID_CTLR_LUNID, TYPE_CMD)) {
8216 goto out;
8217 }
8218 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
8219 PCI_DMA_TODEVICE, NO_TIMEOUT);
8220 if (rc)
8221 goto out;
8222 if (c->err_info->CommandStatus != 0)
8223 out:
8224 dev_warn(&h->pdev->dev,
8225 "error flushing cache on controller\n");
8226 cmd_free(h, c);
8227 kfree(flush_buf);
8228 }
8229
8230 static void hpsa_shutdown(struct pci_dev *pdev)
8231 {
8232 struct ctlr_info *h;
8233
8234 h = pci_get_drvdata(pdev);
8235 /* Turn board interrupts off and send the flush cache command
8236 * sendcmd will turn off interrupt, and send the flush...
8237 * To write all data in the battery backed cache to disks
8238 */
8239 hpsa_flush_cache(h);
8240 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8241 hpsa_free_irqs(h); /* init_one 4 */
8242 hpsa_disable_interrupt_mode(h); /* pci_init 2 */
8243 }
8244
8245 static void hpsa_free_device_info(struct ctlr_info *h)
8246 {
8247 int i;
8248
8249 for (i = 0; i < h->ndevices; i++) {
8250 kfree(h->dev[i]);
8251 h->dev[i] = NULL;
8252 }
8253 }
8254
8255 static void hpsa_remove_one(struct pci_dev *pdev)
8256 {
8257 struct ctlr_info *h;
8258 unsigned long flags;
8259
8260 if (pci_get_drvdata(pdev) == NULL) {
8261 dev_err(&pdev->dev, "unable to remove device\n");
8262 return;
8263 }
8264 h = pci_get_drvdata(pdev);
8265
8266 /* Get rid of any controller monitoring work items */
8267 spin_lock_irqsave(&h->lock, flags);
8268 h->remove_in_progress = 1;
8269 spin_unlock_irqrestore(&h->lock, flags);
8270 cancel_delayed_work_sync(&h->monitor_ctlr_work);
8271 cancel_delayed_work_sync(&h->rescan_ctlr_work);
8272 destroy_workqueue(h->rescan_ctlr_wq);
8273 destroy_workqueue(h->resubmit_wq);
8274
8275 /*
8276 * Call before disabling interrupts.
8277 * scsi_remove_host can trigger I/O operations especially
8278 * when multipath is enabled. There can be SYNCHRONIZE CACHE
8279 * operations which cannot complete and will hang the system.
8280 */
8281 if (h->scsi_host)
8282 scsi_remove_host(h->scsi_host); /* init_one 8 */
8283 /* includes hpsa_free_irqs - init_one 4 */
8284 /* includes hpsa_disable_interrupt_mode - pci_init 2 */
8285 hpsa_shutdown(pdev);
8286
8287 hpsa_free_device_info(h); /* scan */
8288
8289 kfree(h->hba_inquiry_data); /* init_one 10 */
8290 h->hba_inquiry_data = NULL; /* init_one 10 */
8291 hpsa_free_ioaccel2_sg_chain_blocks(h);
8292 hpsa_free_performant_mode(h); /* init_one 7 */
8293 hpsa_free_sg_chain_blocks(h); /* init_one 6 */
8294 hpsa_free_cmd_pool(h); /* init_one 5 */
8295
8296 /* hpsa_free_irqs already called via hpsa_shutdown init_one 4 */
8297
8298 scsi_host_put(h->scsi_host); /* init_one 3 */
8299 h->scsi_host = NULL; /* init_one 3 */
8300
8301 /* includes hpsa_disable_interrupt_mode - pci_init 2 */
8302 hpsa_free_pci_init(h); /* init_one 2.5 */
8303
8304 free_percpu(h->lockup_detected); /* init_one 2 */
8305 h->lockup_detected = NULL; /* init_one 2 */
8306 /* (void) pci_disable_pcie_error_reporting(pdev); */ /* init_one 1 */
8307 kfree(h); /* init_one 1 */
8308 }
8309
8310 static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
8311 __attribute__((unused)) pm_message_t state)
8312 {
8313 return -ENOSYS;
8314 }
8315
8316 static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
8317 {
8318 return -ENOSYS;
8319 }
8320
8321 static struct pci_driver hpsa_pci_driver = {
8322 .name = HPSA,
8323 .probe = hpsa_init_one,
8324 .remove = hpsa_remove_one,
8325 .id_table = hpsa_pci_device_id, /* id_table */
8326 .shutdown = hpsa_shutdown,
8327 .suspend = hpsa_suspend,
8328 .resume = hpsa_resume,
8329 };
8330
8331 /* Fill in bucket_map[], given nsgs (the max number of
8332 * scatter gather elements supported) and bucket[],
8333 * which is an array of 8 integers. The bucket[] array
8334 * contains 8 different DMA transfer sizes (in 16
8335 * byte increments) which the controller uses to fetch
8336 * commands. This function fills in bucket_map[], which
8337 * maps a given number of scatter gather elements to one of
8338 * the 8 DMA transfer sizes. The point of it is to allow the
8339 * controller to only do as much DMA as needed to fetch the
8340 * command, with the DMA transfer size encoded in the lower
8341 * bits of the command address.
8342 */
8343 static void calc_bucket_map(int bucket[], int num_buckets,
8344 int nsgs, int min_blocks, u32 *bucket_map)
8345 {
8346 int i, j, b, size;
8347
8348 /* Note, bucket_map must have nsgs+1 entries. */
8349 for (i = 0; i <= nsgs; i++) {
8350 /* Compute size of a command with i SG entries */
8351 size = i + min_blocks;
8352 b = num_buckets; /* Assume the biggest bucket */
8353 /* Find the bucket that is just big enough */
8354 for (j = 0; j < num_buckets; j++) {
8355 if (bucket[j] >= size) {
8356 b = j;
8357 break;
8358 }
8359 }
8360 /* for a command with i SG entries, use bucket b. */
8361 bucket_map[i] = b;
8362 }
8363 }
8364
8365 /*
8366 * return -ENODEV on err, 0 on success (or no action)
8367 * allocates numerous items that must be freed later
8368 */
8369 static int hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
8370 {
8371 int i;
8372 unsigned long register_value;
8373 unsigned long transMethod = CFGTBL_Trans_Performant |
8374 (trans_support & CFGTBL_Trans_use_short_tags) |
8375 CFGTBL_Trans_enable_directed_msix |
8376 (trans_support & (CFGTBL_Trans_io_accel1 |
8377 CFGTBL_Trans_io_accel2));
8378 struct access_method access = SA5_performant_access;
8379
8380 /* This is a bit complicated. There are 8 registers on
8381 * the controller which we write to to tell it 8 different
8382 * sizes of commands which there may be. It's a way of
8383 * reducing the DMA done to fetch each command. Encoded into
8384 * each command's tag are 3 bits which communicate to the controller
8385 * which of the eight sizes that command fits within. The size of
8386 * each command depends on how many scatter gather entries there are.
8387 * Each SG entry requires 16 bytes. The eight registers are programmed
8388 * with the number of 16-byte blocks a command of that size requires.
8389 * The smallest command possible requires 5 such 16 byte blocks.
8390 * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
8391 * blocks. Note, this only extends to the SG entries contained
8392 * within the command block, and does not extend to chained blocks
8393 * of SG elements. bft[] contains the eight values we write to
8394 * the registers. They are not evenly distributed, but have more
8395 * sizes for small commands, and fewer sizes for larger commands.
8396 */
8397 int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
8398 #define MIN_IOACCEL2_BFT_ENTRY 5
8399 #define HPSA_IOACCEL2_HEADER_SZ 4
8400 int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12,
8401 13, 14, 15, 16, 17, 18, 19,
8402 HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES};
8403 BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16);
8404 BUILD_BUG_ON(ARRAY_SIZE(bft) != 8);
8405 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) >
8406 16 * MIN_IOACCEL2_BFT_ENTRY);
8407 BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16);
8408 BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
8409 /* 5 = 1 s/g entry or 4k
8410 * 6 = 2 s/g entry or 8k
8411 * 8 = 4 s/g entry or 16k
8412 * 10 = 6 s/g entry or 24k
8413 */
8414
8415 /* If the controller supports either ioaccel method then
8416 * we can also use the RAID stack submit path that does not
8417 * perform the superfluous readl() after each command submission.
8418 */
8419 if (trans_support & (CFGTBL_Trans_io_accel1 | CFGTBL_Trans_io_accel2))
8420 access = SA5_performant_access_no_read;
8421
8422 /* Controller spec: zero out this buffer. */
8423 for (i = 0; i < h->nreply_queues; i++)
8424 memset(h->reply_queue[i].head, 0, h->reply_queue_size);
8425
8426 bft[7] = SG_ENTRIES_IN_CMD + 4;
8427 calc_bucket_map(bft, ARRAY_SIZE(bft),
8428 SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
8429 for (i = 0; i < 8; i++)
8430 writel(bft[i], &h->transtable->BlockFetch[i]);
8431
8432 /* size of controller ring buffer */
8433 writel(h->max_commands, &h->transtable->RepQSize);
8434 writel(h->nreply_queues, &h->transtable->RepQCount);
8435 writel(0, &h->transtable->RepQCtrAddrLow32);
8436 writel(0, &h->transtable->RepQCtrAddrHigh32);
8437
8438 for (i = 0; i < h->nreply_queues; i++) {
8439 writel(0, &h->transtable->RepQAddr[i].upper);
8440 writel(h->reply_queue[i].busaddr,
8441 &h->transtable->RepQAddr[i].lower);
8442 }
8443
8444 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
8445 writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
8446 /*
8447 * enable outbound interrupt coalescing in accelerator mode;
8448 */
8449 if (trans_support & CFGTBL_Trans_io_accel1) {
8450 access = SA5_ioaccel_mode1_access;
8451 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
8452 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
8453 } else {
8454 if (trans_support & CFGTBL_Trans_io_accel2) {
8455 access = SA5_ioaccel_mode2_access;
8456 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
8457 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
8458 }
8459 }
8460 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
8461 if (hpsa_wait_for_mode_change_ack(h)) {
8462 dev_err(&h->pdev->dev,
8463 "performant mode problem - doorbell timeout\n");
8464 return -ENODEV;
8465 }
8466 register_value = readl(&(h->cfgtable->TransportActive));
8467 if (!(register_value & CFGTBL_Trans_Performant)) {
8468 dev_err(&h->pdev->dev,
8469 "performant mode problem - transport not active\n");
8470 return -ENODEV;
8471 }
8472 /* Change the access methods to the performant access methods */
8473 h->access = access;
8474 h->transMethod = transMethod;
8475
8476 if (!((trans_support & CFGTBL_Trans_io_accel1) ||
8477 (trans_support & CFGTBL_Trans_io_accel2)))
8478 return 0;
8479
8480 if (trans_support & CFGTBL_Trans_io_accel1) {
8481 /* Set up I/O accelerator mode */
8482 for (i = 0; i < h->nreply_queues; i++) {
8483 writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
8484 h->reply_queue[i].current_entry =
8485 readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
8486 }
8487 bft[7] = h->ioaccel_maxsg + 8;
8488 calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
8489 h->ioaccel1_blockFetchTable);
8490
8491 /* initialize all reply queue entries to unused */
8492 for (i = 0; i < h->nreply_queues; i++)
8493 memset(h->reply_queue[i].head,
8494 (u8) IOACCEL_MODE1_REPLY_UNUSED,
8495 h->reply_queue_size);
8496
8497 /* set all the constant fields in the accelerator command
8498 * frames once at init time to save CPU cycles later.
8499 */
8500 for (i = 0; i < h->nr_cmds; i++) {
8501 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
8502
8503 cp->function = IOACCEL1_FUNCTION_SCSIIO;
8504 cp->err_info = (u32) (h->errinfo_pool_dhandle +
8505 (i * sizeof(struct ErrorInfo)));
8506 cp->err_info_len = sizeof(struct ErrorInfo);
8507 cp->sgl_offset = IOACCEL1_SGLOFFSET;
8508 cp->host_context_flags =
8509 cpu_to_le16(IOACCEL1_HCFLAGS_CISS_FORMAT);
8510 cp->timeout_sec = 0;
8511 cp->ReplyQueue = 0;
8512 cp->tag =
8513 cpu_to_le64((i << DIRECT_LOOKUP_SHIFT));
8514 cp->host_addr =
8515 cpu_to_le64(h->ioaccel_cmd_pool_dhandle +
8516 (i * sizeof(struct io_accel1_cmd)));
8517 }
8518 } else if (trans_support & CFGTBL_Trans_io_accel2) {
8519 u64 cfg_offset, cfg_base_addr_index;
8520 u32 bft2_offset, cfg_base_addr;
8521 int rc;
8522
8523 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
8524 &cfg_base_addr_index, &cfg_offset);
8525 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64);
8526 bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ;
8527 calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg,
8528 4, h->ioaccel2_blockFetchTable);
8529 bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset);
8530 BUILD_BUG_ON(offsetof(struct CfgTable,
8531 io_accel_request_size_offset) != 0xb8);
8532 h->ioaccel2_bft2_regs =
8533 remap_pci_mem(pci_resource_start(h->pdev,
8534 cfg_base_addr_index) +
8535 cfg_offset + bft2_offset,
8536 ARRAY_SIZE(bft2) *
8537 sizeof(*h->ioaccel2_bft2_regs));
8538 for (i = 0; i < ARRAY_SIZE(bft2); i++)
8539 writel(bft2[i], &h->ioaccel2_bft2_regs[i]);
8540 }
8541 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
8542 if (hpsa_wait_for_mode_change_ack(h)) {
8543 dev_err(&h->pdev->dev,
8544 "performant mode problem - enabling ioaccel mode\n");
8545 return -ENODEV;
8546 }
8547 return 0;
8548 }
8549
8550 /* Free ioaccel1 mode command blocks and block fetch table */
8551 static void hpsa_free_ioaccel1_cmd_and_bft(struct ctlr_info *h)
8552 {
8553 if (h->ioaccel_cmd_pool) {
8554 pci_free_consistent(h->pdev,
8555 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
8556 h->ioaccel_cmd_pool,
8557 h->ioaccel_cmd_pool_dhandle);
8558 h->ioaccel_cmd_pool = NULL;
8559 h->ioaccel_cmd_pool_dhandle = 0;
8560 }
8561 kfree(h->ioaccel1_blockFetchTable);
8562 h->ioaccel1_blockFetchTable = NULL;
8563 }
8564
8565 /* Allocate ioaccel1 mode command blocks and block fetch table */
8566 static int hpsa_alloc_ioaccel1_cmd_and_bft(struct ctlr_info *h)
8567 {
8568 h->ioaccel_maxsg =
8569 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
8570 if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
8571 h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
8572
8573 /* Command structures must be aligned on a 128-byte boundary
8574 * because the 7 lower bits of the address are used by the
8575 * hardware.
8576 */
8577 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
8578 IOACCEL1_COMMANDLIST_ALIGNMENT);
8579 h->ioaccel_cmd_pool =
8580 pci_alloc_consistent(h->pdev,
8581 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
8582 &(h->ioaccel_cmd_pool_dhandle));
8583
8584 h->ioaccel1_blockFetchTable =
8585 kmalloc(((h->ioaccel_maxsg + 1) *
8586 sizeof(u32)), GFP_KERNEL);
8587
8588 if ((h->ioaccel_cmd_pool == NULL) ||
8589 (h->ioaccel1_blockFetchTable == NULL))
8590 goto clean_up;
8591
8592 memset(h->ioaccel_cmd_pool, 0,
8593 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
8594 return 0;
8595
8596 clean_up:
8597 hpsa_free_ioaccel1_cmd_and_bft(h);
8598 return -ENOMEM;
8599 }
8600
8601 /* Free ioaccel2 mode command blocks and block fetch table */
8602 static void hpsa_free_ioaccel2_cmd_and_bft(struct ctlr_info *h)
8603 {
8604 hpsa_free_ioaccel2_sg_chain_blocks(h);
8605
8606 if (h->ioaccel2_cmd_pool) {
8607 pci_free_consistent(h->pdev,
8608 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
8609 h->ioaccel2_cmd_pool,
8610 h->ioaccel2_cmd_pool_dhandle);
8611 h->ioaccel2_cmd_pool = NULL;
8612 h->ioaccel2_cmd_pool_dhandle = 0;
8613 }
8614 kfree(h->ioaccel2_blockFetchTable);
8615 h->ioaccel2_blockFetchTable = NULL;
8616 }
8617
8618 /* Allocate ioaccel2 mode command blocks and block fetch table */
8619 static int hpsa_alloc_ioaccel2_cmd_and_bft(struct ctlr_info *h)
8620 {
8621 int rc;
8622
8623 /* Allocate ioaccel2 mode command blocks and block fetch table */
8624
8625 h->ioaccel_maxsg =
8626 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
8627 if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES)
8628 h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES;
8629
8630 BUILD_BUG_ON(sizeof(struct io_accel2_cmd) %
8631 IOACCEL2_COMMANDLIST_ALIGNMENT);
8632 h->ioaccel2_cmd_pool =
8633 pci_alloc_consistent(h->pdev,
8634 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
8635 &(h->ioaccel2_cmd_pool_dhandle));
8636
8637 h->ioaccel2_blockFetchTable =
8638 kmalloc(((h->ioaccel_maxsg + 1) *
8639 sizeof(u32)), GFP_KERNEL);
8640
8641 if ((h->ioaccel2_cmd_pool == NULL) ||
8642 (h->ioaccel2_blockFetchTable == NULL)) {
8643 rc = -ENOMEM;
8644 goto clean_up;
8645 }
8646
8647 rc = hpsa_allocate_ioaccel2_sg_chain_blocks(h);
8648 if (rc)
8649 goto clean_up;
8650
8651 memset(h->ioaccel2_cmd_pool, 0,
8652 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool));
8653 return 0;
8654
8655 clean_up:
8656 hpsa_free_ioaccel2_cmd_and_bft(h);
8657 return rc;
8658 }
8659
8660 /* Free items allocated by hpsa_put_ctlr_into_performant_mode */
8661 static void hpsa_free_performant_mode(struct ctlr_info *h)
8662 {
8663 kfree(h->blockFetchTable);
8664 h->blockFetchTable = NULL;
8665 hpsa_free_reply_queues(h);
8666 hpsa_free_ioaccel1_cmd_and_bft(h);
8667 hpsa_free_ioaccel2_cmd_and_bft(h);
8668 }
8669
8670 /* return -ENODEV on error, 0 on success (or no action)
8671 * allocates numerous items that must be freed later
8672 */
8673 static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
8674 {
8675 u32 trans_support;
8676 unsigned long transMethod = CFGTBL_Trans_Performant |
8677 CFGTBL_Trans_use_short_tags;
8678 int i, rc;
8679
8680 if (hpsa_simple_mode)
8681 return 0;
8682
8683 trans_support = readl(&(h->cfgtable->TransportSupport));
8684 if (!(trans_support & PERFORMANT_MODE))
8685 return 0;
8686
8687 /* Check for I/O accelerator mode support */
8688 if (trans_support & CFGTBL_Trans_io_accel1) {
8689 transMethod |= CFGTBL_Trans_io_accel1 |
8690 CFGTBL_Trans_enable_directed_msix;
8691 rc = hpsa_alloc_ioaccel1_cmd_and_bft(h);
8692 if (rc)
8693 return rc;
8694 } else if (trans_support & CFGTBL_Trans_io_accel2) {
8695 transMethod |= CFGTBL_Trans_io_accel2 |
8696 CFGTBL_Trans_enable_directed_msix;
8697 rc = hpsa_alloc_ioaccel2_cmd_and_bft(h);
8698 if (rc)
8699 return rc;
8700 }
8701
8702 h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1;
8703 hpsa_get_max_perf_mode_cmds(h);
8704 /* Performant mode ring buffer and supporting data structures */
8705 h->reply_queue_size = h->max_commands * sizeof(u64);
8706
8707 for (i = 0; i < h->nreply_queues; i++) {
8708 h->reply_queue[i].head = pci_alloc_consistent(h->pdev,
8709 h->reply_queue_size,
8710 &(h->reply_queue[i].busaddr));
8711 if (!h->reply_queue[i].head) {
8712 rc = -ENOMEM;
8713 goto clean1; /* rq, ioaccel */
8714 }
8715 h->reply_queue[i].size = h->max_commands;
8716 h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
8717 h->reply_queue[i].current_entry = 0;
8718 }
8719
8720 /* Need a block fetch table for performant mode */
8721 h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
8722 sizeof(u32)), GFP_KERNEL);
8723 if (!h->blockFetchTable) {
8724 rc = -ENOMEM;
8725 goto clean1; /* rq, ioaccel */
8726 }
8727
8728 rc = hpsa_enter_performant_mode(h, trans_support);
8729 if (rc)
8730 goto clean2; /* bft, rq, ioaccel */
8731 return 0;
8732
8733 clean2: /* bft, rq, ioaccel */
8734 kfree(h->blockFetchTable);
8735 h->blockFetchTable = NULL;
8736 clean1: /* rq, ioaccel */
8737 hpsa_free_reply_queues(h);
8738 hpsa_free_ioaccel1_cmd_and_bft(h);
8739 hpsa_free_ioaccel2_cmd_and_bft(h);
8740 return rc;
8741 }
8742
8743 static int is_accelerated_cmd(struct CommandList *c)
8744 {
8745 return c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_IOACCEL2;
8746 }
8747
8748 static void hpsa_drain_accel_commands(struct ctlr_info *h)
8749 {
8750 struct CommandList *c = NULL;
8751 int i, accel_cmds_out;
8752 int refcount;
8753
8754 do { /* wait for all outstanding ioaccel commands to drain out */
8755 accel_cmds_out = 0;
8756 for (i = 0; i < h->nr_cmds; i++) {
8757 c = h->cmd_pool + i;
8758 refcount = atomic_inc_return(&c->refcount);
8759 if (refcount > 1) /* Command is allocated */
8760 accel_cmds_out += is_accelerated_cmd(c);
8761 cmd_free(h, c);
8762 }
8763 if (accel_cmds_out <= 0)
8764 break;
8765 msleep(100);
8766 } while (1);
8767 }
8768
8769 /*
8770 * This is it. Register the PCI driver information for the cards we control
8771 * the OS will call our registered routines when it finds one of our cards.
8772 */
8773 static int __init hpsa_init(void)
8774 {
8775 return pci_register_driver(&hpsa_pci_driver);
8776 }
8777
8778 static void __exit hpsa_cleanup(void)
8779 {
8780 pci_unregister_driver(&hpsa_pci_driver);
8781 }
8782
8783 static void __attribute__((unused)) verify_offsets(void)
8784 {
8785 #define VERIFY_OFFSET(member, offset) \
8786 BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset)
8787
8788 VERIFY_OFFSET(structure_size, 0);
8789 VERIFY_OFFSET(volume_blk_size, 4);
8790 VERIFY_OFFSET(volume_blk_cnt, 8);
8791 VERIFY_OFFSET(phys_blk_shift, 16);
8792 VERIFY_OFFSET(parity_rotation_shift, 17);
8793 VERIFY_OFFSET(strip_size, 18);
8794 VERIFY_OFFSET(disk_starting_blk, 20);
8795 VERIFY_OFFSET(disk_blk_cnt, 28);
8796 VERIFY_OFFSET(data_disks_per_row, 36);
8797 VERIFY_OFFSET(metadata_disks_per_row, 38);
8798 VERIFY_OFFSET(row_cnt, 40);
8799 VERIFY_OFFSET(layout_map_count, 42);
8800 VERIFY_OFFSET(flags, 44);
8801 VERIFY_OFFSET(dekindex, 46);
8802 /* VERIFY_OFFSET(reserved, 48 */
8803 VERIFY_OFFSET(data, 64);
8804
8805 #undef VERIFY_OFFSET
8806
8807 #define VERIFY_OFFSET(member, offset) \
8808 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset)
8809
8810 VERIFY_OFFSET(IU_type, 0);
8811 VERIFY_OFFSET(direction, 1);
8812 VERIFY_OFFSET(reply_queue, 2);
8813 /* VERIFY_OFFSET(reserved1, 3); */
8814 VERIFY_OFFSET(scsi_nexus, 4);
8815 VERIFY_OFFSET(Tag, 8);
8816 VERIFY_OFFSET(cdb, 16);
8817 VERIFY_OFFSET(cciss_lun, 32);
8818 VERIFY_OFFSET(data_len, 40);
8819 VERIFY_OFFSET(cmd_priority_task_attr, 44);
8820 VERIFY_OFFSET(sg_count, 45);
8821 /* VERIFY_OFFSET(reserved3 */
8822 VERIFY_OFFSET(err_ptr, 48);
8823 VERIFY_OFFSET(err_len, 56);
8824 /* VERIFY_OFFSET(reserved4 */
8825 VERIFY_OFFSET(sg, 64);
8826
8827 #undef VERIFY_OFFSET
8828
8829 #define VERIFY_OFFSET(member, offset) \
8830 BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
8831
8832 VERIFY_OFFSET(dev_handle, 0x00);
8833 VERIFY_OFFSET(reserved1, 0x02);
8834 VERIFY_OFFSET(function, 0x03);
8835 VERIFY_OFFSET(reserved2, 0x04);
8836 VERIFY_OFFSET(err_info, 0x0C);
8837 VERIFY_OFFSET(reserved3, 0x10);
8838 VERIFY_OFFSET(err_info_len, 0x12);
8839 VERIFY_OFFSET(reserved4, 0x13);
8840 VERIFY_OFFSET(sgl_offset, 0x14);
8841 VERIFY_OFFSET(reserved5, 0x15);
8842 VERIFY_OFFSET(transfer_len, 0x1C);
8843 VERIFY_OFFSET(reserved6, 0x20);
8844 VERIFY_OFFSET(io_flags, 0x24);
8845 VERIFY_OFFSET(reserved7, 0x26);
8846 VERIFY_OFFSET(LUN, 0x34);
8847 VERIFY_OFFSET(control, 0x3C);
8848 VERIFY_OFFSET(CDB, 0x40);
8849 VERIFY_OFFSET(reserved8, 0x50);
8850 VERIFY_OFFSET(host_context_flags, 0x60);
8851 VERIFY_OFFSET(timeout_sec, 0x62);
8852 VERIFY_OFFSET(ReplyQueue, 0x64);
8853 VERIFY_OFFSET(reserved9, 0x65);
8854 VERIFY_OFFSET(tag, 0x68);
8855 VERIFY_OFFSET(host_addr, 0x70);
8856 VERIFY_OFFSET(CISS_LUN, 0x78);
8857 VERIFY_OFFSET(SG, 0x78 + 8);
8858 #undef VERIFY_OFFSET
8859 }
8860
8861 module_init(hpsa_init);
8862 module_exit(hpsa_cleanup);
Linux with added FPC-III support