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ocfs2: fix several issues of append dio
[linux/fpc-iii.git] / drivers / scsi / ufs / ufs-qcom.c
blob4cdffa46d401a5ea6120ba5d350e453158166a31
1 /*
2 * Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 */
14
15 #include <linux/time.h>
16 #include <linux/of.h>
17 #include <linux/platform_device.h>
18 #include <linux/phy/phy.h>
19
20 #include <linux/phy/phy-qcom-ufs.h>
21 #include "ufshcd.h"
22 #include "unipro.h"
23 #include "ufs-qcom.h"
24 #include "ufshci.h"
25
26 static struct ufs_qcom_host *ufs_qcom_hosts[MAX_UFS_QCOM_HOSTS];
27
28 static void ufs_qcom_get_speed_mode(struct ufs_pa_layer_attr *p, char *result);
29 static int ufs_qcom_get_bus_vote(struct ufs_qcom_host *host,
30 const char *speed_mode);
31 static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote);
32
33 static int ufs_qcom_get_connected_tx_lanes(struct ufs_hba *hba, u32 *tx_lanes)
34 {
35 int err = 0;
36
37 err = ufshcd_dme_get(hba,
38 UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), tx_lanes);
39 if (err)
40 dev_err(hba->dev, "%s: couldn't read PA_CONNECTEDTXDATALANES %d\n",
41 __func__, err);
42
43 return err;
44 }
45
46 static int ufs_qcom_host_clk_get(struct device *dev,
47 const char *name, struct clk **clk_out)
48 {
49 struct clk *clk;
50 int err = 0;
51
52 clk = devm_clk_get(dev, name);
53 if (IS_ERR(clk)) {
54 err = PTR_ERR(clk);
55 dev_err(dev, "%s: failed to get %s err %d",
56 __func__, name, err);
57 } else {
58 *clk_out = clk;
59 }
60
61 return err;
62 }
63
64 static int ufs_qcom_host_clk_enable(struct device *dev,
65 const char *name, struct clk *clk)
66 {
67 int err = 0;
68
69 err = clk_prepare_enable(clk);
70 if (err)
71 dev_err(dev, "%s: %s enable failed %d\n", __func__, name, err);
72
73 return err;
74 }
75
76 static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host)
77 {
78 if (!host->is_lane_clks_enabled)
79 return;
80
81 clk_disable_unprepare(host->tx_l1_sync_clk);
82 clk_disable_unprepare(host->tx_l0_sync_clk);
83 clk_disable_unprepare(host->rx_l1_sync_clk);
84 clk_disable_unprepare(host->rx_l0_sync_clk);
85
86 host->is_lane_clks_enabled = false;
87 }
88
89 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
90 {
91 int err = 0;
92 struct device *dev = host->hba->dev;
93
94 if (host->is_lane_clks_enabled)
95 return 0;
96
97 err = ufs_qcom_host_clk_enable(dev, "rx_lane0_sync_clk",
98 host->rx_l0_sync_clk);
99 if (err)
100 goto out;
101
102 err = ufs_qcom_host_clk_enable(dev, "tx_lane0_sync_clk",
103 host->tx_l0_sync_clk);
104 if (err)
105 goto disable_rx_l0;
106
107 err = ufs_qcom_host_clk_enable(dev, "rx_lane1_sync_clk",
108 host->rx_l1_sync_clk);
109 if (err)
110 goto disable_tx_l0;
111
112 err = ufs_qcom_host_clk_enable(dev, "tx_lane1_sync_clk",
113 host->tx_l1_sync_clk);
114 if (err)
115 goto disable_rx_l1;
116
117 host->is_lane_clks_enabled = true;
118 goto out;
119
120 disable_rx_l1:
121 clk_disable_unprepare(host->rx_l1_sync_clk);
122 disable_tx_l0:
123 clk_disable_unprepare(host->tx_l0_sync_clk);
124 disable_rx_l0:
125 clk_disable_unprepare(host->rx_l0_sync_clk);
126 out:
127 return err;
128 }
129
130 static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host)
131 {
132 int err = 0;
133 struct device *dev = host->hba->dev;
134
135 err = ufs_qcom_host_clk_get(dev,
136 "rx_lane0_sync_clk", &host->rx_l0_sync_clk);
137 if (err)
138 goto out;
139
140 err = ufs_qcom_host_clk_get(dev,
141 "tx_lane0_sync_clk", &host->tx_l0_sync_clk);
142 if (err)
143 goto out;
144
145 err = ufs_qcom_host_clk_get(dev, "rx_lane1_sync_clk",
146 &host->rx_l1_sync_clk);
147 if (err)
148 goto out;
149
150 err = ufs_qcom_host_clk_get(dev, "tx_lane1_sync_clk",
151 &host->tx_l1_sync_clk);
152 out:
153 return err;
154 }
155
156 static int ufs_qcom_link_startup_post_change(struct ufs_hba *hba)
157 {
158 struct ufs_qcom_host *host = hba->priv;
159 struct phy *phy = host->generic_phy;
160 u32 tx_lanes;
161 int err = 0;
162
163 err = ufs_qcom_get_connected_tx_lanes(hba, &tx_lanes);
164 if (err)
165 goto out;
166
167 err = ufs_qcom_phy_set_tx_lane_enable(phy, tx_lanes);
168 if (err)
169 dev_err(hba->dev, "%s: ufs_qcom_phy_set_tx_lane_enable failed\n",
170 __func__);
171
172 out:
173 return err;
174 }
175
176 static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
177 {
178 int err;
179 u32 tx_fsm_val = 0;
180 unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS);
181
182 do {
183 err = ufshcd_dme_get(hba,
184 UIC_ARG_MIB(MPHY_TX_FSM_STATE), &tx_fsm_val);
185 if (err || tx_fsm_val == TX_FSM_HIBERN8)
186 break;
187
188 /* sleep for max. 200us */
189 usleep_range(100, 200);
190 } while (time_before(jiffies, timeout));
191
192 /*
193 * we might have scheduled out for long during polling so
194 * check the state again.
195 */
196 if (time_after(jiffies, timeout))
197 err = ufshcd_dme_get(hba,
198 UIC_ARG_MIB(MPHY_TX_FSM_STATE), &tx_fsm_val);
199
200 if (err) {
201 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
202 __func__, err);
203 } else if (tx_fsm_val != TX_FSM_HIBERN8) {
204 err = tx_fsm_val;
205 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n",
206 __func__, err);
207 }
208
209 return err;
210 }
211
212 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
213 {
214 struct ufs_qcom_host *host = hba->priv;
215 struct phy *phy = host->generic_phy;
216 int ret = 0;
217 bool is_rate_B = (UFS_QCOM_LIMIT_HS_RATE == PA_HS_MODE_B)
218 ? true : false;
219
220 /* Assert PHY reset and apply PHY calibration values */
221 ufs_qcom_assert_reset(hba);
222 /* provide 1ms delay to let the reset pulse propagate */
223 usleep_range(1000, 1100);
224
225 ret = ufs_qcom_phy_calibrate_phy(phy, is_rate_B);
226 if (ret) {
227 dev_err(hba->dev, "%s: ufs_qcom_phy_calibrate_phy() failed, ret = %d\n",
228 __func__, ret);
229 goto out;
230 }
231
232 /* De-assert PHY reset and start serdes */
233 ufs_qcom_deassert_reset(hba);
234
235 /*
236 * after reset deassertion, phy will need all ref clocks,
237 * voltage, current to settle down before starting serdes.
238 */
239 usleep_range(1000, 1100);
240 ret = ufs_qcom_phy_start_serdes(phy);
241 if (ret) {
242 dev_err(hba->dev, "%s: ufs_qcom_phy_start_serdes() failed, ret = %d\n",
243 __func__, ret);
244 goto out;
245 }
246
247 ret = ufs_qcom_phy_is_pcs_ready(phy);
248 if (ret)
249 dev_err(hba->dev, "%s: is_physical_coding_sublayer_ready() failed, ret = %d\n",
250 __func__, ret);
251
252 out:
253 return ret;
254 }
255
256 /*
257 * The UTP controller has a number of internal clock gating cells (CGCs).
258 * Internal hardware sub-modules within the UTP controller control the CGCs.
259 * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved
260 * in a specific operation, UTP controller CGCs are by default disabled and
261 * this function enables them (after every UFS link startup) to save some power
262 * leakage.
263 */
264 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba)
265 {
266 ufshcd_writel(hba,
267 ufshcd_readl(hba, REG_UFS_CFG2) | REG_UFS_CFG2_CGC_EN_ALL,
268 REG_UFS_CFG2);
269
270 /* Ensure that HW clock gating is enabled before next operations */
271 mb();
272 }
273
274 static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba, bool status)
275 {
276 struct ufs_qcom_host *host = hba->priv;
277 int err = 0;
278
279 switch (status) {
280 case PRE_CHANGE:
281 ufs_qcom_power_up_sequence(hba);
282 /*
283 * The PHY PLL output is the source of tx/rx lane symbol
284 * clocks, hence, enable the lane clocks only after PHY
285 * is initialized.
286 */
287 err = ufs_qcom_enable_lane_clks(host);
288 break;
289 case POST_CHANGE:
290 /* check if UFS PHY moved from DISABLED to HIBERN8 */
291 err = ufs_qcom_check_hibern8(hba);
292 ufs_qcom_enable_hw_clk_gating(hba);
293
294 break;
295 default:
296 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status);
297 err = -EINVAL;
298 break;
299 }
300 return err;
301 }
302
303 /**
304 * Returns non-zero for success (which rate of core_clk) and 0
305 * in case of a failure
306 */
307 static unsigned long
308 ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear, u32 hs, u32 rate)
309 {
310 struct ufs_qcom_host *host = hba->priv;
311 struct ufs_clk_info *clki;
312 u32 core_clk_period_in_ns;
313 u32 tx_clk_cycles_per_us = 0;
314 unsigned long core_clk_rate = 0;
315 u32 core_clk_cycles_per_us = 0;
316
317 static u32 pwm_fr_table[][2] = {
318 {UFS_PWM_G1, 0x1},
319 {UFS_PWM_G2, 0x1},
320 {UFS_PWM_G3, 0x1},
321 {UFS_PWM_G4, 0x1},
322 };
323
324 static u32 hs_fr_table_rA[][2] = {
325 {UFS_HS_G1, 0x1F},
326 {UFS_HS_G2, 0x3e},
327 };
328
329 static u32 hs_fr_table_rB[][2] = {
330 {UFS_HS_G1, 0x24},
331 {UFS_HS_G2, 0x49},
332 };
333
334 /*
335 * The Qunipro controller does not use following registers:
336 * SYS1CLK_1US_REG, TX_SYMBOL_CLK_1US_REG, CLK_NS_REG &
337 * UFS_REG_PA_LINK_STARTUP_TIMER
338 * But UTP controller uses SYS1CLK_1US_REG register for Interrupt
339 * Aggregation logic.
340 */
341 if (ufs_qcom_cap_qunipro(host) && !ufshcd_is_intr_aggr_allowed(hba))
342 goto out;
343
344 if (gear == 0) {
345 dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear);
346 goto out_error;
347 }
348
349 list_for_each_entry(clki, &hba->clk_list_head, list) {
350 if (!strcmp(clki->name, "core_clk"))
351 core_clk_rate = clk_get_rate(clki->clk);
352 }
353
354 /* If frequency is smaller than 1MHz, set to 1MHz */
355 if (core_clk_rate < DEFAULT_CLK_RATE_HZ)
356 core_clk_rate = DEFAULT_CLK_RATE_HZ;
357
358 core_clk_cycles_per_us = core_clk_rate / USEC_PER_SEC;
359 ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US);
360
361 core_clk_period_in_ns = NSEC_PER_SEC / core_clk_rate;
362 core_clk_period_in_ns <<= OFFSET_CLK_NS_REG;
363 core_clk_period_in_ns &= MASK_CLK_NS_REG;
364
365 switch (hs) {
366 case FASTAUTO_MODE:
367 case FAST_MODE:
368 if (rate == PA_HS_MODE_A) {
369 if (gear > ARRAY_SIZE(hs_fr_table_rA)) {
370 dev_err(hba->dev,
371 "%s: index %d exceeds table size %zu\n",
372 __func__, gear,
373 ARRAY_SIZE(hs_fr_table_rA));
374 goto out_error;
375 }
376 tx_clk_cycles_per_us = hs_fr_table_rA[gear-1][1];
377 } else if (rate == PA_HS_MODE_B) {
378 if (gear > ARRAY_SIZE(hs_fr_table_rB)) {
379 dev_err(hba->dev,
380 "%s: index %d exceeds table size %zu\n",
381 __func__, gear,
382 ARRAY_SIZE(hs_fr_table_rB));
383 goto out_error;
384 }
385 tx_clk_cycles_per_us = hs_fr_table_rB[gear-1][1];
386 } else {
387 dev_err(hba->dev, "%s: invalid rate = %d\n",
388 __func__, rate);
389 goto out_error;
390 }
391 break;
392 case SLOWAUTO_MODE:
393 case SLOW_MODE:
394 if (gear > ARRAY_SIZE(pwm_fr_table)) {
395 dev_err(hba->dev,
396 "%s: index %d exceeds table size %zu\n",
397 __func__, gear,
398 ARRAY_SIZE(pwm_fr_table));
399 goto out_error;
400 }
401 tx_clk_cycles_per_us = pwm_fr_table[gear-1][1];
402 break;
403 case UNCHANGED:
404 default:
405 dev_err(hba->dev, "%s: invalid mode = %d\n", __func__, hs);
406 goto out_error;
407 }
408
409 /* this register 2 fields shall be written at once */
410 ufshcd_writel(hba, core_clk_period_in_ns | tx_clk_cycles_per_us,
411 REG_UFS_TX_SYMBOL_CLK_NS_US);
412 goto out;
413
414 out_error:
415 core_clk_rate = 0;
416 out:
417 return core_clk_rate;
418 }
419
420 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, bool status)
421 {
422 unsigned long core_clk_rate = 0;
423 u32 core_clk_cycles_per_100ms;
424
425 switch (status) {
426 case PRE_CHANGE:
427 core_clk_rate = ufs_qcom_cfg_timers(hba, UFS_PWM_G1,
428 SLOWAUTO_MODE, 0);
429 if (!core_clk_rate) {
430 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
431 __func__);
432 return -EINVAL;
433 }
434 core_clk_cycles_per_100ms =
435 (core_clk_rate / MSEC_PER_SEC) * 100;
436 ufshcd_writel(hba, core_clk_cycles_per_100ms,
437 REG_UFS_PA_LINK_STARTUP_TIMER);
438 break;
439 case POST_CHANGE:
440 ufs_qcom_link_startup_post_change(hba);
441 break;
442 default:
443 break;
444 }
445
446 return 0;
447 }
448
449 static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
450 {
451 struct ufs_qcom_host *host = hba->priv;
452 struct phy *phy = host->generic_phy;
453 int ret = 0;
454
455 if (ufs_qcom_is_link_off(hba)) {
456 /*
457 * Disable the tx/rx lane symbol clocks before PHY is
458 * powered down as the PLL source should be disabled
459 * after downstream clocks are disabled.
460 */
461 ufs_qcom_disable_lane_clks(host);
462 phy_power_off(phy);
463
464 /* Assert PHY soft reset */
465 ufs_qcom_assert_reset(hba);
466 goto out;
467 }
468
469 /*
470 * If UniPro link is not active, PHY ref_clk, main PHY analog power
471 * rail and low noise analog power rail for PLL can be switched off.
472 */
473 if (!ufs_qcom_is_link_active(hba))
474 phy_power_off(phy);
475
476 out:
477 return ret;
478 }
479
480 static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
481 {
482 struct ufs_qcom_host *host = hba->priv;
483 struct phy *phy = host->generic_phy;
484 int err;
485
486 err = phy_power_on(phy);
487 if (err) {
488 dev_err(hba->dev, "%s: failed enabling regs, err = %d\n",
489 __func__, err);
490 goto out;
491 }
492
493 hba->is_sys_suspended = false;
494
495 out:
496 return err;
497 }
498
499 struct ufs_qcom_dev_params {
500 u32 pwm_rx_gear; /* pwm rx gear to work in */
501 u32 pwm_tx_gear; /* pwm tx gear to work in */
502 u32 hs_rx_gear; /* hs rx gear to work in */
503 u32 hs_tx_gear; /* hs tx gear to work in */
504 u32 rx_lanes; /* number of rx lanes */
505 u32 tx_lanes; /* number of tx lanes */
506 u32 rx_pwr_pwm; /* rx pwm working pwr */
507 u32 tx_pwr_pwm; /* tx pwm working pwr */
508 u32 rx_pwr_hs; /* rx hs working pwr */
509 u32 tx_pwr_hs; /* tx hs working pwr */
510 u32 hs_rate; /* rate A/B to work in HS */
511 u32 desired_working_mode;
512 };
513
514 static int ufs_qcom_get_pwr_dev_param(struct ufs_qcom_dev_params *qcom_param,
515 struct ufs_pa_layer_attr *dev_max,
516 struct ufs_pa_layer_attr *agreed_pwr)
517 {
518 int min_qcom_gear;
519 int min_dev_gear;
520 bool is_dev_sup_hs = false;
521 bool is_qcom_max_hs = false;
522
523 if (dev_max->pwr_rx == FAST_MODE)
524 is_dev_sup_hs = true;
525
526 if (qcom_param->desired_working_mode == FAST) {
527 is_qcom_max_hs = true;
528 min_qcom_gear = min_t(u32, qcom_param->hs_rx_gear,
529 qcom_param->hs_tx_gear);
530 } else {
531 min_qcom_gear = min_t(u32, qcom_param->pwm_rx_gear,
532 qcom_param->pwm_tx_gear);
533 }
534
535 /*
536 * device doesn't support HS but qcom_param->desired_working_mode is
537 * HS, thus device and qcom_param don't agree
538 */
539 if (!is_dev_sup_hs && is_qcom_max_hs) {
540 pr_err("%s: failed to agree on power mode (device doesn't support HS but requested power is HS)\n",
541 __func__);
542 return -ENOTSUPP;
543 } else if (is_dev_sup_hs && is_qcom_max_hs) {
544 /*
545 * since device supports HS, it supports FAST_MODE.
546 * since qcom_param->desired_working_mode is also HS
547 * then final decision (FAST/FASTAUTO) is done according
548 * to qcom_params as it is the restricting factor
549 */
550 agreed_pwr->pwr_rx = agreed_pwr->pwr_tx =
551 qcom_param->rx_pwr_hs;
552 } else {
553 /*
554 * here qcom_param->desired_working_mode is PWM.
555 * it doesn't matter whether device supports HS or PWM,
556 * in both cases qcom_param->desired_working_mode will
557 * determine the mode
558 */
559 agreed_pwr->pwr_rx = agreed_pwr->pwr_tx =
560 qcom_param->rx_pwr_pwm;
561 }
562
563 /*
564 * we would like tx to work in the minimum number of lanes
565 * between device capability and vendor preferences.
566 * the same decision will be made for rx
567 */
568 agreed_pwr->lane_tx = min_t(u32, dev_max->lane_tx,
569 qcom_param->tx_lanes);
570 agreed_pwr->lane_rx = min_t(u32, dev_max->lane_rx,
571 qcom_param->rx_lanes);
572
573 /* device maximum gear is the minimum between device rx and tx gears */
574 min_dev_gear = min_t(u32, dev_max->gear_rx, dev_max->gear_tx);
575
576 /*
577 * if both device capabilities and vendor pre-defined preferences are
578 * both HS or both PWM then set the minimum gear to be the chosen
579 * working gear.
580 * if one is PWM and one is HS then the one that is PWM get to decide
581 * what is the gear, as it is the one that also decided previously what
582 * pwr the device will be configured to.
583 */
584 if ((is_dev_sup_hs && is_qcom_max_hs) ||
585 (!is_dev_sup_hs && !is_qcom_max_hs))
586 agreed_pwr->gear_rx = agreed_pwr->gear_tx =
587 min_t(u32, min_dev_gear, min_qcom_gear);
588 else if (!is_dev_sup_hs)
589 agreed_pwr->gear_rx = agreed_pwr->gear_tx = min_dev_gear;
590 else
591 agreed_pwr->gear_rx = agreed_pwr->gear_tx = min_qcom_gear;
592
593 agreed_pwr->hs_rate = qcom_param->hs_rate;
594 return 0;
595 }
596
597 static int ufs_qcom_update_bus_bw_vote(struct ufs_qcom_host *host)
598 {
599 int vote;
600 int err = 0;
601 char mode[BUS_VECTOR_NAME_LEN];
602
603 ufs_qcom_get_speed_mode(&host->dev_req_params, mode);
604
605 vote = ufs_qcom_get_bus_vote(host, mode);
606 if (vote >= 0)
607 err = ufs_qcom_set_bus_vote(host, vote);
608 else
609 err = vote;
610
611 if (err)
612 dev_err(host->hba->dev, "%s: failed %d\n", __func__, err);
613 else
614 host->bus_vote.saved_vote = vote;
615 return err;
616 }
617
618 static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
619 bool status,
620 struct ufs_pa_layer_attr *dev_max_params,
621 struct ufs_pa_layer_attr *dev_req_params)
622 {
623 u32 val;
624 struct ufs_qcom_host *host = hba->priv;
625 struct phy *phy = host->generic_phy;
626 struct ufs_qcom_dev_params ufs_qcom_cap;
627 int ret = 0;
628 int res = 0;
629
630 if (!dev_req_params) {
631 pr_err("%s: incoming dev_req_params is NULL\n", __func__);
632 ret = -EINVAL;
633 goto out;
634 }
635
636 switch (status) {
637 case PRE_CHANGE:
638 ufs_qcom_cap.tx_lanes = UFS_QCOM_LIMIT_NUM_LANES_TX;
639 ufs_qcom_cap.rx_lanes = UFS_QCOM_LIMIT_NUM_LANES_RX;
640 ufs_qcom_cap.hs_rx_gear = UFS_QCOM_LIMIT_HSGEAR_RX;
641 ufs_qcom_cap.hs_tx_gear = UFS_QCOM_LIMIT_HSGEAR_TX;
642 ufs_qcom_cap.pwm_rx_gear = UFS_QCOM_LIMIT_PWMGEAR_RX;
643 ufs_qcom_cap.pwm_tx_gear = UFS_QCOM_LIMIT_PWMGEAR_TX;
644 ufs_qcom_cap.rx_pwr_pwm = UFS_QCOM_LIMIT_RX_PWR_PWM;
645 ufs_qcom_cap.tx_pwr_pwm = UFS_QCOM_LIMIT_TX_PWR_PWM;
646 ufs_qcom_cap.rx_pwr_hs = UFS_QCOM_LIMIT_RX_PWR_HS;
647 ufs_qcom_cap.tx_pwr_hs = UFS_QCOM_LIMIT_TX_PWR_HS;
648 ufs_qcom_cap.hs_rate = UFS_QCOM_LIMIT_HS_RATE;
649 ufs_qcom_cap.desired_working_mode =
650 UFS_QCOM_LIMIT_DESIRED_MODE;
651
652 ret = ufs_qcom_get_pwr_dev_param(&ufs_qcom_cap,
653 dev_max_params,
654 dev_req_params);
655 if (ret) {
656 pr_err("%s: failed to determine capabilities\n",
657 __func__);
658 goto out;
659 }
660
661 break;
662 case POST_CHANGE:
663 if (!ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx,
664 dev_req_params->pwr_rx,
665 dev_req_params->hs_rate)) {
666 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
667 __func__);
668 /*
669 * we return error code at the end of the routine,
670 * but continue to configure UFS_PHY_TX_LANE_ENABLE
671 * and bus voting as usual
672 */
673 ret = -EINVAL;
674 }
675
676 val = ~(MAX_U32 << dev_req_params->lane_tx);
677 res = ufs_qcom_phy_set_tx_lane_enable(phy, val);
678 if (res) {
679 dev_err(hba->dev, "%s: ufs_qcom_phy_set_tx_lane_enable() failed res = %d\n",
680 __func__, res);
681 ret = res;
682 }
683
684 /* cache the power mode parameters to use internally */
685 memcpy(&host->dev_req_params,
686 dev_req_params, sizeof(*dev_req_params));
687 ufs_qcom_update_bus_bw_vote(host);
688 break;
689 default:
690 ret = -EINVAL;
691 break;
692 }
693 out:
694 return ret;
695 }
696
697 static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba)
698 {
699 struct ufs_qcom_host *host = hba->priv;
700
701 if (host->hw_ver.major == 0x1)
702 return UFSHCI_VERSION_11;
703 else
704 return UFSHCI_VERSION_20;
705 }
706
707 /**
708 * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks
709 * @hba: host controller instance
710 *
711 * QCOM UFS host controller might have some non standard behaviours (quirks)
712 * than what is specified by UFSHCI specification. Advertise all such
713 * quirks to standard UFS host controller driver so standard takes them into
714 * account.
715 */
716 static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
717 {
718 struct ufs_qcom_host *host = hba->priv;
719
720 if (host->hw_ver.major == 0x01) {
721 hba->quirks |= UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
722 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP
723 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE;
724
725 if (host->hw_ver.minor == 0x0001 && host->hw_ver.step == 0x0001)
726 hba->quirks |= UFSHCD_QUIRK_BROKEN_INTR_AGGR;
727 }
728
729 if (host->hw_ver.major >= 0x2) {
730 hba->quirks |= UFSHCD_QUIRK_BROKEN_LCC;
731 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION;
732
733 if (!ufs_qcom_cap_qunipro(host))
734 /* Legacy UniPro mode still need following quirks */
735 hba->quirks |= (UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
736 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE
737 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP);
738 }
739 }
740
741 static void ufs_qcom_set_caps(struct ufs_hba *hba)
742 {
743 struct ufs_qcom_host *host = hba->priv;
744
745 if (host->hw_ver.major >= 0x2)
746 host->caps = UFS_QCOM_CAP_QUNIPRO;
747 }
748
749 static int ufs_qcom_get_bus_vote(struct ufs_qcom_host *host,
750 const char *speed_mode)
751 {
752 struct device *dev = host->hba->dev;
753 struct device_node *np = dev->of_node;
754 int err;
755 const char *key = "qcom,bus-vector-names";
756
757 if (!speed_mode) {
758 err = -EINVAL;
759 goto out;
760 }
761
762 if (host->bus_vote.is_max_bw_needed && !!strcmp(speed_mode, "MIN"))
763 err = of_property_match_string(np, key, "MAX");
764 else
765 err = of_property_match_string(np, key, speed_mode);
766
767 out:
768 if (err < 0)
769 dev_err(dev, "%s: Invalid %s mode %d\n",
770 __func__, speed_mode, err);
771 return err;
772 }
773
774 static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote)
775 {
776 int err = 0;
777
778 if (vote != host->bus_vote.curr_vote)
779 host->bus_vote.curr_vote = vote;
780
781 return err;
782 }
783
784 static void ufs_qcom_get_speed_mode(struct ufs_pa_layer_attr *p, char *result)
785 {
786 int gear = max_t(u32, p->gear_rx, p->gear_tx);
787 int lanes = max_t(u32, p->lane_rx, p->lane_tx);
788 int pwr;
789
790 /* default to PWM Gear 1, Lane 1 if power mode is not initialized */
791 if (!gear)
792 gear = 1;
793
794 if (!lanes)
795 lanes = 1;
796
797 if (!p->pwr_rx && !p->pwr_tx) {
798 pwr = SLOWAUTO_MODE;
799 snprintf(result, BUS_VECTOR_NAME_LEN, "MIN");
800 } else if (p->pwr_rx == FAST_MODE || p->pwr_rx == FASTAUTO_MODE ||
801 p->pwr_tx == FAST_MODE || p->pwr_tx == FASTAUTO_MODE) {
802 pwr = FAST_MODE;
803 snprintf(result, BUS_VECTOR_NAME_LEN, "%s_R%s_G%d_L%d", "HS",
804 p->hs_rate == PA_HS_MODE_B ? "B" : "A", gear, lanes);
805 } else {
806 pwr = SLOW_MODE;
807 snprintf(result, BUS_VECTOR_NAME_LEN, "%s_G%d_L%d",
808 "PWM", gear, lanes);
809 }
810 }
811
812 static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on)
813 {
814 struct ufs_qcom_host *host = hba->priv;
815 int err = 0;
816 int vote = 0;
817
818 /*
819 * In case ufs_qcom_init() is not yet done, simply ignore.
820 * This ufs_qcom_setup_clocks() shall be called from
821 * ufs_qcom_init() after init is done.
822 */
823 if (!host)
824 return 0;
825
826 if (on) {
827 err = ufs_qcom_phy_enable_iface_clk(host->generic_phy);
828 if (err)
829 goto out;
830
831 err = ufs_qcom_phy_enable_ref_clk(host->generic_phy);
832 if (err) {
833 dev_err(hba->dev, "%s enable phy ref clock failed, err=%d\n",
834 __func__, err);
835 ufs_qcom_phy_disable_iface_clk(host->generic_phy);
836 goto out;
837 }
838 /* enable the device ref clock */
839 ufs_qcom_phy_enable_dev_ref_clk(host->generic_phy);
840 vote = host->bus_vote.saved_vote;
841 if (vote == host->bus_vote.min_bw_vote)
842 ufs_qcom_update_bus_bw_vote(host);
843 } else {
844 /* M-PHY RMMI interface clocks can be turned off */
845 ufs_qcom_phy_disable_iface_clk(host->generic_phy);
846 if (!ufs_qcom_is_link_active(hba)) {
847 /* turn off UFS local PHY ref_clk */
848 ufs_qcom_phy_disable_ref_clk(host->generic_phy);
849 /* disable device ref_clk */
850 ufs_qcom_phy_disable_dev_ref_clk(host->generic_phy);
851 }
852 vote = host->bus_vote.min_bw_vote;
853 }
854
855 err = ufs_qcom_set_bus_vote(host, vote);
856 if (err)
857 dev_err(hba->dev, "%s: set bus vote failed %d\n",
858 __func__, err);
859
860 out:
861 return err;
862 }
863
864 static ssize_t
865 show_ufs_to_mem_max_bus_bw(struct device *dev, struct device_attribute *attr,
866 char *buf)
867 {
868 struct ufs_hba *hba = dev_get_drvdata(dev);
869 struct ufs_qcom_host *host = hba->priv;
870
871 return snprintf(buf, PAGE_SIZE, "%u\n",
872 host->bus_vote.is_max_bw_needed);
873 }
874
875 static ssize_t
876 store_ufs_to_mem_max_bus_bw(struct device *dev, struct device_attribute *attr,
877 const char *buf, size_t count)
878 {
879 struct ufs_hba *hba = dev_get_drvdata(dev);
880 struct ufs_qcom_host *host = hba->priv;
881 uint32_t value;
882
883 if (!kstrtou32(buf, 0, &value)) {
884 host->bus_vote.is_max_bw_needed = !!value;
885 ufs_qcom_update_bus_bw_vote(host);
886 }
887
888 return count;
889 }
890
891 static int ufs_qcom_bus_register(struct ufs_qcom_host *host)
892 {
893 int err;
894 struct device *dev = host->hba->dev;
895 struct device_node *np = dev->of_node;
896
897 err = of_property_count_strings(np, "qcom,bus-vector-names");
898 if (err < 0 ) {
899 dev_err(dev, "%s: qcom,bus-vector-names not specified correctly %d\n",
900 __func__, err);
901 goto out;
902 }
903
904 /* cache the vote index for minimum and maximum bandwidth */
905 host->bus_vote.min_bw_vote = ufs_qcom_get_bus_vote(host, "MIN");
906 host->bus_vote.max_bw_vote = ufs_qcom_get_bus_vote(host, "MAX");
907
908 host->bus_vote.max_bus_bw.show = show_ufs_to_mem_max_bus_bw;
909 host->bus_vote.max_bus_bw.store = store_ufs_to_mem_max_bus_bw;
910 sysfs_attr_init(&host->bus_vote.max_bus_bw.attr);
911 host->bus_vote.max_bus_bw.attr.name = "max_bus_bw";
912 host->bus_vote.max_bus_bw.attr.mode = S_IRUGO | S_IWUSR;
913 err = device_create_file(dev, &host->bus_vote.max_bus_bw);
914 out:
915 return err;
916 }
917
918 #define ANDROID_BOOT_DEV_MAX 30
919 static char android_boot_dev[ANDROID_BOOT_DEV_MAX];
920 static int get_android_boot_dev(char *str)
921 {
922 strlcpy(android_boot_dev, str, ANDROID_BOOT_DEV_MAX);
923 return 1;
924 }
925 __setup("androidboot.bootdevice=", get_android_boot_dev);
926
927 /**
928 * ufs_qcom_init - bind phy with controller
929 * @hba: host controller instance
930 *
931 * Binds PHY with controller and powers up PHY enabling clocks
932 * and regulators.
933 *
934 * Returns -EPROBE_DEFER if binding fails, returns negative error
935 * on phy power up failure and returns zero on success.
936 */
937 static int ufs_qcom_init(struct ufs_hba *hba)
938 {
939 int err;
940 struct device *dev = hba->dev;
941 struct ufs_qcom_host *host;
942
943 if (strlen(android_boot_dev) && strcmp(android_boot_dev, dev_name(dev)))
944 return -ENODEV;
945
946 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
947 if (!host) {
948 err = -ENOMEM;
949 dev_err(dev, "%s: no memory for qcom ufs host\n", __func__);
950 goto out;
951 }
952
953 host->hba = hba;
954 hba->priv = (void *)host;
955
956 host->generic_phy = devm_phy_get(dev, "ufsphy");
957
958 if (IS_ERR(host->generic_phy)) {
959 err = PTR_ERR(host->generic_phy);
960 dev_err(dev, "%s: PHY get failed %d\n", __func__, err);
961 goto out;
962 }
963
964 err = ufs_qcom_bus_register(host);
965 if (err)
966 goto out_host_free;
967
968 ufs_qcom_get_controller_revision(hba, &host->hw_ver.major,
969 &host->hw_ver.minor, &host->hw_ver.step);
970
971 /* update phy revision information before calling phy_init() */
972 ufs_qcom_phy_save_controller_version(host->generic_phy,
973 host->hw_ver.major, host->hw_ver.minor, host->hw_ver.step);
974
975 phy_init(host->generic_phy);
976 err = phy_power_on(host->generic_phy);
977 if (err)
978 goto out_unregister_bus;
979
980 err = ufs_qcom_init_lane_clks(host);
981 if (err)
982 goto out_disable_phy;
983
984 ufs_qcom_set_caps(hba);
985 ufs_qcom_advertise_quirks(hba);
986
987 hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_CLK_SCALING;
988 hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
989
990 ufs_qcom_setup_clocks(hba, true);
991
992 if (hba->dev->id < MAX_UFS_QCOM_HOSTS)
993 ufs_qcom_hosts[hba->dev->id] = host;
994
995 goto out;
996
997 out_disable_phy:
998 phy_power_off(host->generic_phy);
999 out_unregister_bus:
1000 phy_exit(host->generic_phy);
1001 out_host_free:
1002 devm_kfree(dev, host);
1003 hba->priv = NULL;
1004 out:
1005 return err;
1006 }
1007
1008 static void ufs_qcom_exit(struct ufs_hba *hba)
1009 {
1010 struct ufs_qcom_host *host = hba->priv;
1011
1012 ufs_qcom_disable_lane_clks(host);
1013 phy_power_off(host->generic_phy);
1014 }
1015
1016 static
1017 void ufs_qcom_clk_scale_notify(struct ufs_hba *hba)
1018 {
1019 struct ufs_qcom_host *host = hba->priv;
1020 struct ufs_pa_layer_attr *dev_req_params = &host->dev_req_params;
1021
1022 if (!dev_req_params)
1023 return;
1024
1025 ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx,
1026 dev_req_params->pwr_rx,
1027 dev_req_params->hs_rate);
1028 }
1029
1030 /**
1031 * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations
1032 *
1033 * The variant operations configure the necessary controller and PHY
1034 * handshake during initialization.
1035 */
1036 static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = {
1037 .name = "qcom",
1038 .init = ufs_qcom_init,
1039 .exit = ufs_qcom_exit,
1040 .get_ufs_hci_version = ufs_qcom_get_ufs_hci_version,
1041 .clk_scale_notify = ufs_qcom_clk_scale_notify,
1042 .setup_clocks = ufs_qcom_setup_clocks,
1043 .hce_enable_notify = ufs_qcom_hce_enable_notify,
1044 .link_startup_notify = ufs_qcom_link_startup_notify,
1045 .pwr_change_notify = ufs_qcom_pwr_change_notify,
1046 .suspend = ufs_qcom_suspend,
1047 .resume = ufs_qcom_resume,
1048 };
1049 EXPORT_SYMBOL(ufs_hba_qcom_vops);
Linux with added FPC-III support