drivers/tty/serial/8250/8250_ingenic.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2010 Lars-Peter Clausen <lars@metafoo.de>
   4  * Copyright (C) 2015 Imagination Technologies
   5  *
   6  * Ingenic SoC UART support
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/console.h>
  11 #include <linux/io.h>
  12 #include <linux/libfdt.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/of_fdt.h>
  16 #include <linux/of_device.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/serial_8250.h>
  19 #include <linux/serial_core.h>
  20 #include <linux/serial_reg.h>
  21
  22 #include "8250.h"
  23
  24 /** ingenic_uart_config: SOC specific config data. */
  25 struct ingenic_uart_config {
  26         int tx_loadsz;
  27         int fifosize;
  28 };
  29
  30 struct ingenic_uart_data {
  31         struct clk      *clk_module;
  32         struct clk      *clk_baud;
  33         int             line;
  34 };
  35
  36 static const struct of_device_id of_match[];
  37
  38 #define UART_FCR_UME    BIT(4)
  39
  40 #define UART_MCR_MDCE   BIT(7)
  41 #define UART_MCR_FCM    BIT(6)
  42
  43 static struct earlycon_device *early_device;
  44
  45 static uint8_t early_in(struct uart_port *port, int offset)
  46 {
  47         return readl(port->membase + (offset << 2));
  48 }
  49
  50 static void early_out(struct uart_port *port, int offset, uint8_t value)
  51 {
  52         writel(value, port->membase + (offset << 2));
  53 }
  54
  55 static void ingenic_early_console_putc(struct uart_port *port, int c)
  56 {
  57         uint8_t lsr;
  58
  59         do {
  60                 lsr = early_in(port, UART_LSR);
  61         } while ((lsr & UART_LSR_TEMT) == 0);
  62
  63         early_out(port, UART_TX, c);
  64 }
  65
  66 static void ingenic_early_console_write(struct console *console,
  67                                               const char *s, unsigned int count)
  68 {
  69         uart_console_write(&early_device->port, s, count,
  70                            ingenic_early_console_putc);
  71 }
  72
  73 static void __init ingenic_early_console_setup_clock(struct earlycon_device *dev)
  74 {
  75         void *fdt = initial_boot_params;
  76         const __be32 *prop;
  77         int offset;
  78
  79         offset = fdt_path_offset(fdt, "/ext");
  80         if (offset < 0)
  81                 return;
  82
  83         prop = fdt_getprop(fdt, offset, "clock-frequency", NULL);
  84         if (!prop)
  85                 return;
  86
  87         dev->port.uartclk = be32_to_cpup(prop);
  88 }
  89
  90 static int __init ingenic_early_console_setup(struct earlycon_device *dev,
  91                                               const char *opt)
  92 {
  93         struct uart_port *port = &dev->port;
  94         unsigned int divisor;
  95         int baud = 115200;
  96
  97         if (!dev->port.membase)
  98                 return -ENODEV;
  99
 100         if (opt) {
 101                 unsigned int parity, bits, flow; /* unused for now */
 102
 103                 uart_parse_options(opt, &baud, &parity, &bits, &flow);
 104         }
 105
 106         ingenic_early_console_setup_clock(dev);
 107
 108         if (dev->baud)
 109                 baud = dev->baud;
 110         divisor = DIV_ROUND_CLOSEST(port->uartclk, 16 * baud);
 111
 112         early_out(port, UART_IER, 0);
 113         early_out(port, UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN8);
 114         early_out(port, UART_DLL, 0);
 115         early_out(port, UART_DLM, 0);
 116         early_out(port, UART_LCR, UART_LCR_WLEN8);
 117         early_out(port, UART_FCR, UART_FCR_UME | UART_FCR_CLEAR_XMIT |
 118                         UART_FCR_CLEAR_RCVR | UART_FCR_ENABLE_FIFO);
 119         early_out(port, UART_MCR, UART_MCR_RTS | UART_MCR_DTR);
 120
 121         early_out(port, UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN8);
 122         early_out(port, UART_DLL, divisor & 0xff);
 123         early_out(port, UART_DLM, (divisor >> 8) & 0xff);
 124         early_out(port, UART_LCR, UART_LCR_WLEN8);
 125
 126         early_device = dev;
 127         dev->con->write = ingenic_early_console_write;
 128
 129         return 0;
 130 }
 131
 132 OF_EARLYCON_DECLARE(jz4740_uart, "ingenic,jz4740-uart",
 133                     ingenic_early_console_setup);
 134
 135 OF_EARLYCON_DECLARE(jz4770_uart, "ingenic,jz4770-uart",
 136                     ingenic_early_console_setup);
 137
 138 OF_EARLYCON_DECLARE(jz4775_uart, "ingenic,jz4775-uart",
 139                     ingenic_early_console_setup);
 140
 141 OF_EARLYCON_DECLARE(jz4780_uart, "ingenic,jz4780-uart",
 142                     ingenic_early_console_setup);
 143
 144 OF_EARLYCON_DECLARE(x1000_uart, "ingenic,x1000-uart",
 145                     ingenic_early_console_setup);
 146
 147 static void ingenic_uart_serial_out(struct uart_port *p, int offset, int value)
 148 {
 149         int ier;
 150
 151         switch (offset) {
 152         case UART_FCR:
 153                 /* UART module enable */
 154                 value |= UART_FCR_UME;
 155                 break;
 156
 157         case UART_IER:
 158                 /*
 159                  * Enable receive timeout interrupt with the receive line
 160                  * status interrupt.
 161                  */
 162                 value |= (value & 0x4) << 2;
 163                 break;
 164
 165         case UART_MCR:
 166                 /*
 167                  * If we have enabled modem status IRQs we should enable
 168                  * modem mode.
 169                  */
 170                 ier = p->serial_in(p, UART_IER);
 171
 172                 if (ier & UART_IER_MSI)
 173                         value |= UART_MCR_MDCE | UART_MCR_FCM;
 174                 else
 175                         value &= ~(UART_MCR_MDCE | UART_MCR_FCM);
 176                 break;
 177
 178         default:
 179                 break;
 180         }
 181
 182         writeb(value, p->membase + (offset << p->regshift));
 183 }
 184
 185 static unsigned int ingenic_uart_serial_in(struct uart_port *p, int offset)
 186 {
 187         unsigned int value;
 188
 189         value = readb(p->membase + (offset << p->regshift));
 190
 191         /* Hide non-16550 compliant bits from higher levels */
 192         switch (offset) {
 193         case UART_FCR:
 194                 value &= ~UART_FCR_UME;
 195                 break;
 196
 197         case UART_MCR:
 198                 value &= ~(UART_MCR_MDCE | UART_MCR_FCM);
 199                 break;
 200
 201         default:
 202                 break;
 203         }
 204         return value;
 205 }
 206
 207 static int ingenic_uart_probe(struct platform_device *pdev)
 208 {
 209         struct uart_8250_port uart = {};
 210         struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 211         struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 212         struct ingenic_uart_data *data;
 213         const struct ingenic_uart_config *cdata;
 214         const struct of_device_id *match;
 215         int err, line;
 216
 217         match = of_match_device(of_match, &pdev->dev);
 218         if (!match) {
 219                 dev_err(&pdev->dev, "Error: No device match found\n");
 220                 return -ENODEV;
 221         }
 222         cdata = match->data;
 223
 224         if (!regs || !irq) {
 225                 dev_err(&pdev->dev, "no registers/irq defined\n");
 226                 return -EINVAL;
 227         }
 228
 229         data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
 230         if (!data)
 231                 return -ENOMEM;
 232
 233         spin_lock_init(&uart.port.lock);
 234         uart.port.type = PORT_16550A;
 235         uart.port.flags = UPF_SKIP_TEST | UPF_IOREMAP | UPF_FIXED_TYPE;
 236         uart.port.iotype = UPIO_MEM;
 237         uart.port.mapbase = regs->start;
 238         uart.port.regshift = 2;
 239         uart.port.serial_out = ingenic_uart_serial_out;
 240         uart.port.serial_in = ingenic_uart_serial_in;
 241         uart.port.irq = irq->start;
 242         uart.port.dev = &pdev->dev;
 243         uart.port.fifosize = cdata->fifosize;
 244         uart.tx_loadsz = cdata->tx_loadsz;
 245         uart.capabilities = UART_CAP_FIFO | UART_CAP_RTOIE;
 246
 247         /* Check for a fixed line number */
 248         line = of_alias_get_id(pdev->dev.of_node, "serial");
 249         if (line >= 0)
 250                 uart.port.line = line;
 251
 252         uart.port.membase = devm_ioremap(&pdev->dev, regs->start,
 253                                          resource_size(regs));
 254         if (!uart.port.membase)
 255                 return -ENOMEM;
 256
 257         data->clk_module = devm_clk_get(&pdev->dev, "module");
 258         if (IS_ERR(data->clk_module)) {
 259                 err = PTR_ERR(data->clk_module);
 260                 if (err != -EPROBE_DEFER)
 261                         dev_err(&pdev->dev,
 262                                 "unable to get module clock: %d\n", err);
 263                 return err;
 264         }
 265
 266         data->clk_baud = devm_clk_get(&pdev->dev, "baud");
 267         if (IS_ERR(data->clk_baud)) {
 268                 err = PTR_ERR(data->clk_baud);
 269                 if (err != -EPROBE_DEFER)
 270                         dev_err(&pdev->dev,
 271                                 "unable to get baud clock: %d\n", err);
 272                 return err;
 273         }
 274
 275         err = clk_prepare_enable(data->clk_module);
 276         if (err) {
 277                 dev_err(&pdev->dev, "could not enable module clock: %d\n", err);
 278                 goto out;
 279         }
 280
 281         err = clk_prepare_enable(data->clk_baud);
 282         if (err) {
 283                 dev_err(&pdev->dev, "could not enable baud clock: %d\n", err);
 284                 goto out_disable_moduleclk;
 285         }
 286         uart.port.uartclk = clk_get_rate(data->clk_baud);
 287
 288         data->line = serial8250_register_8250_port(&uart);
 289         if (data->line < 0) {
 290                 err = data->line;
 291                 goto out_disable_baudclk;
 292         }
 293
 294         platform_set_drvdata(pdev, data);
 295         return 0;
 296
 297 out_disable_baudclk:
 298         clk_disable_unprepare(data->clk_baud);
 299 out_disable_moduleclk:
 300         clk_disable_unprepare(data->clk_module);
 301 out:
 302         return err;
 303 }
 304
 305 static int ingenic_uart_remove(struct platform_device *pdev)
 306 {
 307         struct ingenic_uart_data *data = platform_get_drvdata(pdev);
 308
 309         serial8250_unregister_port(data->line);
 310         clk_disable_unprepare(data->clk_module);
 311         clk_disable_unprepare(data->clk_baud);
 312         return 0;
 313 }
 314
 315 static const struct ingenic_uart_config jz4740_uart_config = {
 316         .tx_loadsz = 8,
 317         .fifosize = 16,
 318 };
 319
 320 static const struct ingenic_uart_config jz4760_uart_config = {
 321         .tx_loadsz = 16,
 322         .fifosize = 32,
 323 };
 324
 325 static const struct ingenic_uart_config jz4780_uart_config = {
 326         .tx_loadsz = 32,
 327         .fifosize = 64,
 328 };
 329
 330 static const struct ingenic_uart_config x1000_uart_config = {
 331         .tx_loadsz = 32,
 332         .fifosize = 64,
 333 };
 334
 335 static const struct of_device_id of_match[] = {
 336         { .compatible = "ingenic,jz4740-uart", .data = &jz4740_uart_config },
 337         { .compatible = "ingenic,jz4760-uart", .data = &jz4760_uart_config },
 338         { .compatible = "ingenic,jz4770-uart", .data = &jz4760_uart_config },
 339         { .compatible = "ingenic,jz4775-uart", .data = &jz4760_uart_config },
 340         { .compatible = "ingenic,jz4780-uart", .data = &jz4780_uart_config },
 341         { .compatible = "ingenic,x1000-uart", .data = &x1000_uart_config },
 342         { /* sentinel */ }
 343 };
 344 MODULE_DEVICE_TABLE(of, of_match);
 345
 346 static struct platform_driver ingenic_uart_platform_driver = {
 347         .driver = {
 348                 .name           = "ingenic-uart",
 349                 .of_match_table = of_match,
 350         },
 351         .probe                  = ingenic_uart_probe,
 352         .remove                 = ingenic_uart_remove,
 353 };
 354
 355 module_platform_driver(ingenic_uart_platform_driver);
 356
 357 MODULE_AUTHOR("Paul Burton");
 358 MODULE_LICENSE("GPL");
 359 MODULE_DESCRIPTION("Ingenic SoC UART driver");