| blob | 0a854a47d31a77ef0723231dd75e3aceddc5d6b0 |
1 /* Intel PRO/1000 Linux driver
2 * Copyright(c) 1999 - 2015 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
15 *
16 * Contact Information:
17 * Linux NICS <linux.nics@intel.com>
18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
20 */
24 #include <linux/module.h>
25 #include <linux/types.h>
26 #include <linux/init.h>
27 #include <linux/pci.h>
28 #include <linux/vmalloc.h>
29 #include <linux/pagemap.h>
30 #include <linux/delay.h>
31 #include <linux/netdevice.h>
32 #include <linux/interrupt.h>
33 #include <linux/tcp.h>
34 #include <linux/ipv6.h>
35 #include <linux/slab.h>
36 #include <net/checksum.h>
37 #include <net/ip6_checksum.h>
38 #include <linux/ethtool.h>
39 #include <linux/if_vlan.h>
40 #include <linux/cpu.h>
41 #include <linux/smp.h>
42 #include <linux/pm_qos.h>
43 #include <linux/pm_runtime.h>
44 #include <linux/aer.h>
45 #include <linux/prefetch.h>
55 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
74 };
77 u32 ofs;
79 };
82 /* General Registers */
87 /* Interrupt Registers */
90 /* Rx Registers */
106 /* Tx Registers */
123 /* List Terminator */
125 };
127 /**
128 * __ew32_prepare - prepare to write to MAC CSR register on certain parts
129 * @hw: pointer to the HW structure
130 *
131 * When updating the MAC CSR registers, the Manageability Engine (ME) could
132 * be accessing the registers at the same time. Normally, this is handled in
133 * h/w by an arbiter but on some parts there is a bug that acknowledges Host
134 * accesses later than it should which could result in the register to have
135 * an incorrect value. Workaround this by checking the FWSM register which
136 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set
137 * and try again a number of times.
138 **/
140 {
147 }
150 {
155 }
157 /**
158 * e1000_regdump - register printout routine
159 * @hw: pointer to the HW structure
160 * @reginfo: pointer to the register info table
161 **/
163 {
185 }
189 }
193 {
205 }
206 }
207 }
209 /**
210 * e1000e_dump - Print registers, Tx-ring and Rx-ring
211 * @adapter: board private structure
212 **/
214 {
221 __le64 a;
222 __le64 b;
229 __le64 a;
230 __le64 b;
231 __le64 c;
232 __le64 d;
234 u32 staterr;
240 /* Print netdevice Info */
246 }
248 /* Print Registers */
254 }
256 /* Print Tx Ring Summary */
270 /* Print Tx Ring */
276 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
277 *
278 * Legacy Transmit Descriptor
279 * +--------------------------------------------------------------+
280 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
281 * +--------------------------------------------------------------+
282 * 8 | Special | CSS | Status | CMD | CSO | Length |
283 * +--------------------------------------------------------------+
284 * 63 48 47 36 35 32 31 24 23 16 15 0
285 *
286 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
287 * 63 48 47 40 39 32 31 16 15 8 7 0
288 * +----------------------------------------------------------------+
289 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
290 * +----------------------------------------------------------------+
291 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
292 * +----------------------------------------------------------------+
293 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
294 *
295 * Extended Data Descriptor (DTYP=0x1)
296 * +----------------------------------------------------------------+
297 * 0 | Buffer Address [63:0] |
298 * +----------------------------------------------------------------+
299 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
300 * +----------------------------------------------------------------+
301 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
302 */
303 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
304 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
305 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
317 else
322 i,
334 }
336 /* Print Rx Ring Summary */
337 rx_ring_summary:
343 /* Print Rx Ring */
352 /* [Extended] Packet Split Receive Descriptor Format
353 *
354 * +-----------------------------------------------------+
355 * 0 | Buffer Address 0 [63:0] |
356 * +-----------------------------------------------------+
357 * 8 | Buffer Address 1 [63:0] |
358 * +-----------------------------------------------------+
359 * 16 | Buffer Address 2 [63:0] |
360 * +-----------------------------------------------------+
361 * 24 | Buffer Address 3 [63:0] |
362 * +-----------------------------------------------------+
363 */
364 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
365 /* [Extended] Receive Descriptor (Write-Back) Format
366 *
367 * 63 48 47 32 31 13 12 8 7 4 3 0
368 * +------------------------------------------------------+
369 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
370 * | Checksum | Ident | | Queue | | Type |
371 * +------------------------------------------------------+
372 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
373 * +------------------------------------------------------+
374 * 63 48 47 32 31 20 19 0
375 */
376 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
382 staterr =
389 else
393 /* Descriptor Done */
413 buffer_info);
414 }
415 }
419 /* Extended Receive Descriptor (Read) Format
420 *
421 * +-----------------------------------------------------+
422 * 0 | Buffer Address [63:0] |
423 * +-----------------------------------------------------+
424 * 8 | Reserved |
425 * +-----------------------------------------------------+
426 */
427 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
428 /* Extended Receive Descriptor (Write-Back) Format
429 *
430 * 63 48 47 32 31 24 23 4 3 0
431 * +------------------------------------------------------+
432 * | RSS Hash | | | |
433 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
434 * | Packet | IP | | | Type |
435 * | Checksum | Ident | | | |
436 * +------------------------------------------------------+
437 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
438 * +------------------------------------------------------+
439 * 63 48 47 32 31 20 19 0
440 */
455 else
459 /* Descriptor Done */
481 }
482 }
483 }
484 }
486 /**
487 * e1000_desc_unused - calculate if we have unused descriptors
488 **/
490 {
495 }
497 /**
498 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp
499 * @adapter: board private structure
500 * @hwtstamps: time stamp structure to update
501 * @systim: unsigned 64bit system time value.
502 *
503 * Convert the system time value stored in the RX/TXSTMP registers into a
504 * hwtstamp which can be used by the upper level time stamping functions.
505 *
506 * The 'systim_lock' spinlock is used to protect the consistency of the
507 * system time value. This is needed because reading the 64 bit time
508 * value involves reading two 32 bit registers. The first read latches the
509 * value.
510 **/
513 u64 systim)
514 {
515 u64 ns;
524 }
526 /**
527 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp
528 * @adapter: board private structure
529 * @status: descriptor extended error and status field
530 * @skb: particular skb to include time stamp
531 *
532 * If the time stamp is valid, convert it into the timecounter ns value
533 * and store that result into the shhwtstamps structure which is passed
534 * up the network stack.
535 **/
538 {
540 u64 rxstmp;
547 /* The Rx time stamp registers contain the time stamp. No other
548 * received packet will be time stamped until the Rx time stamp
549 * registers are read. Because only one packet can be time stamped
550 * at a time, the register values must belong to this packet and
551 * therefore none of the other additional attributes need to be
552 * compared.
553 */
559 }
561 /**
562 * e1000_receive_skb - helper function to handle Rx indications
563 * @adapter: board private structure
564 * @staterr: descriptor extended error and status field as written by hardware
565 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
566 * @skb: pointer to sk_buff to be indicated to stack
567 **/
571 {
582 }
584 /**
585 * e1000_rx_checksum - Receive Checksum Offload
586 * @adapter: board private structure
587 * @status_err: receive descriptor status and error fields
588 * @csum: receive descriptor csum field
589 * @sk_buff: socket buffer with received data
590 **/
593 {
599 /* Rx checksum disabled */
603 /* Ignore Checksum bit is set */
607 /* TCP/UDP checksum error bit or IP checksum error bit is set */
609 /* let the stack verify checksum errors */
612 }
614 /* TCP/UDP Checksum has not been calculated */
618 /* It must be a TCP or UDP packet with a valid checksum */
621 }
624 {
637 }
638 }
641 {
654 }
655 }
657 /**
658 * e1000_alloc_rx_buffers - Replace used receive buffers
659 * @rx_ring: Rx descriptor ring
660 **/
663 {
681 }
685 /* Better luck next round */
688 }
691 map_skb:
694 DMA_FROM_DEVICE);
699 }
705 /* Force memory writes to complete before letting h/w
706 * know there are new descriptors to fetch. (Only
707 * applicable for weak-ordered memory model archs,
708 * such as IA-64).
709 */
713 else
715 }
716 i++;
720 }
723 }
725 /**
726 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
727 * @rx_ring: Rx descriptor ring
728 **/
731 {
750 /* all unused desc entries get hw null ptr */
754 }
760 }
764 DMA_FROM_DEVICE);
771 }
772 }
773 /* Refresh the desc even if buffer_addrs
774 * didn't change because each write-back
775 * erases this info.
776 */
779 }
782 gfp);
787 }
792 DMA_FROM_DEVICE);
796 /* cleanup skb */
800 }
805 /* Force memory writes to complete before letting h/w
806 * know there are new descriptors to fetch. (Only
807 * applicable for weak-ordered memory model archs,
808 * such as IA-64).
809 */
813 else
815 }
817 i++;
821 }
823 no_buffers:
825 }
827 /**
828 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
829 * @rx_ring: Rx descriptor ring
830 * @cleaned_count: number of buffers to allocate this pass
831 **/
835 {
853 }
857 /* Better luck next round */
860 }
863 check_page:
864 /* allocate a new page if necessary */
870 }
871 }
876 PAGE_SIZE,
877 DMA_FROM_DEVICE);
881 }
882 }
890 }
897 /* Force memory writes to complete before letting h/w
898 * know there are new descriptors to fetch. (Only
899 * applicable for weak-ordered memory model archs,
900 * such as IA-64).
901 */
905 else
907 }
908 }
912 {
915 }
917 /**
918 * e1000_clean_rx_irq - Send received data up the network stack
919 * @rx_ring: Rx descriptor ring
920 *
921 * the return value indicates whether actual cleaning was done, there
922 * is no guarantee that everything was cleaned
923 **/
926 {
957 i++;
966 cleaned_count++;
973 /* !EOP means multiple descriptors were used to store a single
974 * packet, if that's the case we need to toss it. In fact, we
975 * need to toss every packet with the EOP bit clear and the
976 * next frame that _does_ have the EOP bit set, as it is by
977 * definition only a frame fragment
978 */
983 /* All receives must fit into a single buffer */
985 /* recycle */
990 }
994 /* recycle */
997 }
999 /* adjust length to remove Ethernet CRC */
1001 /* If configured to store CRC, don't subtract FCS,
1002 * but keep the FCS bytes out of the total_rx_bytes
1003 * counter
1004 */
1007 else
1009 }
1012 total_rx_packets++;
1014 /* code added for copybreak, this should improve
1015 * performance for small packets with large amounts
1016 * of reassembly being done in the stack
1017 */
1025 NET_IP_ALIGN),
1027 NET_IP_ALIGN));
1028 /* save the skb in buffer_info as good */
1031 }
1032 /* else just continue with the old one */
1033 }
1034 /* end copybreak code */
1037 /* Receive Checksum Offload */
1045 next_desc:
1048 /* return some buffers to hardware, one at a time is too slow */
1051 GFP_ATOMIC);
1053 }
1055 /* use prefetched values */
1060 }
1070 }
1074 {
1081 else
1085 }
1089 }
1091 }
1094 {
1097 print_hang_task);
1105 u16 pci_status;
1111 /* May be block on write-back, flush and detect again
1112 * flush pending descriptor writebacks to memory
1113 */
1115 /* execute the writes immediately */
1117 /* Due to rare timing issues, write to TIDV again to ensure
1118 * the write is successful
1119 */
1121 /* execute the writes immediately */
1125 }
1131 }
1133 /* Real hang detected */
1142 /* detected Hardware unit hang */
1165 /* Suggest workaround for known h/w issue */
1168 }
1170 /**
1171 * e1000e_tx_hwtstamp_work - check for Tx time stamp
1172 * @work: pointer to work struct
1173 *
1174 * This work function polls the TSYNCTXCTL valid bit to determine when a
1175 * timestamp has been taken for the current stored skb. The timestamp must
1176 * be for this skb because only one such packet is allowed in the queue.
1177 */
1179 {
1181 tx_hwtstamp_work);
1186 u64 txstmp;
1203 /* reschedule to check later */
1205 }
1206 }
1208 /**
1209 * e1000_clean_tx_irq - Reclaim resources after transmit completes
1210 * @tx_ring: Tx descriptor ring
1211 *
1212 * the return value indicates whether actual cleaning was done, there
1213 * is no guarantee that everything was cleaned
1214 **/
1216 {
1246 pkts_compl++;
1247 }
1248 }
1253 i++;
1256 }
1262 }
1268 #define TX_WAKE_THRESHOLD 32
1271 /* Make sure that anybody stopping the queue after this
1272 * sees the new next_to_clean.
1273 */
1280 }
1281 }
1284 /* Detect a transmit hang in hardware, this serializes the
1285 * check with the clearing of time_stamp and movement of i
1286 */
1293 else
1295 }
1299 }
1301 /**
1302 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
1303 * @rx_ring: Rx descriptor ring
1304 *
1305 * the return value indicates whether actual cleaning was done, there
1306 * is no guarantee that everything was cleaned
1307 **/
1310 {
1337 /* in the packet split case this is header only */
1340 i++;
1349 cleaned_count++;
1354 /* see !EOP comment in other Rx routine */
1364 }
1370 }
1378 }
1380 /* Good Receive */
1383 {
1384 /* this looks ugly, but it seems compiler issues make
1385 * it more efficient than reusing j
1386 */
1389 /* page alloc/put takes too long and effects small
1390 * packet throughput, so unsplit small packets and
1391 * save the alloc/put only valid in softirq (napi)
1392 * context to call kmap_*
1393 */
1400 /* there is no documentation about how to call
1401 * kmap_atomic, so we can't hold the mapping
1402 * very long
1403 */
1406 PAGE_SIZE,
1407 DMA_FROM_DEVICE);
1413 PAGE_SIZE,
1414 DMA_FROM_DEVICE);
1416 /* remove the CRC */
1420 }
1425 }
1434 DMA_FROM_DEVICE);
1441 }
1443 /* strip the ethernet crc, problem is we're using pages now so
1444 * this whole operation can get a little cpu intensive
1445 */
1449 }
1451 copydone:
1453 total_rx_packets++;
1466 next_desc:
1470 /* return some buffers to hardware, one at a time is too slow */
1473 GFP_ATOMIC);
1475 }
1477 /* use prefetched values */
1482 }
1492 }
1494 /**
1495 * e1000_consume_page - helper function
1496 **/
1498 u16 length)
1499 {
1504 }
1506 /**
1507 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1508 * @adapter: board private structure
1509 *
1510 * the return value indicates whether actual cleaning was done, there
1511 * is no guarantee that everything was cleaned
1512 **/
1515 {
1553 cleaned_count++;
1555 DMA_FROM_DEVICE);
1560 /* errors is only valid for DD + EOP descriptors */
1564 /* recycle both page and skb */
1566 /* an error means any chain goes out the window too */
1571 }
1572 #define rxtop (rx_ring->rx_skb_top)
1574 /* this descriptor is only the beginning (or middle) */
1576 /* this is the beginning of a chain */
1581 /* this is the middle of a chain */
1585 length);
1586 /* re-use the skb, only consumed the page */
1588 }
1593 /* end of the chain */
1597 length);
1598 /* re-use the current skb, we only consumed the
1599 * page
1600 */
1606 /* no chain, got EOP, this buf is the packet
1607 * copybreak to save the put_page/alloc_page
1608 */
1614 length);
1616 /* re-use the page, so don't erase
1617 * buffer_info->page
1618 */
1623 length);
1625 length);
1626 }
1627 }
1628 }
1630 /* Receive Checksum Offload */
1635 /* probably a little skewed due to removing CRC */
1637 total_rx_packets++;
1639 /* eth type trans needs skb->data to point to something */
1644 }
1649 next_desc:
1652 /* return some buffers to hardware, one at a time is too slow */
1655 GFP_ATOMIC);
1657 }
1659 /* use prefetched values */
1664 }
1674 }
1676 /**
1677 * e1000_clean_rx_ring - Free Rx Buffers per Queue
1678 * @rx_ring: Rx descriptor ring
1679 **/
1681 {
1688 /* Free all the Rx ring sk_buffs */
1695 DMA_FROM_DEVICE);
1702 DMA_FROM_DEVICE);
1704 }
1709 }
1714 }
1721 DMA_FROM_DEVICE);
1725 }
1726 }
1728 /* there also may be some cached data from a chained receive */
1732 }
1734 /* Zero out the descriptor ring */
1740 }
1743 {
1746 downshift_task);
1752 }
1754 /**
1755 * e1000_intr_msi - Interrupt Handler
1756 * @irq: interrupt number
1757 * @data: pointer to a network interface device structure
1758 **/
1760 {
1766 /* read ICR disables interrupts using IAM */
1769 /* ICH8 workaround-- Call gig speed drop workaround on cable
1770 * disconnect (LSC) before accessing any PHY registers
1771 */
1776 /* 80003ES2LAN workaround-- For packet buffer work-around on
1777 * link down event; disable receives here in the ISR and reset
1778 * adapter in watchdog
1779 */
1782 /* disable receives */
1787 }
1788 /* guard against interrupt when we're going down */
1791 }
1793 /* Reset on uncorrectable ECC error */
1802 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1804 /* Do the reset outside of interrupt context */
1807 /* return immediately since reset is imminent */
1809 }
1817 }
1820 }
1822 /**
1823 * e1000_intr - Interrupt Handler
1824 * @irq: interrupt number
1825 * @data: pointer to a network interface device structure
1826 **/
1828 {
1837 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
1838 * not set, then the adapter didn't send an interrupt
1839 */
1843 /* Interrupt Auto-Mask...upon reading ICR,
1844 * interrupts are masked. No need for the
1845 * IMC write
1846 */
1850 /* ICH8 workaround-- Call gig speed drop workaround on cable
1851 * disconnect (LSC) before accessing any PHY registers
1852 */
1857 /* 80003ES2LAN workaround--
1858 * For packet buffer work-around on link down event;
1859 * disable receives here in the ISR and
1860 * reset adapter in watchdog
1861 */
1864 /* disable receives */
1868 }
1869 /* guard against interrupt when we're going down */
1872 }
1874 /* Reset on uncorrectable ECC error */
1883 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1885 /* Do the reset outside of interrupt context */
1888 /* return immediately since reset is imminent */
1890 }
1898 }
1901 }
1904 {
1914 }
1923 /* guard against interrupt when we're going down */
1926 }
1928 no_link_interrupt:
1933 }
1936 {
1946 /* Ring was not completely cleaned, so fire another interrupt */
1950 }
1953 {
1958 /* Write the ITR value calculated at the end of the
1959 * previous interrupt.
1960 */
1965 }
1971 }
1973 }
1975 /**
1976 * e1000_configure_msix - Configure MSI-X hardware
1977 *
1978 * e1000_configure_msix sets up the hardware to properly
1979 * generate MSI-X interrupts.
1980 **/
1982 {
1991 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1997 }
1999 /* Configure Rx vector */
2005 else
2009 /* Configure Tx vector */
2011 vector++;
2015 else
2020 /* set vector for Other Causes, e.g. link changes */
2021 vector++;
2026 else
2029 /* Cause Tx interrupts on every write back */
2034 /* enable MSI-X PBA support */
2038 /* Auto-Mask Other interrupts upon ICR read */
2043 }
2046 {
2054 }
2055 }
2057 /**
2058 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
2059 *
2060 * Attempt to configure interrupts using the best available
2061 * capabilities of the hardware and kernel.
2062 **/
2064 {
2074 msix_entry),
2075 GFP_KERNEL);
2088 }
2089 /* MSI-X failed, so fall through and try MSI */
2092 }
2094 /* Fall through */
2101 }
2102 /* Fall through */
2104 /* Don't do anything; this is the system default */
2106 }
2108 /* store the number of vectors being used */
2110 }
2112 /**
2113 * e1000_request_msix - Initialize MSI-X interrupts
2114 *
2115 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
2116 * kernel.
2117 **/
2119 {
2127 else
2131 netdev);
2137 vector++;
2143 else
2147 netdev);
2153 vector++;
2163 }
2165 /**
2166 * e1000_request_irq - initialize interrupts
2167 *
2168 * Attempts to configure interrupts using the best available
2169 * capabilities of the hardware and kernel.
2170 **/
2172 {
2180 /* fall back to MSI */
2184 }
2191 /* fall back to legacy interrupt */
2194 }
2202 }
2205 {
2212 vector++;
2215 vector++;
2217 /* Other Causes interrupt vector */
2220 }
2223 }
2225 /**
2226 * e1000_irq_disable - Mask off interrupt generation on the NIC
2227 **/
2229 {
2244 }
2245 }
2247 /**
2248 * e1000_irq_enable - Enable default interrupt generation settings
2249 **/
2251 {
2262 }
2264 }
2266 /**
2267 * e1000e_get_hw_control - get control of the h/w from f/w
2268 * @adapter: address of board private structure
2269 *
2270 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2271 * For ASF and Pass Through versions of f/w this means that
2272 * the driver is loaded. For AMT version (only with 82573)
2273 * of the f/w this means that the network i/f is open.
2274 **/
2276 {
2278 u32 ctrl_ext;
2279 u32 swsm;
2281 /* Let firmware know the driver has taken over */
2288 }
2289 }
2291 /**
2292 * e1000e_release_hw_control - release control of the h/w to f/w
2293 * @adapter: address of board private structure
2294 *
2295 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2296 * For ASF and Pass Through versions of f/w this means that the
2297 * driver is no longer loaded. For AMT version (only with 82573) i
2298 * of the f/w this means that the network i/f is closed.
2299 *
2300 **/
2302 {
2304 u32 ctrl_ext;
2305 u32 swsm;
2307 /* Let firmware taken over control of h/w */
2314 }
2315 }
2317 /**
2318 * e1000_alloc_ring_dma - allocate memory for a ring structure
2319 **/
2322 {
2326 GFP_KERNEL);
2331 }
2333 /**
2334 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
2335 * @tx_ring: Tx descriptor ring
2336 *
2337 * Return 0 on success, negative on failure
2338 **/
2340 {
2349 /* round up to nearest 4K */
2361 err:
2365 }
2367 /**
2368 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
2369 * @rx_ring: Rx descriptor ring
2370 *
2371 * Returns 0 on success, negative on failure
2372 **/
2374 {
2388 GFP_KERNEL);
2391 }
2395 /* Round up to nearest 4K */
2409 err_pages:
2413 }
2414 err:
2418 }
2420 /**
2421 * e1000_clean_tx_ring - Free Tx Buffers
2422 * @tx_ring: Tx descriptor ring
2423 **/
2425 {
2434 }
2444 }
2446 /**
2447 * e1000e_free_tx_resources - Free Tx Resources per Queue
2448 * @tx_ring: Tx descriptor ring
2449 *
2450 * Free all transmit software resources
2451 **/
2453 {
2465 }
2467 /**
2468 * e1000e_free_rx_resources - Free Rx Resources
2469 * @rx_ring: Rx descriptor ring
2470 *
2471 * Free all receive software resources
2472 **/
2474 {
2490 }
2492 /**
2493 * e1000_update_itr - update the dynamic ITR value based on statistics
2494 * @adapter: pointer to adapter
2495 * @itr_setting: current adapter->itr
2496 * @packets: the number of packets during this measurement interval
2497 * @bytes: the number of bytes during this measurement interval
2498 *
2499 * Stores a new ITR value based on packets and byte
2500 * counts during the last interrupt. The advantage of per interrupt
2501 * computation is faster updates and more accurate ITR for the current
2502 * traffic pattern. Constants in this function were computed
2503 * based on theoretical maximum wire speed and thresholds were set based
2504 * on testing data as well as attempting to minimize response time
2505 * while increasing bulk throughput. This functionality is controlled
2506 * by the InterruptThrottleRate module parameter.
2507 **/
2509 {
2517 /* handle TSO and jumbo frames */
2525 /* this if handles the TSO accounting */
2536 }
2544 }
2546 }
2549 }
2552 {
2553 u16 current_itr;
2556 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2561 }
2566 }
2571 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2578 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2584 /* counts and packets in update_itr are dependent on these numbers */
2597 }
2599 set_itr_now:
2601 /* this attempts to bias the interrupt rate towards Bulk
2602 * by adding intermediate steps when interrupt rate is
2603 * increasing
2604 */
2611 else
2613 }
2614 }
2616 /**
2617 * e1000e_write_itr - write the ITR value to the appropriate registers
2618 * @adapter: address of board private structure
2619 * @itr: new ITR value to program
2620 *
2621 * e1000e_write_itr determines if the adapter is in MSI-X mode
2622 * and, if so, writes the EITR registers with the ITR value.
2623 * Otherwise, it writes the ITR value into the ITR register.
2624 **/
2626 {
2637 }
2638 }
2640 /**
2641 * e1000_alloc_queues - Allocate memory for all rings
2642 * @adapter: board private structure to initialize
2643 **/
2645 {
2661 err:
2666 }
2668 /**
2669 * e1000e_poll - NAPI Rx polling callback
2670 * @napi: struct associated with this polling callback
2671 * @weight: number of packets driver is allowed to process this poll
2672 **/
2674 {
2676 napi);
2692 /* If weight not fully consumed, exit the polling mode */
2700 else
2702 }
2703 }
2706 }
2710 {
2715 /* don't update vlan cookie if already programmed */
2717 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2721 /* add VID to filter table */
2727 }
2732 }
2736 {
2742 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2744 /* release control to f/w */
2747 }
2749 /* remove VID from filter table */
2755 }
2760 }
2762 /**
2763 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2764 * @adapter: board private structure to initialize
2765 **/
2767 {
2770 u32 rctl;
2773 /* disable VLAN receive filtering */
2782 }
2783 }
2784 }
2786 /**
2787 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2788 * @adapter: board private structure to initialize
2789 **/
2791 {
2793 u32 rctl;
2796 /* enable VLAN receive filtering */
2801 }
2802 }
2804 /**
2805 * e1000e_vlan_strip_enable - helper to disable HW VLAN stripping
2806 * @adapter: board private structure to initialize
2807 **/
2809 {
2811 u32 ctrl;
2813 /* disable VLAN tag insert/strip */
2817 }
2819 /**
2820 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2821 * @adapter: board private structure to initialize
2822 **/
2824 {
2826 u32 ctrl;
2828 /* enable VLAN tag insert/strip */
2832 }
2835 {
2843 }
2847 }
2850 {
2851 u16 vid;
2857 }
2860 {
2869 /* enable receiving management packets to the host. this will probably
2870 * generate destination unreachable messages from the host OS, but
2871 * the packets will be handled on SMBUS
2872 */
2882 /* Check if IPMI pass-through decision filter already exists;
2883 * if so, enable it.
2884 */
2888 /* Ignore filters with anything other than IPMI ports */
2892 /* Enable this decision filter in MANC2H */
2897 }
2902 /* Create new decision filter in an empty filter */
2906 E1000_MDEF_PORT_664));
2908 j++;
2910 }
2915 }
2919 }
2921 /**
2922 * e1000_configure_tx - Configure Transmit Unit after Reset
2923 * @adapter: board private structure
2924 *
2925 * Configure the Tx unit of the MAC after a reset.
2926 **/
2928 {
2931 u64 tdba;
2934 /* Setup the HW Tx Head and Tail descriptor pointers */
2948 else
2951 /* Set the Tx Interrupt Delay register */
2953 /* Tx irq moderation */
2960 E1000_TXDCTL_WTHRESH);
2961 /* set up some performance related parameters to encourage the
2962 * hardware to use the bus more efficiently in bursts, depends
2963 * on the tx_int_delay to be enabled,
2964 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls
2965 * hthresh = 1 ==> prefetch when one or more available
2966 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2967 * BEWARE: this seems to work but should be considered first if
2968 * there are Tx hangs or other Tx related bugs
2969 */
2972 }
2973 /* erratum work around: set txdctl the same for both queues */
2976 /* Program the Transmit Control Register */
2984 /* set the speed mode bit, we'll clear it if we're not at
2985 * gigabit link later
2986 */
2987 #define SPEED_MODE_BIT (1 << 21)
2990 }
2992 /* errata: program both queues to unweighted RR */
3000 }
3002 /* Setup Transmit Descriptor Settings for eop descriptor */
3005 /* only set IDE if we are delaying interrupts using the timers */
3009 /* enable Report Status bit */
3016 /* SPT Si errata workaround to avoid data corruption */
3018 u32 reg_val;
3027 }
3028 }
3030 /**
3031 * e1000_setup_rctl - configure the receive control registers
3032 * @adapter: Board private structure
3033 **/
3034 #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
3035 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
3037 {
3042 /* Workaround Si errata on PCHx - configure jumbo frame flow.
3043 * If jumbo frames not set, program related MAC/PHY registers
3044 * to h/w defaults
3045 */
3047 s32 ret_val;
3051 else
3056 }
3058 /* Program MC offset vector base */
3065 /* Do not Store bad packets */
3068 /* Enable Long Packet receive */
3071 else
3074 /* Some systems expect that the CRC is included in SMBUS traffic. The
3075 * hardware strips the CRC before sending to both SMBUS (BMC) and to
3076 * host memory when this is enabled
3077 */
3081 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
3083 u16 phy_data;
3096 }
3098 /* Setup buffer sizes */
3116 }
3118 /* Enable Extended Status in all Receive Descriptors */
3123 /* 82571 and greater support packet-split where the protocol
3124 * header is placed in skb->data and the packet data is
3125 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
3126 * In the case of a non-split, skb->data is linearly filled,
3127 * followed by the page buffers. Therefore, skb->data is
3128 * sized to hold the largest protocol header.
3129 *
3130 * allocations using alloc_page take too long for regular MTU
3131 * so only enable packet split for jumbo frames
3132 *
3133 * Using pages when the page size is greater than 16k wastes
3134 * a lot of memory, since we allocate 3 pages at all times
3135 * per packet.
3136 */
3140 else
3146 /* Enable Packet split descriptors */
3154 /* fall-through */
3157 /* fall-through */
3161 }
3164 }
3166 /* This is useful for sniffing bad packets. */
3168 /* UPE and MPE will be handled by normal PROMISC logic
3169 * in e1000e_set_rx_mode
3170 */
3178 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3179 * and that breaks VLANs.
3180 */
3181 }
3184 /* just started the receive unit, no need to restart */
3186 }
3188 /**
3189 * e1000_configure_rx - Configure Receive Unit after Reset
3190 * @adapter: board private structure
3191 *
3192 * Configure the Rx unit of the MAC after a reset.
3193 **/
3195 {
3198 u64 rdba;
3202 /* this is a 32 byte descriptor */
3215 }
3217 /* disable receives while setting up the descriptors */
3225 /* set the writeback threshold (only takes effect if the RDTR
3226 * is set). set GRAN=1 and write back up to 0x4 worth, and
3227 * enable prefetching of 0x20 Rx descriptors
3228 * granularity = 01
3229 * wthresh = 04,
3230 * hthresh = 04,
3231 * pthresh = 0x20
3232 */
3236 /* override the delay timers for enabling bursting, only if
3237 * the value was not set by the user via module options
3238 */
3243 }
3245 /* set the Receive Delay Timer Register */
3248 /* irq moderation */
3254 /* Auto-Mask interrupts upon ICR access */
3260 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3261 * the Base and Length of the Rx Descriptor Ring
3262 */
3275 else
3278 /* Enable Receive Checksum Offload for TCP and UDP */
3282 else
3286 /* With jumbo frames, excessive C-state transition latencies result
3287 * in dropped transactions.
3288 */
3290 u32 lat =
3298 }
3303 PM_QOS_DEFAULT_VALUE);
3304 }
3306 /* Enable Receives */
3308 }
3310 /**
3311 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3312 * @netdev: network interface device structure
3313 *
3314 * Writes multicast address list to the MTA hash table.
3315 * Returns: -ENOMEM on failure
3316 * 0 on no addresses written
3317 * X on writing X addresses to MTA
3318 */
3320 {
3328 /* nothing to program, so clear mc list */
3331 }
3337 /* update_mc_addr_list expects a packed array of only addresses. */
3346 }
3348 /**
3349 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3350 * @netdev: network interface device structure
3351 *
3352 * Writes unicast address list to the RAR table.
3353 * Returns: -ENOMEM on failure/insufficient address space
3354 * 0 on no addresses written
3355 * X on writing X addresses to the RAR table
3356 **/
3358 {
3366 /* save a rar entry for our hardware address */
3367 rar_entries--;
3369 /* save a rar entry for the LAA workaround */
3371 rar_entries--;
3373 /* return ENOMEM indicating insufficient memory for addresses */
3380 /* write the addresses in reverse order to avoid write
3381 * combining
3382 */
3391 count++;
3392 }
3393 }
3395 /* zero out the remaining RAR entries not used above */
3399 }
3403 }
3405 /**
3406 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
3407 * @netdev: network interface device structure
3408 *
3409 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3410 * address list or the network interface flags are updated. This routine is
3411 * responsible for configuring the hardware for proper unicast, multicast,
3412 * promiscuous mode, and all-multi behavior.
3413 **/
3415 {
3418 u32 rctl;
3423 /* Check for Promiscuous and All Multicast modes */
3426 /* clear the affected bits */
3431 /* Do not hardware filter VLANs in promisc mode */
3439 /* Write addresses to the MTA, if the attempt fails
3440 * then we should just turn on promiscuous mode so
3441 * that we can at least receive multicast traffic
3442 */
3446 }
3448 /* Write addresses to available RAR registers, if there is not
3449 * sufficient space to store all the addresses then enable
3450 * unicast promiscuous mode
3451 */
3455 }
3461 else
3463 }
3466 {
3476 /* Direct all traffic to queue 0 */
3480 /* Disable raw packet checksumming so that RSS hash is placed in
3481 * descriptor on writeback.
3482 */
3489 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3490 E1000_MRQC_RSS_FIELD_IPV6 |
3491 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3492 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3495 }
3497 /**
3498 * e1000e_get_base_timinca - get default SYSTIM time increment attributes
3499 * @adapter: board private structure
3500 * @timinca: pointer to returned time increment attributes
3501 *
3502 * Get attributes for incrementing the System Time Register SYSTIML/H at
3503 * the default base frequency, and set the cyclecounter shift value.
3504 **/
3506 {
3510 /* Make sure clock is enabled on I217/I218/I219 before checking
3511 * the frequency
3512 */
3522 }
3523 }
3529 /* Stable 96MHz frequency */
3535 /* Stable 25MHz frequency */
3540 }
3544 /* Stable 24MHz frequency */
3550 }
3554 /* Stable 25MHz frequency */
3562 }
3568 }
3570 /**
3571 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable
3572 * @adapter: board private structure
3573 *
3574 * Outgoing time stamping can be enabled and disabled. Play nice and
3575 * disable it when requested, although it shouldn't cause any overhead
3576 * when no packet needs it. At most one packet in the queue may be
3577 * marked for time stamping, otherwise it would be impossible to tell
3578 * for sure to which packet the hardware time stamp belongs.
3579 *
3580 * Incoming time stamping has to be configured via the hardware filters.
3581 * Not all combinations are supported, in particular event type has to be
3582 * specified. Matching the kind of event packet is not supported, with the
3583 * exception of "all V2 events regardless of level 2 or 4".
3584 **/
3587 {
3595 u32 regval;
3596 s32 ret_val;
3601 /* flags reserved for future extensions - must be zero */
3613 }
3630 /* Also time stamps V2 L2 Path Delay Request/Response */
3636 /* Also time stamps V2 L2 Path Delay Request/Response. */
3642 /* Hardware cannot filter just V2 L4 Sync messages;
3643 * fall-through to V2 (both L2 and L4) Sync.
3644 */
3646 /* Also time stamps V2 Path Delay Request/Response. */
3653 /* Hardware cannot filter just V2 L4 Delay Request messages;
3654 * fall-through to V2 (both L2 and L4) Delay Request.
3655 */
3657 /* Also time stamps V2 Path Delay Request/Response. */
3665 /* Hardware cannot filter just V2 L4 or L2 Event messages;
3666 * fall-through to all V2 (both L2 and L4) Events.
3667 */
3675 /* For V1, the hardware can only filter Sync messages or
3676 * Delay Request messages but not both so fall-through to
3677 * time stamp all packets.
3678 */
3687 }
3691 /* enable/disable Tx h/w time stamping */
3700 }
3702 /* enable/disable Rx h/w time stamping */
3708 E1000_TSYNCRXCTL_TYPE_MASK)) !=
3710 E1000_TSYNCRXCTL_TYPE_MASK))) {
3713 }
3715 /* L2: define ethertype filter for time stamped packets */
3719 /* define which PTP packets get time stamped */
3722 /* Filter by destination port */
3726 }
3731 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */
3735 /* Get and set the System Time Register SYSTIM base frequency */
3741 /* reset the ns time counter */
3746 }
3748 /**
3749 * e1000_configure - configure the hardware for Rx and Tx
3750 * @adapter: private board structure
3751 **/
3753 {
3768 }
3770 /**
3771 * e1000e_power_up_phy - restore link in case the phy was powered down
3772 * @adapter: address of board private structure
3773 *
3774 * The phy may be powered down to save power and turn off link when the
3775 * driver is unloaded and wake on lan is not enabled (among others)
3776 * *** this routine MUST be followed by a call to e1000e_reset ***
3777 **/
3779 {
3784 }
3786 /**
3787 * e1000_power_down_phy - Power down the PHY
3788 *
3789 * Power down the PHY so no link is implied when interface is down.
3790 * The PHY cannot be powered down if management or WoL is active.
3791 */
3793 {
3796 }
3798 /**
3799 * e1000_flush_tx_ring - remove all descriptors from the tx_ring
3800 *
3801 * We want to clear all pending descriptors from the TX ring.
3802 * zeroing happens when the HW reads the regs. We assign the ring itself as
3803 * the data of the next descriptor. We don't care about the data we are about
3804 * to reset the HW.
3805 */
3807 {
3823 /* flush descriptors to memory before notifying the HW */
3831 }
3833 /**
3834 * e1000_flush_rx_ring - remove all descriptors from the rx_ring
3835 *
3836 * Mark all descriptors in the RX ring as consumed and disable the rx ring
3837 */
3839 {
3849 /* zero the lower 14 bits (prefetch and host thresholds) */
3852 /* update thresholds: prefetch threshold to 31, host threshold to 1
3853 * and make sure the granularity is "descriptors" and not "cache lines"
3854 */
3858 /* momentarily enable the RX ring for the changes to take effect */
3863 }
3865 /**
3866 * e1000_flush_desc_rings - remove all descriptors from the descriptor rings
3867 *
3868 * In i219, the descriptor rings must be emptied before resetting the HW
3869 * or before changing the device state to D3 during runtime (runtime PM).
3870 *
3871 * Failure to do this will cause the HW to enter a unit hang state which can
3872 * only be released by PCI reset on the device
3873 *
3874 */
3877 {
3878 u16 hang_state;
3882 /* First, disable MULR fix in FEXTNVM11 */
3886 /* do nothing if we're not in faulty state, or if the queue is empty */
3893 /* recheck, maybe the fault is caused by the rx ring */
3898 }
3900 /**
3901 * e1000e_reset - bring the hardware into a known good state
3902 *
3903 * This function boots the hardware and enables some settings that
3904 * require a configuration cycle of the hardware - those cannot be
3905 * set/changed during runtime. After reset the device needs to be
3906 * properly configured for Rx, Tx etc.
3907 */
3909 {
3915 u16 hwm;
3917 /* reset Packet Buffer Allocation to default */
3921 /* To maintain wire speed transmits, the Tx FIFO should be
3922 * large enough to accommodate two full transmit packets,
3923 * rounded up to the next 1KB and expressed in KB. Likewise,
3924 * the Rx FIFO should be large enough to accommodate at least
3925 * one full receive packet and is similarly rounded up and
3926 * expressed in KB.
3927 */
3929 /* upper 16 bits has Tx packet buffer allocation size in KB */
3931 /* lower 16 bits has Rx packet buffer allocation size in KB */
3933 /* the Tx fifo also stores 16 bytes of information about the Tx
3934 * but don't include ethernet FCS because hardware appends it
3935 */
3940 /* software strips receive CRC, so leave room for it */
3945 /* If current Tx allocation is less than the min Tx FIFO size,
3946 * and the min Tx FIFO size is less than the current Rx FIFO
3947 * allocation, take space away from current Rx allocation
3948 */
3953 /* if short on Rx space, Rx wins and must trump Tx
3954 * adjustment
3955 */
3958 }
3961 }
3963 /* flow control settings
3964 *
3965 * The high water mark must be low enough to fit one full frame
3966 * (or the size used for early receive) above it in the Rx FIFO.
3967 * Set it to the lower of:
3968 * - 90% of the Rx FIFO size, and
3969 * - the full Rx FIFO size minus one full frame
3970 */
3973 else
3987 }
3988 /* fall-through */
3997 /* Workaround PCH LOM adapter hangs with certain network
3998 * loads. If hangs persist, try disabling Tx flow control.
3999 */
4006 }
4019 }
4026 }
4028 /* Alignment of Tx data is on an arbitrary byte boundary with the
4029 * maximum size per Tx descriptor limited only to the transmit
4030 * allocation of the packet buffer minus 96 bytes with an upper
4031 * limit of 24KB due to receive synchronization limitations.
4032 */
4036 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot
4037 * fit in receive buffer.
4038 */
4046 }
4053 }
4054 }
4058 /* Allow time for pending master requests to run */
4061 /* For parts with AMT enabled, let the firmware know
4062 * that the network interface is in control
4063 */
4074 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
4079 /* initialize systim and reset the ns time counter */
4082 /* Set EEE advertisement as appropriate */
4084 s32 ret_val;
4085 u16 adv_addr;
4098 }
4105 }
4112 }
4123 /* speed up time to link by disabling smart power down, ignore
4124 * the return value of this function because there is nothing
4125 * different we would do if it failed
4126 */
4130 }
4132 u32 reg;
4134 /* Fextnvm7 @ 0xe4[2] = 1 */
4138 /* Fextnvm9 @ 0x5bb4[13:12] = 11 */
4141 E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS;
4143 }
4145 }
4148 {
4151 /* hardware has been reset, we need to reload some things */
4162 /* fire a link change interrupt to start the watchdog */
4165 else
4169 }
4172 {
4178 /* flush pending descriptor writebacks to memory */
4182 /* execute the writes immediately */
4185 /* due to rare timing issues, write to TIDV/RDTR again to ensure the
4186 * write is successful
4187 */
4191 /* execute the writes immediately */
4193 }
4197 /**
4198 * e1000e_down - quiesce the device and optionally reset the hardware
4199 * @adapter: board private structure
4200 * @reset: boolean flag to reset the hardware or not
4201 */
4203 {
4208 /* signal that we're down so the interrupt handler does not
4209 * reschedule our watchdog timer
4210 */
4215 /* disable receives in the hardware */
4219 /* flush and sleep below */
4223 /* disable transmits in the hardware */
4228 /* flush both disables and wait for them to finish */
4248 /* Disable Si errata workaround on PCHx for jumbo frame flow */
4259 }
4262 }
4265 {
4272 }
4274 /**
4275 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter)
4276 * @cc: cyclecounter structure
4277 **/
4279 {
4281 cc);
4285 /* SYSTIMH latching upon SYSTIML read does not work well.
4286 * This means that if SYSTIML overflows after we read it but before
4287 * we read SYSTIMH, the value of SYSTIMH has been incremented and we
4288 * will experience a huge non linear increment in the systime value
4289 * to fix that we test for overflow and if true, we re-read systime.
4290 */
4294 /* Check for overflow. If there was no overflow, use the values */
4299 /* There was an overflow, read again SYSTIMH, and use
4300 * systimel_2
4301 */
4305 }
4311 /* errata for 82574/82583 possible bad bits read from SYSTIMH/L
4312 * check to see that the time is incrementing at a reasonable
4313 * rate and is a multiple of incvalue
4314 */
4317 /* latch SYSTIMH on read of SYSTIML */
4330 }
4331 }
4333 }
4335 /**
4336 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4337 * @adapter: board private structure to initialize
4338 *
4339 * e1000_sw_init initializes the Adapter private data structure.
4340 * Fields are initialized based on PCI device information and
4341 * OS network device settings (MTU size).
4342 **/
4344 {
4361 /* Setup hardware time stamping cyclecounter */
4366 /* cc.shift set in e1000e_get_base_tininca() */
4370 }
4372 /* Explicitly disable IRQ since the NIC can be in any state. */
4377 }
4379 /**
4380 * e1000_intr_msi_test - Interrupt Handler
4381 * @irq: interrupt number
4382 * @data: pointer to a network interface device structure
4383 **/
4385 {
4394 /* Force memory writes to complete before acknowledging the
4395 * interrupt is handled.
4396 */
4398 }
4401 }
4403 /**
4404 * e1000_test_msi_interrupt - Returns 0 for successful test
4405 * @adapter: board private struct
4406 *
4407 * code flow taken from tg3.c
4408 **/
4410 {
4415 /* poll_enable hasn't been called yet, so don't need disable */
4416 /* clear any pending events */
4419 /* free the real vector and request a test handler */
4423 /* Assume that the test fails, if it succeeds then the test
4424 * MSI irq handler will unset this flag
4425 */
4437 }
4439 /* Force memory writes to complete before enabling and firing an
4440 * interrupt.
4441 */
4446 /* fire an unusual interrupt on the test handler */
4460 }
4465 msi_test_failed:
4468 }
4470 /**
4471 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
4472 * @adapter: board private struct
4473 *
4474 * code flow taken from tg3.c, called with e1000 interrupts disabled.
4475 **/
4477 {
4479 u16 pci_cmd;
4484 /* disable SERR in case the MSI write causes a master abort */
4492 /* re-enable SERR */
4497 }
4500 }
4502 /**
4503 * e1000_open - Called when a network interface is made active
4504 * @netdev: network interface device structure
4505 *
4506 * Returns 0 on success, negative value on failure
4507 *
4508 * The open entry point is called when a network interface is made
4509 * active by the system (IFF_UP). At this point all resources needed
4510 * for transmit and receive operations are allocated, the interrupt
4511 * handler is registered with the OS, the watchdog timer is started,
4512 * and the stack is notified that the interface is ready.
4513 **/
4515 {
4521 /* disallow open during test */
4529 /* allocate transmit descriptors */
4534 /* allocate receive descriptors */
4539 /* If AMT is enabled, let the firmware know that the network
4540 * interface is now open and reset the part to a known state.
4541 */
4545 }
4553 /* DMA latency requirement to workaround jumbo issue */
4555 PM_QOS_DEFAULT_VALUE);
4557 /* before we allocate an interrupt, we must be ready to handle it.
4558 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4559 * as soon as we call pci_request_irq, so we have to setup our
4560 * clean_rx handler before we do so.
4561 */
4568 /* Work around PCIe errata with MSI interrupts causing some chipsets to
4569 * ignore e1000e MSI messages, which means we need to test our MSI
4570 * interrupt now
4571 */
4577 }
4578 }
4580 /* From here on the code is the same as e1000e_up() */
4593 /* fire a link status change interrupt to start the watchdog */
4596 else
4601 err_req_irq:
4606 err_setup_rx:
4608 err_setup_tx:
4613 }
4615 /**
4616 * e1000_close - Disables a network interface
4617 * @netdev: network interface device structure
4618 *
4619 * Returns 0, this is not allowed to fail
4620 *
4621 * The close entry point is called when an interface is de-activated
4622 * by the OS. The hardware is still under the drivers control, but
4623 * needs to be disabled. A global MAC reset is issued to stop the
4624 * hardware, and all transmit and receive resources are freed.
4625 **/
4627 {
4643 /* Link status message must follow this format */
4645 }
4652 /* kill manageability vlan ID if supported, but not if a vlan with
4653 * the same ID is registered on the host OS (let 8021q kill it)
4654 */
4659 /* If AMT is enabled, let the firmware know that the network
4660 * interface is now closed
4661 */
4671 }
4673 /**
4674 * e1000_set_mac - Change the Ethernet Address of the NIC
4675 * @netdev: network interface device structure
4676 * @p: pointer to an address structure
4677 *
4678 * Returns 0 on success, negative on failure
4679 **/
4681 {
4695 /* activate the work around */
4698 /* Hold a copy of the LAA in RAR[14] This is done so that
4699 * between the time RAR[0] gets clobbered and the time it
4700 * gets fixed (in e1000_watchdog), the actual LAA is in one
4701 * of the RARs and no incoming packets directed to this port
4702 * are dropped. Eventually the LAA will be in RAR[0] and
4703 * RAR[14]
4704 */
4707 }
4710 }
4712 /**
4713 * e1000e_update_phy_task - work thread to update phy
4714 * @work: pointer to our work struct
4715 *
4716 * this worker thread exists because we must acquire a
4717 * semaphore to read the phy, which we could msleep while
4718 * waiting for it, and we can't msleep in a timer.
4719 **/
4721 {
4724 update_phy_task);
4732 /* Enable EEE on 82579 after link up */
4735 }
4737 /**
4738 * e1000_update_phy_info - timre call-back to update PHY info
4739 * @data: pointer to adapter cast into an unsigned long
4740 *
4741 * Need to wait a few seconds after link up to get diagnostic information from
4742 * the phy
4743 **/
4745 {
4752 }
4754 /**
4755 * e1000e_update_phy_stats - Update the PHY statistics counters
4756 * @adapter: board private structure
4757 *
4758 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
4759 **/
4761 {
4763 s32 ret_val;
4764 u16 phy_data;
4770 /* A page set is expensive so check if already on desired page.
4771 * If not, set to the page with the PHY status registers.
4772 */
4783 }
4785 /* Single Collision Count */
4791 /* Excessive Collision Count */
4797 /* Multiple Collision Count */
4803 /* Late Collision Count */
4809 /* Collision Count - also used for adaptive IFS */
4815 /* Defer Count */
4821 /* Transmit with no CRS */
4827 release:
4829 }
4831 /**
4832 * e1000e_update_stats - Update the board statistics counters
4833 * @adapter: board private structure
4834 **/
4836 {
4841 /* Prevent stats update while adapter is being reset, or if the pci
4842 * connection is down.
4843 */
4859 /* Half-duplex statistics */
4875 }
4877 }
4892 /* used for adaptive IFS */
4903 /* Fill out the OS statistics structure */
4907 /* Rx Errors */
4909 /* RLEC on some newer hardware can be incorrect so build
4910 * our own version based on RUC and ROC
4911 */
4921 /* Tx Errors */
4927 /* Tx Dropped needs to be maintained elsewhere */
4929 /* Management Stats */
4934 /* Correctable ECC Errors */
4943 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
4944 }
4945 }
4947 /**
4948 * e1000_phy_read_status - Update the PHY register status snapshot
4949 * @adapter: board private structure
4950 **/
4952 {
4972 /* Do not read PHY registers if link is not up
4973 * Set values to typical power-on defaults
4974 */
4978 BMSR_ERCAP);
4986 }
4987 }
4990 {
4994 /* Link status message must follow this format for user tools */
5001 }
5004 {
5009 /* get_link_status is set on LSC (link status) interrupt or
5010 * Rx sequence error interrupt. get_link_status will stay
5011 * false until the check_for_link establishes link
5012 * for copper adapters ONLY
5013 */
5021 }
5034 }
5038 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
5040 }
5043 }
5046 {
5047 /* make sure the receive unit is started */
5055 }
5056 }
5059 {
5062 /* With 82574 controllers, PHY needs to be checked periodically
5063 * for hung state and reset, if two calls return true
5064 */
5067 else
5074 }
5075 }
5077 /**
5078 * e1000_watchdog - Timer Call-back
5079 * @data: pointer to adapter cast into an unsigned long
5080 **/
5082 {
5085 /* Do the rest outside of interrupt context */
5088 /* TODO: make this use queue_delayed_work() */
5089 }
5092 {
5095 watchdog_task);
5108 /* Cancel scheduled suspend requests. */
5113 }
5123 /* Cancel scheduled suspend requests. */
5126 /* update snapshot of PHY registers on LSC */
5133 /* check if SmartSpeed worked */
5139 /* On supported PHYs, check for duplex mismatch only
5140 * if link has autonegotiated at 10/100 half
5141 */
5148 u16 autoneg_exp;
5153 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
5154 }
5156 /* adjust timeout factor according to speed/duplex */
5167 }
5169 /* workaround: re-program speed mode bit after
5170 * link-up event
5171 */
5174 u32 tarc0;
5179 }
5181 /* disable TSO for pcie and 10/100 speeds, to avoid
5182 * some hardware issues
5183 */
5197 /* oops */
5199 }
5200 }
5202 /* enable transmits in the hardware, need to do this
5203 * after setting TARC(0)
5204 */
5209 /* Perform any post-link-up configuration before
5210 * reporting link up.
5211 */
5220 }
5225 /* Link status message must follow this format */
5232 /* 8000ES2LAN requires a Rx packet buffer work-around
5233 * on link down event; reset the controller to flush
5234 * the Rx packet buffer.
5235 */
5238 else
5240 LINK_TIMEOUT);
5241 }
5242 }
5244 link_up:
5259 /* If the link is lost the controller stops DMA, but
5260 * if there is queued Tx work it cannot be done. So
5261 * reset the controller to flush the Tx packet buffers.
5262 */
5267 /* If reset is necessary, do it outside of interrupt context. */
5270 /* return immediately since reset is imminent */
5272 }
5276 /* Simple mode for Interrupt Throttle Rate (ITR) */
5278 /* Symmetric Tx/Rx gets a reduced ITR=2000;
5279 * Total asymmetrical Tx or Rx gets ITR=8000;
5280 * everyone else is between 2000-8000.
5281 */
5289 }
5291 /* Cause software interrupt to ensure Rx ring is cleaned */
5294 else
5297 /* flush pending descriptors to memory before detecting Tx hang */
5300 /* Force detection of hung controller every watchdog period */
5303 /* With 82571 controllers, LAA may be overwritten due to controller
5304 * reset from the other port. Set the appropriate LAA in RAR[0]
5305 */
5312 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */
5320 }
5321 }
5323 /* Reset the timer */
5327 }
5329 #define E1000_TX_FLAGS_CSUM 0x00000001
5330 #define E1000_TX_FLAGS_VLAN 0x00000002
5331 #define E1000_TX_FLAGS_TSO 0x00000004
5332 #define E1000_TX_FLAGS_IPV4 0x00000008
5333 #define E1000_TX_FLAGS_NO_FCS 0x00000010
5334 #define E1000_TX_FLAGS_HWTSTAMP 0x00000020
5335 #define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
5336 #define E1000_TX_FLAGS_VLAN_SHIFT 16
5339 __be16 protocol)
5340 {
5372 }
5398 i++;
5404 }
5407 __be16 protocol)
5408 {
5413 u8 css;
5425 /* XXX not handling all IPV6 headers */
5434 }
5452 i++;
5458 }
5463 {
5489 count++;
5492 i++;
5495 }
5496 }
5506 i++;
5518 DMA_TO_DEVICE);
5525 count++;
5526 }
5527 }
5530 /* multiply data chunks by size of headers */
5540 dma_error:
5544 count--;
5549 i--;
5552 }
5555 }
5558 {
5567 E1000_TXD_CMD_TSE;
5572 }
5577 }
5582 }
5590 }
5602 i++;
5609 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
5613 /* Force memory writes to complete before letting h/w
5614 * know there are new descriptors to fetch. (Only
5615 * applicable for weak-ordered memory model archs,
5616 * such as IA-64).
5617 */
5621 }
5623 #define MINIMUM_DHCP_PACKET_SIZE 282
5626 {
5633 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
5642 {
5656 }
5659 }
5662 {
5666 /* Herbert's original patch had:
5667 * smp_mb__after_netif_stop_queue();
5668 * but since that doesn't exist yet, just open code it.
5669 */
5672 /* We need to check again in a case another CPU has just
5673 * made room available.
5674 */
5678 /* A reprieve! */
5682 }
5685 {
5691 }
5695 {
5711 }
5716 }
5718 /* The minimum packet size with TCTL.PSP set is 17 bytes so
5719 * pad skb in order to meet this minimum size requirement
5720 */
5726 u8 hdr_len;
5728 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
5729 * points to just header, pull a few bytes of payload from
5730 * frags into skb->data
5731 */
5733 /* we do this workaround for ES2LAN, but it is un-necessary,
5734 * avoiding it could save a lot of cycles
5735 */
5744 }
5746 }
5747 }
5749 /* reserve a descriptor for the offload context */
5751 count++;
5752 count++;
5764 /* need: count + 2 desc gap to keep tail from touching
5765 * head, otherwise try next time
5766 */
5773 E1000_TX_FLAGS_VLAN_SHIFT);
5774 }
5782 }
5789 /* Old method was to assume IPv4 packet by default if TSO was enabled.
5790 * 82571 hardware supports TSO capabilities for IPv6 as well...
5791 * no longer assume, we must.
5792 */
5799 /* if count is 0 then mapping error has occurred */
5801 nr_frags);
5813 }
5817 /* Make sure there is space in the ring for the next send. */
5828 else
5831 /* we need this if more than one processor can write
5832 * to our tail at a time, it synchronizes IO on
5833 *IA64/Altix systems
5834 */
5836 }
5841 }
5844 }
5846 /**
5847 * e1000_tx_timeout - Respond to a Tx Hang
5848 * @netdev: network interface device structure
5849 **/
5851 {
5854 /* Do the reset outside of interrupt context */
5857 }
5860 {
5864 /* don't run the task if already down */
5871 }
5873 }
5875 /**
5876 * e1000_get_stats64 - Get System Network Statistics
5877 * @netdev: network interface device structure
5878 * @stats: rtnl_link_stats64 pointer
5879 *
5880 * Returns the address of the device statistics structure.
5881 **/
5884 {
5890 /* Fill out the OS statistics structure */
5898 /* Rx Errors */
5900 /* RLEC on some newer hardware can be incorrect so build
5901 * our own version based on RUC and ROC
5902 */
5911 /* Tx Errors */
5917 /* Tx Dropped needs to be maintained elsewhere */
5921 }
5923 /**
5924 * e1000_change_mtu - Change the Maximum Transfer Unit
5925 * @netdev: network interface device structure
5926 * @new_mtu: new value for maximum frame size
5927 *
5928 * Returns 0 on success, negative on failure
5929 **/
5931 {
5935 /* Jumbo frame support */
5940 }
5942 /* Supported frame sizes */
5947 }
5949 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
5955 }
5959 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
5969 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
5970 * means we reserve 2 more, this pushes us to allocate from the next
5971 * larger slab size.
5972 * i.e. RXBUFFER_2048 --> size-4096 slab
5973 * However with the new *_jumbo_rx* routines, jumbo receives will use
5974 * fragmented skbs
5975 */
5979 else
5982 /* adjust allocation if LPE protects us, and we aren't using SBP */
5988 else
5996 }
6000 {
6047 }
6052 }
6054 }
6056 /**
6057 * e1000e_hwtstamp_ioctl - control hardware time stamping
6058 * @netdev: network interface device structure
6059 * @ifreq: interface request
6060 *
6061 * Outgoing time stamping can be enabled and disabled. Play nice and
6062 * disable it when requested, although it shouldn't cause any overhead
6063 * when no packet needs it. At most one packet in the queue may be
6064 * marked for time stamping, otherwise it would be impossible to tell
6065 * for sure to which packet the hardware time stamp belongs.
6066 *
6067 * Incoming time stamping has to be configured via the hardware filters.
6068 * Not all combinations are supported, in particular event type has to be
6069 * specified. Matching the kind of event packet is not supported, with the
6070 * exception of "all V2 events regardless of level 2 or 4".
6071 **/
6073 {
6092 /* With V2 type filters which specify a Sync or Delay Request,
6093 * Path Delay Request/Response messages are also time stamped
6094 * by hardware so notify the caller the requested packets plus
6095 * some others are time stamped.
6096 */
6101 }
6105 }
6108 {
6113 }
6116 {
6128 }
6129 }
6132 {
6138 /* copy MAC RARs to PHY RARs */
6145 }
6147 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
6152 /* copy MAC MTA to PHY MTA - only needed for pchlan */
6159 }
6161 /* configure PHY Rx Control register */
6185 /* enable PHY wakeup in MAC register */
6190 /* configure and enable PHY wakeup in PHY registers */
6194 /* activate PHY wakeup */
6199 release:
6203 }
6206 {
6210 u32 ret_val;
6223 fl_out:
6225 }
6228 {
6242 /* Quiesce the device without resetting the hardware */
6245 }
6248 /* Allow time for pending master requests to run */
6252 }
6255 {
6260 /* Runtime suspend should only enable wakeup for link changes */
6272 /* turn on all-multi mode if wake on multicast is enabled */
6277 }
6287 e1000_media_type_internal_serdes) {
6288 /* keep the laser running in D3 */
6292 }
6301 /* enable wakeup by the PHY */
6306 /* enable wakeup by the MAC */
6309 }
6315 }
6322 /* ULP does not support wake from unicast, multicast
6323 * or broadcast.
6324 */
6329 }
6331 /* Ensure that the appropriate bits are set in LPI_CTRL
6332 * for EEE in Sx
6333 */
6345 I82579_EEE_100_SUPPORTED)
6349 I82579_EEE_1000_SUPPORTED)
6353 lpi_ctrl);
6354 }
6355 }
6357 }
6359 /* Release control of h/w to f/w. If f/w is AMT enabled, this
6360 * would have already happened in close and is redundant.
6361 */
6366 /* The pci-e switch on some quad port adapters will report a
6367 * correctable error when the MAC transitions from D0 to D3. To
6368 * prevent this we need to mask off the correctable errors on the
6369 * downstream port of the pci-e switch.
6370 *
6371 * We don't have the associated upstream bridge while assigning
6372 * the PCI device into guest. For example, the KVM on power is
6373 * one of the cases.
6374 */
6377 u16 devctl;
6390 }
6393 }
6395 /**
6396 * __e1000e_disable_aspm - Disable ASPM states
6397 * @pdev: pointer to PCI device struct
6398 * @state: bit-mask of ASPM states to disable
6399 * @locked: indication if this context holds pci_bus_sem locked.
6400 *
6401 * Some devices *must* have certain ASPM states disabled per hardware errata.
6402 **/
6404 {
6413 /* fall-through - can't have L1 without L0s */
6419 }
6428 }
6430 /* Nothing to do if the ASPM states to be disabled already are */
6441 #ifdef CONFIG_PCIEASPM
6444 else
6447 /* Double-check ASPM control. If not disabled by the above, the
6448 * BIOS is preventing that from happening (or CONFIG_PCIEASPM is
6449 * not enabled); override by writing PCI config space directly.
6450 */
6456 #endif
6458 /* Both device and parent should have the same ASPM setting.
6459 * Disable ASPM in downstream component first and then upstream.
6460 */
6465 aspm_dis_mask);
6466 }
6468 /**
6469 * e1000e_disable_aspm - Disable ASPM states.
6470 * @pdev: pointer to PCI device struct
6471 * @state: bit-mask of ASPM states to disable
6472 *
6473 * This function acquires the pci_bus_sem!
6474 * Some devices *must* have certain ASPM states disabled per hardware errata.
6475 **/
6477 {
6479 }
6481 /**
6482 * e1000e_disable_aspm_locked Disable ASPM states.
6483 * @pdev: pointer to PCI device struct
6484 * @state: bit-mask of ASPM states to disable
6485 *
6486 * This function must be called with pci_bus_sem acquired!
6487 * Some devices *must* have certain ASPM states disabled per hardware errata.
6488 **/
6490 {
6492 }
6494 #ifdef CONFIG_PM
6496 {
6516 /* report the system wakeup cause from S3/S4 */
6518 u16 phy_data;
6529 }
6542 }
6544 }
6550 /* If the controller has AMT, do not set DRV_LOAD until the interface
6551 * is up. For all other cases, let the f/w know that the h/w is now
6552 * under the control of the driver.
6553 */
6558 }
6560 #ifdef CONFIG_PM_SLEEP
6562 {
6574 }
6579 }
6582 {
6590 }
6593 {
6602 }
6606 {
6610 u16 eee_lp;
6617 }
6620 }
6623 {
6637 }
6640 {
6653 /* Down the device without resetting the hardware */
6655 }
6660 }
6663 }
6667 {
6673 }
6675 #ifdef CONFIG_NET_POLL_CONTROLLER
6678 {
6691 vector++;
6697 vector++;
6702 }
6705 }
6707 /**
6708 * e1000_netpoll
6709 * @netdev: network interface device structure
6710 *
6711 * Polling 'interrupt' - used by things like netconsole to send skbs
6712 * without having to re-enable interrupts. It's not called while
6713 * the interrupt routine is executing.
6714 */
6716 {
6733 }
6734 }
6735 #endif
6737 /**
6738 * e1000_io_error_detected - called when PCI error is detected
6739 * @pdev: Pointer to PCI device
6740 * @state: The current pci connection state
6741 *
6742 * This function is called after a PCI bus error affecting
6743 * this device has been detected.
6744 */
6746 pci_channel_state_t state)
6747 {
6760 /* Request a slot slot reset. */
6762 }
6764 /**
6765 * e1000_io_slot_reset - called after the pci bus has been reset.
6766 * @pdev: Pointer to PCI device
6767 *
6768 * Restart the card from scratch, as if from a cold-boot. Implementation
6769 * resembles the first-half of the e1000e_pm_resume routine.
6770 */
6772 {
6778 pci_ers_result_t result;
6803 }
6808 }
6810 /**
6811 * e1000_io_resume - called when traffic can start flowing again.
6812 * @pdev: Pointer to PCI device
6813 *
6814 * This callback is called when the error recovery driver tells us that
6815 * its OK to resume normal operation. Implementation resembles the
6816 * second-half of the e1000e_pm_resume routine.
6817 */
6819 {
6830 }
6831 }
6835 /* If the controller has AMT, do not set DRV_LOAD until the interface
6836 * is up. For all other cases, let the f/w know that the h/w is now
6837 * under the control of the driver.
6838 */
6841 }
6844 {
6847 u32 ret_val;
6850 /* print bus type/speed/width info */
6852 /* bus width */
6855 /* MAC address */
6860 E1000_PBANUM_LENGTH);
6865 }
6868 {
6879 /* Deep Smart Power Down (DSPD) */
6882 }
6883 }
6886 netdev_features_t features)
6887 {
6891 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
6896 }
6899 netdev_features_t features)
6900 {
6909 NETIF_F_RXALL)))
6916 /* We need to take it back to defaults, which might mean
6917 * stripping is still disabled at the adapter level.
6918 */
6921 else
6923 }
6924 }
6930 else
6934 }
6950 #ifdef CONFIG_NET_POLL_CONTROLLER
6952 #endif
6956 };
6958 /**
6959 * e1000_probe - Device Initialization Routine
6960 * @pdev: PCI device information struct
6961 * @ent: entry in e1000_pci_tbl
6962 *
6963 * Returns 0 on success, negative on failure
6964 *
6965 * e1000_probe initializes an adapter identified by a pci_dev structure.
6966 * The OS initialization, configuring of the adapter private structure,
6967 * and a hardware reset occur.
6968 **/
6970 {
7005 }
7006 }
7010 e1000e_driver_name);
7014 /* AER (Advanced Error Reporting) hooks */
7018 /* PCI config space info */
7062 }
7064 /* Set default EEE advertisement */
7068 /* construct the net_device struct */
7082 /* setup adapter struct */
7104 /* Copper options */
7109 }
7115 /* Set initial default active device features */
7117 NETIF_F_HW_VLAN_CTAG_RX |
7118 NETIF_F_HW_VLAN_CTAG_TX |
7119 NETIF_F_TSO |
7120 NETIF_F_TSO6 |
7121 NETIF_F_RXHASH |
7122 NETIF_F_RXCSUM |
7123 NETIF_F_HW_CSUM);
7125 /* Set user-changeable features (subset of all device features) */
7135 NETIF_F_TSO |
7136 NETIF_F_TSO6 |
7137 NETIF_F_HW_CSUM);
7144 }
7149 /* before reading the NVM, reset the controller to
7150 * put the device in a known good starting state
7151 */
7154 /* systems with ASPM and others may see the checksum fail on the first
7155 * attempt. Let's give it a few tries
7156 */
7164 }
7165 }
7169 /* copy the MAC address */
7181 }
7197 /* Initialize link parameters. User can change them with ethtool */
7204 /* Initial Wake on LAN setting - If APM wake is enabled in
7205 * the EEPROM, enable the ACPI Magic Packet filter
7206 */
7208 /* APME bit in EEPROM is mapped to WUC.APME */
7218 NVM_INIT_CONTROL3_PORT_B,
7220 else
7222 NVM_INIT_CONTROL3_PORT_A,
7224 }
7226 /* fetch WoL from EEPROM */
7232 /* now that we have the eeprom settings, apply the special cases
7233 * where the eeprom may be wrong or the board simply won't support
7234 * wake on lan on a particular port
7235 */
7239 /* initialize the wol settings based on the eeprom settings */
7242 /* make sure adapter isn't asleep if manageability is enabled */
7247 /* save off EEPROM version number */
7253 }
7255 /* reset the hardware with the new settings */
7258 /* If the controller has AMT, do not set DRV_LOAD until the interface
7259 * is up. For all other cases, let the f/w know that the h/w is now
7260 * under the control of the driver.
7261 */
7270 /* carrier off reporting is important to ethtool even BEFORE open */
7273 /* init PTP hardware clock */
7283 err_register:
7286 err_eeprom:
7289 err_hw_init:
7292 err_sw_init:
7296 err_flashmap:
7298 err_ioremap:
7300 err_alloc_etherdev:
7303 err_pci_reg:
7304 err_dma:
7307 }
7309 /**
7310 * e1000_remove - Device Removal Routine
7311 * @pdev: PCI device information struct
7312 *
7313 * e1000_remove is called by the PCI subsystem to alert the driver
7314 * that it should release a PCI device. The could be caused by a
7315 * Hot-Plug event, or because the driver is going to be removed from
7316 * memory.
7317 **/
7319 {
7326 /* The timers may be rescheduled, so explicitly disable them
7327 * from being rescheduled.
7328 */
7345 }
7346 }
7348 /* Don't lie to e1000_close() down the road. */
7356 /* Release control of h/w to f/w. If f/w is AMT enabled, this
7357 * would have already happened in close and is redundant.
7358 */
7374 /* AER disable */
7378 }
7380 /* PCI Error Recovery (ERS) */
7385 };
7392 board_82571 },
7413 board_80003es2lan },
7415 board_80003es2lan },
7417 board_80003es2lan },
7419 board_80003es2lan },
7470 };
7474 #ifdef CONFIG_PM_SLEEP
7481 #endif
7483 e1000e_pm_runtime_idle)
7484 };
7486 /* PCI Device API Driver */
7494 },
7497 };
7499 /**
7500 * e1000_init_module - Driver Registration Routine
7501 *
7502 * e1000_init_module is the first routine called when the driver is
7503 * loaded. All it does is register with the PCI subsystem.
7504 **/
7506 {
7510 e1000e_driver_version);
7515 }
7518 /**
7519 * e1000_exit_module - Driver Exit Cleanup Routine
7520 *
7521 * e1000_exit_module is called just before the driver is removed
7522 * from memory.
7523 **/
7525 {
7527 }
7535 /* netdev.c */