1 ; RUN: llc -verify-machineinstrs < %s -enable-misched -pre-RA-sched=source -scheditins=false \
2 ; RUN: -disable-ifcvt-triangle-false -disable-post-ra | FileCheck %s
4 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
5 target triple = "powerpc64-bgq-linux"
7 ; %val1 is a load live out of %entry. It should be hoisted
9 ; CHECK-LABEL: testload:
15 define i32 @testload(i32 *%ptr, i32 %sumin) {
17 %sum1 = add i32 %sumin, 1
18 %val1 = load i32, i32* %ptr
19 %p = icmp eq i32 %sumin, 0
20 br i1 %p, label %true, label %end, !prof !1
22 %sum2 = add i32 %sum1, 1
23 %ptr2 = getelementptr i32, i32* %ptr, i32 1
24 %val = load i32, i32* %ptr2
25 %val2 = add i32 %val1, %val
28 %valmerge = phi i32 [ %val1, %entry], [ %val2, %true ]
29 %summerge = phi i32 [ %sum1, %entry], [ %sum2, %true ]
30 %sumout = add i32 %valmerge, %summerge
34 ; The prefetch gets a default latency of 3 cycles and should be hoisted
37 ; CHECK-LABEL: testprefetch:
42 define i32 @testprefetch(i8 *%ptr, i32 %i) {
45 tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3, i32 1 )
46 %p = icmp eq i32 %i, 0
47 br i1 %p, label %true, label %end
49 %val2 = add i32 %val1, 1
52 %valmerge = phi i32 [ %val1, %entry], [ %val2, %true ]
55 declare void @llvm.prefetch(i8*, i32, i32, i32) nounwind
57 !1 = !{!"branch_weights", i32 2, i32 1}