| blob | a34dfb7b09a77df0a29a245834eb145ccd6e63a7 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
3 ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
4 ; RUN: FileCheck %s --check-prefix=CHECK-P8
5 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
6 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
7 ; RUN: FileCheck %s --check-prefix=CHECK-P9
8 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
9 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
10 ; RUN: FileCheck %s --check-prefix=CHECK-BE
12 define i64 @test2elt(i16 %a.coerce) local_unnamed_addr #0 {
13 ; CHECK-P8-LABEL: test2elt:
14 ; CHECK-P8: # %bb.0: # %entry
15 ; CHECK-P8-NEXT: mtvsrd f0, r3
16 ; CHECK-P8-NEXT: mfvsrd r3, f0
17 ; CHECK-P8-NEXT: clrldi r4, r3, 56
18 ; CHECK-P8-NEXT: rldicl r3, r3, 56, 56
19 ; CHECK-P8-NEXT: rlwinm r4, r4, 0, 24, 31
20 ; CHECK-P8-NEXT: rlwinm r3, r3, 0, 24, 31
21 ; CHECK-P8-NEXT: mtfprwz f0, r4
22 ; CHECK-P8-NEXT: mtfprwz f1, r3
23 ; CHECK-P8-NEXT: xscvuxdsp f0, f0
24 ; CHECK-P8-NEXT: xscvuxdsp f1, f1
25 ; CHECK-P8-NEXT: xscvdpspn vs0, f0
26 ; CHECK-P8-NEXT: xscvdpspn vs1, f1
27 ; CHECK-P8-NEXT: xxsldwi v2, vs0, vs0, 1
28 ; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 1
29 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
30 ; CHECK-P8-NEXT: xxswapd vs0, v2
31 ; CHECK-P8-NEXT: mfvsrd r3, f0
32 ; CHECK-P8-NEXT: blr
33 ;
34 ; CHECK-P9-LABEL: test2elt:
35 ; CHECK-P9: # %bb.0: # %entry
36 ; CHECK-P9-NEXT: mtvsrws v2, r3
37 ; CHECK-P9-NEXT: li r3, 0
38 ; CHECK-P9-NEXT: vextubrx r3, r3, v2
39 ; CHECK-P9-NEXT: rlwinm r3, r3, 0, 24, 31
40 ; CHECK-P9-NEXT: mtfprwz f0, r3
41 ; CHECK-P9-NEXT: li r3, 1
42 ; CHECK-P9-NEXT: xscvuxdsp f0, f0
43 ; CHECK-P9-NEXT: xscvdpspn vs0, f0
44 ; CHECK-P9-NEXT: vextubrx r3, r3, v2
45 ; CHECK-P9-NEXT: rlwinm r3, r3, 0, 24, 31
46 ; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 1
47 ; CHECK-P9-NEXT: mtfprwz f0, r3
48 ; CHECK-P9-NEXT: xscvuxdsp f0, f0
49 ; CHECK-P9-NEXT: xscvdpspn vs0, f0
50 ; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 1
51 ; CHECK-P9-NEXT: vmrglw v2, v2, v3
52 ; CHECK-P9-NEXT: mfvsrld r3, v2
53 ; CHECK-P9-NEXT: blr
54 ;
55 ; CHECK-BE-LABEL: test2elt:
56 ; CHECK-BE: # %bb.0: # %entry
57 ; CHECK-BE-NEXT: mtvsrws v2, r3
58 ; CHECK-BE-NEXT: li r3, 1
59 ; CHECK-BE-NEXT: vextublx r3, r3, v2
60 ; CHECK-BE-NEXT: rlwinm r3, r3, 0, 24, 31
61 ; CHECK-BE-NEXT: mtfprwz f0, r3
62 ; CHECK-BE-NEXT: li r3, 0
63 ; CHECK-BE-NEXT: xscvuxdsp f0, f0
64 ; CHECK-BE-NEXT: vextublx r3, r3, v2
65 ; CHECK-BE-NEXT: rlwinm r3, r3, 0, 24, 31
66 ; CHECK-BE-NEXT: xscvdpspn v3, f0
67 ; CHECK-BE-NEXT: mtfprwz f0, r3
68 ; CHECK-BE-NEXT: xscvuxdsp f0, f0
69 ; CHECK-BE-NEXT: xscvdpspn v2, f0
70 ; CHECK-BE-NEXT: vmrghw v2, v2, v3
71 ; CHECK-BE-NEXT: mfvsrd r3, v2
72 ; CHECK-BE-NEXT: blr
73 entry:
74 %0 = bitcast i16 %a.coerce to <2 x i8>
75 %1 = uitofp <2 x i8> %0 to <2 x float>
76 %2 = bitcast <2 x float> %1 to i64
77 ret i64 %2
78 }
80 define <4 x float> @test4elt(i32 %a.coerce) local_unnamed_addr #1 {
81 ; CHECK-P8-LABEL: test4elt:
82 ; CHECK-P8: # %bb.0: # %entry
83 ; CHECK-P8-NEXT: addis r4, r2, .LCPI1_0@toc@ha
84 ; CHECK-P8-NEXT: mtvsrd f0, r3
85 ; CHECK-P8-NEXT: addi r3, r4, .LCPI1_0@toc@l
86 ; CHECK-P8-NEXT: xxlxor v4, v4, v4
87 ; CHECK-P8-NEXT: xxswapd v2, vs0
88 ; CHECK-P8-NEXT: lvx v3, 0, r3
89 ; CHECK-P8-NEXT: vperm v2, v4, v2, v3
90 ; CHECK-P8-NEXT: xvcvuxwsp v2, v2
91 ; CHECK-P8-NEXT: blr
92 ;
93 ; CHECK-P9-LABEL: test4elt:
94 ; CHECK-P9: # %bb.0: # %entry
95 ; CHECK-P9-NEXT: mtvsrws v2, r3
96 ; CHECK-P9-NEXT: addis r3, r2, .LCPI1_0@toc@ha
97 ; CHECK-P9-NEXT: addi r3, r3, .LCPI1_0@toc@l
98 ; CHECK-P9-NEXT: lxvx v3, 0, r3
99 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
100 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
101 ; CHECK-P9-NEXT: xvcvuxwsp v2, v2
102 ; CHECK-P9-NEXT: blr
103 ;
104 ; CHECK-BE-LABEL: test4elt:
105 ; CHECK-BE: # %bb.0: # %entry
106 ; CHECK-BE-NEXT: mtvsrws v2, r3
107 ; CHECK-BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha
108 ; CHECK-BE-NEXT: addi r3, r3, .LCPI1_0@toc@l
109 ; CHECK-BE-NEXT: lxvx v3, 0, r3
110 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
111 ; CHECK-BE-NEXT: vperm v2, v2, v4, v3
112 ; CHECK-BE-NEXT: xvcvuxwsp v2, v2
113 ; CHECK-BE-NEXT: blr
114 entry:
115 %0 = bitcast i32 %a.coerce to <4 x i8>
116 %1 = uitofp <4 x i8> %0 to <4 x float>
117 ret <4 x float> %1
118 }
120 define void @test8elt(<8 x float>* noalias nocapture sret %agg.result, i64 %a.coerce) local_unnamed_addr #2 {
121 ; CHECK-P8-LABEL: test8elt:
122 ; CHECK-P8: # %bb.0: # %entry
123 ; CHECK-P8-NEXT: addis r5, r2, .LCPI2_0@toc@ha
124 ; CHECK-P8-NEXT: mtvsrd f0, r4
125 ; CHECK-P8-NEXT: addis r4, r2, .LCPI2_1@toc@ha
126 ; CHECK-P8-NEXT: addi r5, r5, .LCPI2_0@toc@l
127 ; CHECK-P8-NEXT: addi r4, r4, .LCPI2_1@toc@l
128 ; CHECK-P8-NEXT: xxlxor v4, v4, v4
129 ; CHECK-P8-NEXT: lvx v2, 0, r5
130 ; CHECK-P8-NEXT: xxswapd v3, vs0
131 ; CHECK-P8-NEXT: lvx v5, 0, r4
132 ; CHECK-P8-NEXT: li r4, 16
133 ; CHECK-P8-NEXT: vperm v2, v4, v3, v2
134 ; CHECK-P8-NEXT: vperm v3, v4, v3, v5
135 ; CHECK-P8-NEXT: xvcvuxwsp v2, v2
136 ; CHECK-P8-NEXT: xvcvuxwsp v3, v3
137 ; CHECK-P8-NEXT: stvx v2, 0, r3
138 ; CHECK-P8-NEXT: stvx v3, r3, r4
139 ; CHECK-P8-NEXT: blr
140 ;
141 ; CHECK-P9-LABEL: test8elt:
142 ; CHECK-P9: # %bb.0: # %entry
143 ; CHECK-P9-NEXT: mtvsrd f0, r4
144 ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha
145 ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l
146 ; CHECK-P9-NEXT: lxvx v3, 0, r4
147 ; CHECK-P9-NEXT: xxswapd v2, vs0
148 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
149 ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_1@toc@ha
150 ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_1@toc@l
151 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
152 ; CHECK-P9-NEXT: xvcvuxwsp vs0, v3
153 ; CHECK-P9-NEXT: lxvx v3, 0, r4
154 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
155 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
156 ; CHECK-P9-NEXT: xvcvuxwsp vs1, v2
157 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
158 ; CHECK-P9-NEXT: blr
159 ;
160 ; CHECK-BE-LABEL: test8elt:
161 ; CHECK-BE: # %bb.0: # %entry
162 ; CHECK-BE-NEXT: mtvsrd v2, r4
163 ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha
164 ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l
165 ; CHECK-BE-NEXT: lxvx v3, 0, r4
166 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
167 ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_1@toc@ha
168 ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_1@toc@l
169 ; CHECK-BE-NEXT: vperm v3, v2, v4, v3
170 ; CHECK-BE-NEXT: xvcvuxwsp vs0, v3
171 ; CHECK-BE-NEXT: lxvx v3, 0, r4
172 ; CHECK-BE-NEXT: vperm v2, v4, v2, v3
173 ; CHECK-BE-NEXT: stxv vs0, 0(r3)
174 ; CHECK-BE-NEXT: xvcvuxwsp vs1, v2
175 ; CHECK-BE-NEXT: stxv vs1, 16(r3)
176 ; CHECK-BE-NEXT: blr
177 entry:
178 %0 = bitcast i64 %a.coerce to <8 x i8>
179 %1 = uitofp <8 x i8> %0 to <8 x float>
180 store <8 x float> %1, <8 x float>* %agg.result, align 32
181 ret void
182 }
184 define void @test16elt(<16 x float>* noalias nocapture sret %agg.result, <16 x i8> %a) local_unnamed_addr #3 {
185 ; CHECK-P8-LABEL: test16elt:
186 ; CHECK-P8: # %bb.0: # %entry
187 ; CHECK-P8-NEXT: addis r4, r2, .LCPI3_0@toc@ha
188 ; CHECK-P8-NEXT: addis r5, r2, .LCPI3_2@toc@ha
189 ; CHECK-P8-NEXT: xxlxor v4, v4, v4
190 ; CHECK-P8-NEXT: addi r4, r4, .LCPI3_0@toc@l
191 ; CHECK-P8-NEXT: addi r5, r5, .LCPI3_2@toc@l
192 ; CHECK-P8-NEXT: lvx v3, 0, r4
193 ; CHECK-P8-NEXT: addis r4, r2, .LCPI3_3@toc@ha
194 ; CHECK-P8-NEXT: lvx v5, 0, r5
195 ; CHECK-P8-NEXT: addis r5, r2, .LCPI3_1@toc@ha
196 ; CHECK-P8-NEXT: addi r4, r4, .LCPI3_3@toc@l
197 ; CHECK-P8-NEXT: addi r5, r5, .LCPI3_1@toc@l
198 ; CHECK-P8-NEXT: lvx v0, 0, r4
199 ; CHECK-P8-NEXT: lvx v1, 0, r5
200 ; CHECK-P8-NEXT: li r4, 48
201 ; CHECK-P8-NEXT: li r5, 32
202 ; CHECK-P8-NEXT: vperm v5, v4, v2, v5
203 ; CHECK-P8-NEXT: vperm v3, v4, v2, v3
204 ; CHECK-P8-NEXT: vperm v0, v4, v2, v0
205 ; CHECK-P8-NEXT: vperm v2, v4, v2, v1
206 ; CHECK-P8-NEXT: xvcvuxwsp v4, v5
207 ; CHECK-P8-NEXT: xvcvuxwsp v3, v3
208 ; CHECK-P8-NEXT: xvcvuxwsp v5, v0
209 ; CHECK-P8-NEXT: xvcvuxwsp v2, v2
210 ; CHECK-P8-NEXT: stvx v4, r3, r5
211 ; CHECK-P8-NEXT: stvx v3, 0, r3
212 ; CHECK-P8-NEXT: stvx v5, r3, r4
213 ; CHECK-P8-NEXT: li r4, 16
214 ; CHECK-P8-NEXT: stvx v2, r3, r4
215 ; CHECK-P8-NEXT: blr
216 ;
217 ; CHECK-P9-LABEL: test16elt:
218 ; CHECK-P9: # %bb.0: # %entry
219 ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha
220 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l
221 ; CHECK-P9-NEXT: lxvx v3, 0, r4
222 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
223 ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha
224 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l
225 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
226 ; CHECK-P9-NEXT: xvcvuxwsp vs0, v3
227 ; CHECK-P9-NEXT: lxvx v3, 0, r4
228 ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_2@toc@ha
229 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_2@toc@l
230 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
231 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
232 ; CHECK-P9-NEXT: xvcvuxwsp vs1, v3
233 ; CHECK-P9-NEXT: lxvx v3, 0, r4
234 ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_3@toc@ha
235 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_3@toc@l
236 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
237 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
238 ; CHECK-P9-NEXT: xvcvuxwsp vs2, v3
239 ; CHECK-P9-NEXT: lxvx v3, 0, r4
240 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
241 ; CHECK-P9-NEXT: stxv vs2, 32(r3)
242 ; CHECK-P9-NEXT: xvcvuxwsp vs3, v2
243 ; CHECK-P9-NEXT: stxv vs3, 48(r3)
244 ; CHECK-P9-NEXT: blr
245 ;
246 ; CHECK-BE-LABEL: test16elt:
247 ; CHECK-BE: # %bb.0: # %entry
248 ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha
249 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l
250 ; CHECK-BE-NEXT: lxvx v3, 0, r4
251 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
252 ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha
253 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l
254 ; CHECK-BE-NEXT: vperm v3, v2, v4, v3
255 ; CHECK-BE-NEXT: xvcvuxwsp vs0, v3
256 ; CHECK-BE-NEXT: lxvx v3, 0, r4
257 ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_2@toc@ha
258 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_2@toc@l
259 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
260 ; CHECK-BE-NEXT: stxv vs0, 0(r3)
261 ; CHECK-BE-NEXT: xvcvuxwsp vs1, v3
262 ; CHECK-BE-NEXT: lxvx v3, 0, r4
263 ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_3@toc@ha
264 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_3@toc@l
265 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
266 ; CHECK-BE-NEXT: stxv vs1, 16(r3)
267 ; CHECK-BE-NEXT: xvcvuxwsp vs2, v3
268 ; CHECK-BE-NEXT: lxvx v3, 0, r4
269 ; CHECK-BE-NEXT: vperm v2, v4, v2, v3
270 ; CHECK-BE-NEXT: stxv vs2, 32(r3)
271 ; CHECK-BE-NEXT: xvcvuxwsp vs3, v2
272 ; CHECK-BE-NEXT: stxv vs3, 48(r3)
273 ; CHECK-BE-NEXT: blr
274 entry:
275 %0 = uitofp <16 x i8> %a to <16 x float>
276 store <16 x float> %0, <16 x float>* %agg.result, align 64
277 ret void
278 }
280 define i64 @test2elt_signed(i16 %a.coerce) local_unnamed_addr #0 {
281 ; CHECK-P8-LABEL: test2elt_signed:
282 ; CHECK-P8: # %bb.0: # %entry
283 ; CHECK-P8-NEXT: mtvsrd f0, r3
284 ; CHECK-P8-NEXT: mfvsrd r3, f0
285 ; CHECK-P8-NEXT: clrldi r4, r3, 56
286 ; CHECK-P8-NEXT: rldicl r3, r3, 56, 56
287 ; CHECK-P8-NEXT: extsb r4, r4
288 ; CHECK-P8-NEXT: extsb r3, r3
289 ; CHECK-P8-NEXT: mtfprwa f0, r4
290 ; CHECK-P8-NEXT: mtfprwa f1, r3
291 ; CHECK-P8-NEXT: xscvsxdsp f0, f0
292 ; CHECK-P8-NEXT: xscvsxdsp f1, f1
293 ; CHECK-P8-NEXT: xscvdpspn vs0, f0
294 ; CHECK-P8-NEXT: xscvdpspn vs1, f1
295 ; CHECK-P8-NEXT: xxsldwi v2, vs0, vs0, 1
296 ; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 1
297 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
298 ; CHECK-P8-NEXT: xxswapd vs0, v2
299 ; CHECK-P8-NEXT: mfvsrd r3, f0
300 ; CHECK-P8-NEXT: blr
301 ;
302 ; CHECK-P9-LABEL: test2elt_signed:
303 ; CHECK-P9: # %bb.0: # %entry
304 ; CHECK-P9-NEXT: mtvsrws v2, r3
305 ; CHECK-P9-NEXT: li r3, 0
306 ; CHECK-P9-NEXT: vextubrx r3, r3, v2
307 ; CHECK-P9-NEXT: extsb r3, r3
308 ; CHECK-P9-NEXT: mtfprwa f0, r3
309 ; CHECK-P9-NEXT: li r3, 1
310 ; CHECK-P9-NEXT: xscvsxdsp f0, f0
311 ; CHECK-P9-NEXT: xscvdpspn vs0, f0
312 ; CHECK-P9-NEXT: vextubrx r3, r3, v2
313 ; CHECK-P9-NEXT: extsb r3, r3
314 ; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 1
315 ; CHECK-P9-NEXT: mtfprwa f0, r3
316 ; CHECK-P9-NEXT: xscvsxdsp f0, f0
317 ; CHECK-P9-NEXT: xscvdpspn vs0, f0
318 ; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 1
319 ; CHECK-P9-NEXT: vmrglw v2, v2, v3
320 ; CHECK-P9-NEXT: mfvsrld r3, v2
321 ; CHECK-P9-NEXT: blr
322 ;
323 ; CHECK-BE-LABEL: test2elt_signed:
324 ; CHECK-BE: # %bb.0: # %entry
325 ; CHECK-BE-NEXT: mtvsrws v2, r3
326 ; CHECK-BE-NEXT: li r3, 1
327 ; CHECK-BE-NEXT: vextublx r3, r3, v2
328 ; CHECK-BE-NEXT: extsb r3, r3
329 ; CHECK-BE-NEXT: mtfprwa f0, r3
330 ; CHECK-BE-NEXT: li r3, 0
331 ; CHECK-BE-NEXT: xscvsxdsp f0, f0
332 ; CHECK-BE-NEXT: vextublx r3, r3, v2
333 ; CHECK-BE-NEXT: extsb r3, r3
334 ; CHECK-BE-NEXT: xscvdpspn v3, f0
335 ; CHECK-BE-NEXT: mtfprwa f0, r3
336 ; CHECK-BE-NEXT: xscvsxdsp f0, f0
337 ; CHECK-BE-NEXT: xscvdpspn v2, f0
338 ; CHECK-BE-NEXT: vmrghw v2, v2, v3
339 ; CHECK-BE-NEXT: mfvsrd r3, v2
340 ; CHECK-BE-NEXT: blr
341 entry:
342 %0 = bitcast i16 %a.coerce to <2 x i8>
343 %1 = sitofp <2 x i8> %0 to <2 x float>
344 %2 = bitcast <2 x float> %1 to i64
345 ret i64 %2
346 }
348 define <4 x float> @test4elt_signed(i32 %a.coerce) local_unnamed_addr #1 {
349 ; CHECK-P8-LABEL: test4elt_signed:
350 ; CHECK-P8: # %bb.0: # %entry
351 ; CHECK-P8-NEXT: addis r4, r2, .LCPI5_0@toc@ha
352 ; CHECK-P8-NEXT: mtvsrd f0, r3
353 ; CHECK-P8-NEXT: addi r3, r4, .LCPI5_0@toc@l
354 ; CHECK-P8-NEXT: xxswapd v2, vs0
355 ; CHECK-P8-NEXT: lvx v3, 0, r3
356 ; CHECK-P8-NEXT: vperm v2, v2, v2, v3
357 ; CHECK-P8-NEXT: vspltisw v3, 12
358 ; CHECK-P8-NEXT: vadduwm v3, v3, v3
359 ; CHECK-P8-NEXT: vslw v2, v2, v3
360 ; CHECK-P8-NEXT: vsraw v2, v2, v3
361 ; CHECK-P8-NEXT: xvcvsxwsp v2, v2
362 ; CHECK-P8-NEXT: blr
363 ;
364 ; CHECK-P9-LABEL: test4elt_signed:
365 ; CHECK-P9: # %bb.0: # %entry
366 ; CHECK-P9-NEXT: mtvsrws v2, r3
367 ; CHECK-P9-NEXT: addis r3, r2, .LCPI5_0@toc@ha
368 ; CHECK-P9-NEXT: addi r3, r3, .LCPI5_0@toc@l
369 ; CHECK-P9-NEXT: lxvx v3, 0, r3
370 ; CHECK-P9-NEXT: vperm v2, v2, v2, v3
371 ; CHECK-P9-NEXT: vextsb2w v2, v2
372 ; CHECK-P9-NEXT: xvcvsxwsp v2, v2
373 ; CHECK-P9-NEXT: blr
374 ;
375 ; CHECK-BE-LABEL: test4elt_signed:
376 ; CHECK-BE: # %bb.0: # %entry
377 ; CHECK-BE-NEXT: mtvsrws v2, r3
378 ; CHECK-BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha
379 ; CHECK-BE-NEXT: addi r3, r3, .LCPI5_0@toc@l
380 ; CHECK-BE-NEXT: lxvx v3, 0, r3
381 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
382 ; CHECK-BE-NEXT: vextsb2w v2, v2
383 ; CHECK-BE-NEXT: xvcvsxwsp v2, v2
384 ; CHECK-BE-NEXT: blr
385 entry:
386 %0 = bitcast i32 %a.coerce to <4 x i8>
387 %1 = sitofp <4 x i8> %0 to <4 x float>
388 ret <4 x float> %1
389 }
391 define void @test8elt_signed(<8 x float>* noalias nocapture sret %agg.result, i64 %a.coerce) local_unnamed_addr #2 {
392 ; CHECK-P8-LABEL: test8elt_signed:
393 ; CHECK-P8: # %bb.0: # %entry
394 ; CHECK-P8-NEXT: addis r5, r2, .LCPI6_0@toc@ha
395 ; CHECK-P8-NEXT: mtvsrd f0, r4
396 ; CHECK-P8-NEXT: addis r4, r2, .LCPI6_1@toc@ha
397 ; CHECK-P8-NEXT: vspltisw v5, 12
398 ; CHECK-P8-NEXT: addi r5, r5, .LCPI6_0@toc@l
399 ; CHECK-P8-NEXT: addi r4, r4, .LCPI6_1@toc@l
400 ; CHECK-P8-NEXT: lvx v2, 0, r5
401 ; CHECK-P8-NEXT: xxswapd v3, vs0
402 ; CHECK-P8-NEXT: lvx v4, 0, r4
403 ; CHECK-P8-NEXT: li r4, 16
404 ; CHECK-P8-NEXT: vperm v2, v3, v3, v2
405 ; CHECK-P8-NEXT: vperm v3, v3, v3, v4
406 ; CHECK-P8-NEXT: vadduwm v4, v5, v5
407 ; CHECK-P8-NEXT: vslw v2, v2, v4
408 ; CHECK-P8-NEXT: vslw v3, v3, v4
409 ; CHECK-P8-NEXT: vsraw v2, v2, v4
410 ; CHECK-P8-NEXT: vsraw v3, v3, v4
411 ; CHECK-P8-NEXT: xvcvsxwsp v2, v2
412 ; CHECK-P8-NEXT: xvcvsxwsp v3, v3
413 ; CHECK-P8-NEXT: stvx v2, 0, r3
414 ; CHECK-P8-NEXT: stvx v3, r3, r4
415 ; CHECK-P8-NEXT: blr
416 ;
417 ; CHECK-P9-LABEL: test8elt_signed:
418 ; CHECK-P9: # %bb.0: # %entry
419 ; CHECK-P9-NEXT: mtvsrd f0, r4
420 ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_0@toc@ha
421 ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_0@toc@l
422 ; CHECK-P9-NEXT: lxvx v3, 0, r4
423 ; CHECK-P9-NEXT: xxswapd v2, vs0
424 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
425 ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_1@toc@ha
426 ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_1@toc@l
427 ; CHECK-P9-NEXT: vextsb2w v3, v3
428 ; CHECK-P9-NEXT: xvcvsxwsp vs0, v3
429 ; CHECK-P9-NEXT: lxvx v3, 0, r4
430 ; CHECK-P9-NEXT: vperm v2, v2, v2, v3
431 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
432 ; CHECK-P9-NEXT: vextsb2w v2, v2
433 ; CHECK-P9-NEXT: xvcvsxwsp vs1, v2
434 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
435 ; CHECK-P9-NEXT: blr
436 ;
437 ; CHECK-BE-LABEL: test8elt_signed:
438 ; CHECK-BE: # %bb.0: # %entry
439 ; CHECK-BE-NEXT: mtvsrd v2, r4
440 ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha
441 ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l
442 ; CHECK-BE-NEXT: lxvx v4, 0, r4
443 ; CHECK-BE-NEXT: xxlxor v3, v3, v3
444 ; CHECK-BE-NEXT: vperm v3, v3, v2, v4
445 ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_1@toc@ha
446 ; CHECK-BE-NEXT: vextsb2w v3, v3
447 ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_1@toc@l
448 ; CHECK-BE-NEXT: xvcvsxwsp vs0, v3
449 ; CHECK-BE-NEXT: lxvx v3, 0, r4
450 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
451 ; CHECK-BE-NEXT: stxv vs0, 16(r3)
452 ; CHECK-BE-NEXT: vextsb2w v2, v2
453 ; CHECK-BE-NEXT: xvcvsxwsp vs1, v2
454 ; CHECK-BE-NEXT: stxv vs1, 0(r3)
455 ; CHECK-BE-NEXT: blr
456 entry:
457 %0 = bitcast i64 %a.coerce to <8 x i8>
458 %1 = sitofp <8 x i8> %0 to <8 x float>
459 store <8 x float> %1, <8 x float>* %agg.result, align 32
460 ret void
461 }
463 define void @test16elt_signed(<16 x float>* noalias nocapture sret %agg.result, <16 x i8> %a) local_unnamed_addr #3 {
464 ; CHECK-P8-LABEL: test16elt_signed:
465 ; CHECK-P8: # %bb.0: # %entry
466 ; CHECK-P8-NEXT: addis r4, r2, .LCPI7_0@toc@ha
467 ; CHECK-P8-NEXT: addis r5, r2, .LCPI7_2@toc@ha
468 ; CHECK-P8-NEXT: vspltisw v1, 12
469 ; CHECK-P8-NEXT: addi r4, r4, .LCPI7_0@toc@l
470 ; CHECK-P8-NEXT: addi r5, r5, .LCPI7_2@toc@l
471 ; CHECK-P8-NEXT: lvx v3, 0, r4
472 ; CHECK-P8-NEXT: addis r4, r2, .LCPI7_3@toc@ha
473 ; CHECK-P8-NEXT: lvx v4, 0, r5
474 ; CHECK-P8-NEXT: addis r5, r2, .LCPI7_1@toc@ha
475 ; CHECK-P8-NEXT: addi r4, r4, .LCPI7_3@toc@l
476 ; CHECK-P8-NEXT: addi r5, r5, .LCPI7_1@toc@l
477 ; CHECK-P8-NEXT: lvx v5, 0, r4
478 ; CHECK-P8-NEXT: lvx v0, 0, r5
479 ; CHECK-P8-NEXT: li r4, 48
480 ; CHECK-P8-NEXT: li r5, 32
481 ; CHECK-P8-NEXT: vperm v3, v2, v2, v3
482 ; CHECK-P8-NEXT: vperm v4, v2, v2, v4
483 ; CHECK-P8-NEXT: vperm v5, v2, v2, v5
484 ; CHECK-P8-NEXT: vperm v2, v2, v2, v0
485 ; CHECK-P8-NEXT: vadduwm v0, v1, v1
486 ; CHECK-P8-NEXT: vslw v3, v3, v0
487 ; CHECK-P8-NEXT: vslw v4, v4, v0
488 ; CHECK-P8-NEXT: vslw v5, v5, v0
489 ; CHECK-P8-NEXT: vslw v2, v2, v0
490 ; CHECK-P8-NEXT: vsraw v3, v3, v0
491 ; CHECK-P8-NEXT: vsraw v4, v4, v0
492 ; CHECK-P8-NEXT: vsraw v5, v5, v0
493 ; CHECK-P8-NEXT: vsraw v2, v2, v0
494 ; CHECK-P8-NEXT: xvcvsxwsp v3, v3
495 ; CHECK-P8-NEXT: xvcvsxwsp v4, v4
496 ; CHECK-P8-NEXT: xvcvsxwsp v5, v5
497 ; CHECK-P8-NEXT: xvcvsxwsp v2, v2
498 ; CHECK-P8-NEXT: stvx v3, 0, r3
499 ; CHECK-P8-NEXT: stvx v4, r3, r5
500 ; CHECK-P8-NEXT: stvx v5, r3, r4
501 ; CHECK-P8-NEXT: li r4, 16
502 ; CHECK-P8-NEXT: stvx v2, r3, r4
503 ; CHECK-P8-NEXT: blr
504 ;
505 ; CHECK-P9-LABEL: test16elt_signed:
506 ; CHECK-P9: # %bb.0: # %entry
507 ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_0@toc@ha
508 ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_0@toc@l
509 ; CHECK-P9-NEXT: lxvx v3, 0, r4
510 ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_1@toc@ha
511 ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_1@toc@l
512 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
513 ; CHECK-P9-NEXT: vextsb2w v3, v3
514 ; CHECK-P9-NEXT: xvcvsxwsp vs0, v3
515 ; CHECK-P9-NEXT: lxvx v3, 0, r4
516 ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_2@toc@ha
517 ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_2@toc@l
518 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
519 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
520 ; CHECK-P9-NEXT: vextsb2w v3, v3
521 ; CHECK-P9-NEXT: xvcvsxwsp vs1, v3
522 ; CHECK-P9-NEXT: lxvx v3, 0, r4
523 ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_3@toc@ha
524 ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_3@toc@l
525 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
526 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
527 ; CHECK-P9-NEXT: vextsb2w v3, v3
528 ; CHECK-P9-NEXT: xvcvsxwsp vs2, v3
529 ; CHECK-P9-NEXT: lxvx v3, 0, r4
530 ; CHECK-P9-NEXT: vperm v2, v2, v2, v3
531 ; CHECK-P9-NEXT: stxv vs2, 32(r3)
532 ; CHECK-P9-NEXT: vextsb2w v2, v2
533 ; CHECK-P9-NEXT: xvcvsxwsp vs3, v2
534 ; CHECK-P9-NEXT: stxv vs3, 48(r3)
535 ; CHECK-P9-NEXT: blr
536 ;
537 ; CHECK-BE-LABEL: test16elt_signed:
538 ; CHECK-BE: # %bb.0: # %entry
539 ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_0@toc@ha
540 ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_0@toc@l
541 ; CHECK-BE-NEXT: lxvx v3, 0, r4
542 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
543 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
544 ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_1@toc@ha
545 ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_1@toc@l
546 ; CHECK-BE-NEXT: vextsb2w v3, v3
547 ; CHECK-BE-NEXT: xvcvsxwsp vs0, v3
548 ; CHECK-BE-NEXT: lxvx v3, 0, r4
549 ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_2@toc@ha
550 ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_2@toc@l
551 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
552 ; CHECK-BE-NEXT: stxv vs0, 16(r3)
553 ; CHECK-BE-NEXT: vextsb2w v3, v3
554 ; CHECK-BE-NEXT: xvcvsxwsp vs1, v3
555 ; CHECK-BE-NEXT: lxvx v3, 0, r4
556 ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_3@toc@ha
557 ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_3@toc@l
558 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
559 ; CHECK-BE-NEXT: stxv vs1, 48(r3)
560 ; CHECK-BE-NEXT: vextsb2w v3, v3
561 ; CHECK-BE-NEXT: xvcvsxwsp vs2, v3
562 ; CHECK-BE-NEXT: lxvx v3, 0, r4
563 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
564 ; CHECK-BE-NEXT: stxv vs2, 0(r3)
565 ; CHECK-BE-NEXT: vextsb2w v2, v2
566 ; CHECK-BE-NEXT: xvcvsxwsp vs3, v2
567 ; CHECK-BE-NEXT: stxv vs3, 32(r3)
568 ; CHECK-BE-NEXT: blr
569 entry:
570 %0 = sitofp <16 x i8> %a to <16 x float>
571 store <16 x float> %0, <16 x float>* %agg.result, align 64
572 ret void
573 }