1 //===- llvm/CodeGen/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 /// This file describes how to lower LLVM code to machine code. This has two
13 /// 1. Which ValueTypes are natively supported by the target.
14 /// 2. Which operations are supported for supported ValueTypes.
15 /// 3. Cost thresholds for alternative implementations of certain operations.
17 /// In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_CODEGEN_TARGETLOWERING_H
23 #define LLVM_CODEGEN_TARGETLOWERING_H
25 #include "llvm/ADT/APInt.h"
26 #include "llvm/ADT/ArrayRef.h"
27 #include "llvm/ADT/DenseMap.h"
28 #include "llvm/ADT/STLExtras.h"
29 #include "llvm/ADT/SmallVector.h"
30 #include "llvm/ADT/StringRef.h"
31 #include "llvm/Analysis/LegacyDivergenceAnalysis.h"
32 #include "llvm/CodeGen/DAGCombine.h"
33 #include "llvm/CodeGen/ISDOpcodes.h"
34 #include "llvm/CodeGen/RuntimeLibcalls.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/CodeGen/SelectionDAGNodes.h"
37 #include "llvm/CodeGen/TargetCallingConv.h"
38 #include "llvm/CodeGen/ValueTypes.h"
39 #include "llvm/IR/Attributes.h"
40 #include "llvm/IR/CallSite.h"
41 #include "llvm/IR/CallingConv.h"
42 #include "llvm/IR/DataLayout.h"
43 #include "llvm/IR/DerivedTypes.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/IRBuilder.h"
46 #include "llvm/IR/InlineAsm.h"
47 #include "llvm/IR/Instruction.h"
48 #include "llvm/IR/Instructions.h"
49 #include "llvm/IR/Type.h"
50 #include "llvm/MC/MCRegisterInfo.h"
51 #include "llvm/Support/Alignment.h"
52 #include "llvm/Support/AtomicOrdering.h"
53 #include "llvm/Support/Casting.h"
54 #include "llvm/Support/ErrorHandling.h"
55 #include "llvm/Support/MachineValueType.h"
56 #include "llvm/Target/TargetMachine.h"
69 class BranchProbability
;
74 class FunctionLoweringInfo
;
79 class MachineBasicBlock
;
80 class MachineFunction
;
82 class MachineJumpTableInfo
;
84 class MachineRegisterInfo
;
88 class TargetRegisterClass
;
89 class TargetLibraryInfo
;
90 class TargetRegisterInfo
;
96 None
, // No preference
97 Source
, // Follow source order.
98 RegPressure
, // Scheduling for lowest register pressure.
99 Hybrid
, // Scheduling for both latency and register pressure.
100 ILP
, // Scheduling for ILP in low register pressure mode.
101 VLIW
// Scheduling for VLIW targets.
104 } // end namespace Sched
106 /// This base class for TargetLowering contains the SelectionDAG-independent
107 /// parts that can be used from the rest of CodeGen.
108 class TargetLoweringBase
{
110 /// This enum indicates whether operations are valid for a target, and if not,
111 /// what action should be used to make them valid.
112 enum LegalizeAction
: uint8_t {
113 Legal
, // The target natively supports this operation.
114 Promote
, // This operation should be executed in a larger type.
115 Expand
, // Try to expand this to other ops, otherwise use a libcall.
116 LibCall
, // Don't try to expand this to other ops, always use a libcall.
117 Custom
// Use the LowerOperation hook to implement custom lowering.
120 /// This enum indicates whether a types are legal for a target, and if not,
121 /// what action should be used to make them valid.
122 enum LegalizeTypeAction
: uint8_t {
123 TypeLegal
, // The target natively supports this type.
124 TypePromoteInteger
, // Replace this integer with a larger one.
125 TypeExpandInteger
, // Split this integer into two of half the size.
126 TypeSoftenFloat
, // Convert this float to a same size integer type,
127 // if an operation is not supported in target HW.
128 TypeExpandFloat
, // Split this float into two of half the size.
129 TypeScalarizeVector
, // Replace this one-element vector with its element.
130 TypeSplitVector
, // Split this vector into two of half the size.
131 TypeWidenVector
, // This vector should be widened into a larger vector.
132 TypePromoteFloat
// Replace this float with a larger one.
135 /// LegalizeKind holds the legalization kind that needs to happen to EVT
136 /// in order to type-legalize it.
137 using LegalizeKind
= std::pair
<LegalizeTypeAction
, EVT
>;
139 /// Enum that describes how the target represents true/false values.
140 enum BooleanContent
{
141 UndefinedBooleanContent
, // Only bit 0 counts, the rest can hold garbage.
142 ZeroOrOneBooleanContent
, // All bits zero except for bit 0.
143 ZeroOrNegativeOneBooleanContent
// All bits equal to bit 0.
146 /// Enum that describes what type of support for selects the target has.
147 enum SelectSupportKind
{
148 ScalarValSelect
, // The target supports scalar selects (ex: cmov).
149 ScalarCondVectorVal
, // The target supports selects with a scalar condition
150 // and vector values (ex: cmov).
151 VectorMaskSelect
// The target supports vector selects with a vector
152 // mask (ex: x86 blends).
155 /// Enum that specifies what an atomic load/AtomicRMWInst is expanded
156 /// to, if at all. Exists because different targets have different levels of
157 /// support for these atomic instructions, and also have different options
158 /// w.r.t. what they should expand to.
159 enum class AtomicExpansionKind
{
160 None
, // Don't expand the instruction.
161 LLSC
, // Expand the instruction into loadlinked/storeconditional; used
163 LLOnly
, // Expand the (load) instruction into just a load-linked, which has
164 // greater atomic guarantees than a normal load.
165 CmpXChg
, // Expand the instruction into cmpxchg; used by at least X86.
166 MaskedIntrinsic
, // Use a target-specific intrinsic for the LL/SC loop.
169 /// Enum that specifies when a multiplication should be expanded.
170 enum class MulExpansionKind
{
171 Always
, // Always expand the instruction.
172 OnlyLegalOrCustom
, // Only expand when the resulting instructions are legal
178 Value
*Val
= nullptr;
179 SDValue Node
= SDValue();
189 bool IsSwiftSelf
: 1;
190 bool IsSwiftError
: 1;
191 uint16_t Alignment
= 0;
192 Type
*ByValType
= nullptr;
195 : IsSExt(false), IsZExt(false), IsInReg(false), IsSRet(false),
196 IsNest(false), IsByVal(false), IsInAlloca(false), IsReturned(false),
197 IsSwiftSelf(false), IsSwiftError(false) {}
199 void setAttributes(const CallBase
*Call
, unsigned ArgIdx
);
201 void setAttributes(ImmutableCallSite
*CS
, unsigned ArgIdx
) {
202 return setAttributes(cast
<CallBase
>(CS
->getInstruction()), ArgIdx
);
205 using ArgListTy
= std::vector
<ArgListEntry
>;
207 virtual void markLibCallAttributes(MachineFunction
*MF
, unsigned CC
,
208 ArgListTy
&Args
) const {};
210 static ISD::NodeType
getExtendForContent(BooleanContent Content
) {
212 case UndefinedBooleanContent
:
213 // Extend by adding rubbish bits.
214 return ISD::ANY_EXTEND
;
215 case ZeroOrOneBooleanContent
:
216 // Extend by adding zero bits.
217 return ISD::ZERO_EXTEND
;
218 case ZeroOrNegativeOneBooleanContent
:
219 // Extend by copying the sign bit.
220 return ISD::SIGN_EXTEND
;
222 llvm_unreachable("Invalid content kind");
225 /// NOTE: The TargetMachine owns TLOF.
226 explicit TargetLoweringBase(const TargetMachine
&TM
);
227 TargetLoweringBase(const TargetLoweringBase
&) = delete;
228 TargetLoweringBase
&operator=(const TargetLoweringBase
&) = delete;
229 virtual ~TargetLoweringBase() = default;
232 /// Initialize all of the actions to default values.
236 const TargetMachine
&getTargetMachine() const { return TM
; }
238 virtual bool useSoftFloat() const { return false; }
240 /// Return the pointer type for the given address space, defaults to
241 /// the pointer type from the data layout.
242 /// FIXME: The default needs to be removed once all the code is updated.
243 virtual MVT
getPointerTy(const DataLayout
&DL
, uint32_t AS
= 0) const {
244 return MVT::getIntegerVT(DL
.getPointerSizeInBits(AS
));
247 /// Return the in-memory pointer type for the given address space, defaults to
248 /// the pointer type from the data layout. FIXME: The default needs to be
249 /// removed once all the code is updated.
250 MVT
getPointerMemTy(const DataLayout
&DL
, uint32_t AS
= 0) const {
251 return MVT::getIntegerVT(DL
.getPointerSizeInBits(AS
));
254 /// Return the type for frame index, which is determined by
255 /// the alloca address space specified through the data layout.
256 MVT
getFrameIndexTy(const DataLayout
&DL
) const {
257 return getPointerTy(DL
, DL
.getAllocaAddrSpace());
260 /// Return the type for operands of fence.
261 /// TODO: Let fence operands be of i32 type and remove this.
262 virtual MVT
getFenceOperandTy(const DataLayout
&DL
) const {
263 return getPointerTy(DL
);
266 /// EVT is not used in-tree, but is used by out-of-tree target.
267 /// A documentation for this function would be nice...
268 virtual MVT
getScalarShiftAmountTy(const DataLayout
&, EVT
) const;
270 EVT
getShiftAmountTy(EVT LHSTy
, const DataLayout
&DL
,
271 bool LegalTypes
= true) const;
273 /// Returns the type to be used for the index operand of:
274 /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
275 /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
276 virtual MVT
getVectorIdxTy(const DataLayout
&DL
) const {
277 return getPointerTy(DL
);
280 virtual bool isSelectSupported(SelectSupportKind
/*kind*/) const {
284 /// Return true if it is profitable to convert a select of FP constants into
285 /// a constant pool load whose address depends on the select condition. The
286 /// parameter may be used to differentiate a select with FP compare from
288 virtual bool reduceSelectOfFPConstantLoads(bool IsFPSetCC
) const {
292 /// Return true if multiple condition registers are available.
293 bool hasMultipleConditionRegisters() const {
294 return HasMultipleConditionRegisters
;
297 /// Return true if the target has BitExtract instructions.
298 bool hasExtractBitsInsn() const { return HasExtractBitsInsn
; }
300 /// Return the preferred vector type legalization action.
301 virtual TargetLoweringBase::LegalizeTypeAction
302 getPreferredVectorAction(MVT VT
) const {
303 // The default action for one element vectors is to scalarize
304 if (VT
.getVectorNumElements() == 1)
305 return TypeScalarizeVector
;
306 // The default action for an odd-width vector is to widen.
307 if (!VT
.isPow2VectorType())
308 return TypeWidenVector
;
309 // The default action for other vectors is to promote
310 return TypePromoteInteger
;
313 // There are two general methods for expanding a BUILD_VECTOR node:
314 // 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
316 // 2. Build the vector on the stack and then load it.
317 // If this function returns true, then method (1) will be used, subject to
318 // the constraint that all of the necessary shuffles are legal (as determined
319 // by isShuffleMaskLegal). If this function returns false, then method (2) is
320 // always used. The vector type, and the number of defined values, are
323 shouldExpandBuildVectorWithShuffles(EVT
/* VT */,
324 unsigned DefinedValues
) const {
325 return DefinedValues
< 3;
328 /// Return true if integer divide is usually cheaper than a sequence of
329 /// several shifts, adds, and multiplies for this target.
330 /// The definition of "cheaper" may depend on whether we're optimizing
331 /// for speed or for size.
332 virtual bool isIntDivCheap(EVT VT
, AttributeList Attr
) const { return false; }
334 /// Return true if the target can handle a standalone remainder operation.
335 virtual bool hasStandaloneRem(EVT VT
) const {
339 /// Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).
340 virtual bool isFsqrtCheap(SDValue X
, SelectionDAG
&DAG
) const {
341 // Default behavior is to replace SQRT(X) with X*RSQRT(X).
345 /// Reciprocal estimate status values used by the functions below.
346 enum ReciprocalEstimate
: int {
352 /// Return a ReciprocalEstimate enum value for a square root of the given type
353 /// based on the function's attributes. If the operation is not overridden by
354 /// the function's attributes, "Unspecified" is returned and target defaults
355 /// are expected to be used for instruction selection.
356 int getRecipEstimateSqrtEnabled(EVT VT
, MachineFunction
&MF
) const;
358 /// Return a ReciprocalEstimate enum value for a division of the given type
359 /// based on the function's attributes. If the operation is not overridden by
360 /// the function's attributes, "Unspecified" is returned and target defaults
361 /// are expected to be used for instruction selection.
362 int getRecipEstimateDivEnabled(EVT VT
, MachineFunction
&MF
) const;
364 /// Return the refinement step count for a square root of the given type based
365 /// on the function's attributes. If the operation is not overridden by
366 /// the function's attributes, "Unspecified" is returned and target defaults
367 /// are expected to be used for instruction selection.
368 int getSqrtRefinementSteps(EVT VT
, MachineFunction
&MF
) const;
370 /// Return the refinement step count for a division of the given type based
371 /// on the function's attributes. If the operation is not overridden by
372 /// the function's attributes, "Unspecified" is returned and target defaults
373 /// are expected to be used for instruction selection.
374 int getDivRefinementSteps(EVT VT
, MachineFunction
&MF
) const;
376 /// Returns true if target has indicated at least one type should be bypassed.
377 bool isSlowDivBypassed() const { return !BypassSlowDivWidths
.empty(); }
379 /// Returns map of slow types for division or remainder with corresponding
381 const DenseMap
<unsigned int, unsigned int> &getBypassSlowDivWidths() const {
382 return BypassSlowDivWidths
;
385 /// Return true if Flow Control is an expensive operation that should be
387 bool isJumpExpensive() const { return JumpIsExpensive
; }
389 /// Return true if selects are only cheaper than branches if the branch is
390 /// unlikely to be predicted right.
391 bool isPredictableSelectExpensive() const {
392 return PredictableSelectIsExpensive
;
395 /// If a branch or a select condition is skewed in one direction by more than
396 /// this factor, it is very likely to be predicted correctly.
397 virtual BranchProbability
getPredictableBranchThreshold() const;
399 /// Return true if the following transform is beneficial:
400 /// fold (conv (load x)) -> (load (conv*)x)
401 /// On architectures that don't natively support some vector loads
402 /// efficiently, casting the load to a smaller vector of larger types and
403 /// loading is more efficient, however, this can be undone by optimizations in
405 virtual bool isLoadBitCastBeneficial(EVT LoadVT
, EVT BitcastVT
,
406 const SelectionDAG
&DAG
,
407 const MachineMemOperand
&MMO
) const {
408 // Don't do if we could do an indexed load on the original type, but not on
410 if (!LoadVT
.isSimple() || !BitcastVT
.isSimple())
413 MVT LoadMVT
= LoadVT
.getSimpleVT();
415 // Don't bother doing this if it's just going to be promoted again later, as
416 // doing so might interfere with other combines.
417 if (getOperationAction(ISD::LOAD
, LoadMVT
) == Promote
&&
418 getTypeToPromoteTo(ISD::LOAD
, LoadMVT
) == BitcastVT
.getSimpleVT())
422 return allowsMemoryAccess(*DAG
.getContext(), DAG
.getDataLayout(), BitcastVT
,
426 /// Return true if the following transform is beneficial:
427 /// (store (y (conv x)), y*)) -> (store x, (x*))
428 virtual bool isStoreBitCastBeneficial(EVT StoreVT
, EVT BitcastVT
,
429 const SelectionDAG
&DAG
,
430 const MachineMemOperand
&MMO
) const {
431 // Default to the same logic as loads.
432 return isLoadBitCastBeneficial(StoreVT
, BitcastVT
, DAG
, MMO
);
435 /// Return true if it is expected to be cheaper to do a store of a non-zero
436 /// vector constant with the given size and type for the address space than to
437 /// store the individual scalar element constants.
438 virtual bool storeOfVectorConstantIsCheap(EVT MemVT
,
440 unsigned AddrSpace
) const {
444 /// Allow store merging for the specified type after legalization in addition
445 /// to before legalization. This may transform stores that do not exist
446 /// earlier (for example, stores created from intrinsics).
447 virtual bool mergeStoresAfterLegalization(EVT MemVT
) const {
451 /// Returns if it's reasonable to merge stores to MemVT size.
452 virtual bool canMergeStoresTo(unsigned AS
, EVT MemVT
,
453 const SelectionDAG
&DAG
) const {
457 /// Return true if it is cheap to speculate a call to intrinsic cttz.
458 virtual bool isCheapToSpeculateCttz() const {
462 /// Return true if it is cheap to speculate a call to intrinsic ctlz.
463 virtual bool isCheapToSpeculateCtlz() const {
467 /// Return true if ctlz instruction is fast.
468 virtual bool isCtlzFast() const {
472 /// Return true if it is safe to transform an integer-domain bitwise operation
473 /// into the equivalent floating-point operation. This should be set to true
474 /// if the target has IEEE-754-compliant fabs/fneg operations for the input
476 virtual bool hasBitPreservingFPLogic(EVT VT
) const {
480 /// Return true if it is cheaper to split the store of a merged int val
481 /// from a pair of smaller values into multiple stores.
482 virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy
, EVT HTy
) const {
486 /// Return if the target supports combining a
489 /// %andResult = and %val1, #mask
490 /// %icmpResult = icmp %andResult, 0
492 /// into a single machine instruction of a form like:
494 /// cc = test %register, #mask
496 virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction
&AndI
) const {
500 /// Use bitwise logic to make pairs of compares more efficient. For example:
501 /// and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0
502 /// This should be true when it takes more than one instruction to lower
503 /// setcc (cmp+set on x86 scalar), when bitwise ops are faster than logic on
504 /// condition bits (crand on PowerPC), and/or when reducing cmp+br is a win.
505 virtual bool convertSetCCLogicToBitwiseLogic(EVT VT
) const {
509 /// Return the preferred operand type if the target has a quick way to compare
510 /// integer values of the given size. Assume that any legal integer type can
511 /// be compared efficiently. Targets may override this to allow illegal wide
512 /// types to return a vector type if there is support to compare that type.
513 virtual MVT
hasFastEqualityCompare(unsigned NumBits
) const {
514 MVT VT
= MVT::getIntegerVT(NumBits
);
515 return isTypeLegal(VT
) ? VT
: MVT::INVALID_SIMPLE_VALUE_TYPE
;
518 /// Return true if the target should transform:
519 /// (X & Y) == Y ---> (~X & Y) == 0
520 /// (X & Y) != Y ---> (~X & Y) != 0
522 /// This may be profitable if the target has a bitwise and-not operation that
523 /// sets comparison flags. A target may want to limit the transformation based
524 /// on the type of Y or if Y is a constant.
526 /// Note that the transform will not occur if Y is known to be a power-of-2
527 /// because a mask and compare of a single bit can be handled by inverting the
528 /// predicate, for example:
529 /// (X & 8) == 8 ---> (X & 8) != 0
530 virtual bool hasAndNotCompare(SDValue Y
) const {
534 /// Return true if the target has a bitwise and-not operation:
536 /// This can be used to simplify select or other instructions.
537 virtual bool hasAndNot(SDValue X
) const {
538 // If the target has the more complex version of this operation, assume that
539 // it has this operation too.
540 return hasAndNotCompare(X
);
543 /// Return true if the target has a bit-test instruction:
544 /// (X & (1 << Y)) ==/!= 0
545 /// This knowledge can be used to prevent breaking the pattern,
546 /// or creating it if it could be recognized.
547 virtual bool hasBitTest(SDValue X
, SDValue Y
) const { return false; }
549 /// There are two ways to clear extreme bits (either low or high):
550 /// Mask: x & (-1 << y) (the instcombine canonical form)
551 /// Shifts: x >> y << y
552 /// Return true if the variant with 2 variable shifts is preferred.
553 /// Return false if there is no preference.
554 virtual bool shouldFoldMaskToVariableShiftPair(SDValue X
) const {
555 // By default, let's assume that no one prefers shifts.
559 /// Return true if it is profitable to fold a pair of shifts into a mask.
560 /// This is usually true on most targets. But some targets, like Thumb1,
561 /// have immediate shift instructions, but no immediate "and" instruction;
562 /// this makes the fold unprofitable.
563 virtual bool shouldFoldConstantShiftPairToMask(const SDNode
*N
,
564 CombineLevel Level
) const {
568 /// Should we tranform the IR-optimal check for whether given truncation
569 /// down into KeptBits would be truncating or not:
570 /// (add %x, (1 << (KeptBits-1))) srccond (1 << KeptBits)
571 /// Into it's more traditional form:
572 /// ((%x << C) a>> C) dstcond %x
573 /// Return true if we should transform.
574 /// Return false if there is no preference.
575 virtual bool shouldTransformSignedTruncationCheck(EVT XVT
,
576 unsigned KeptBits
) const {
577 // By default, let's assume that no one prefers shifts.
581 /// Given the pattern
582 /// (X & (C l>>/<< Y)) ==/!= 0
583 /// return true if it should be transformed into:
584 /// ((X <</l>> Y) & C) ==/!= 0
585 /// WARNING: if 'X' is a constant, the fold may deadlock!
586 /// FIXME: we could avoid passing XC, but we can't use isConstOrConstSplat()
587 /// here because it can end up being not linked in.
588 virtual bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(
589 SDValue X
, ConstantSDNode
*XC
, ConstantSDNode
*CC
, SDValue Y
,
590 unsigned OldShiftOpcode
, unsigned NewShiftOpcode
,
591 SelectionDAG
&DAG
) const {
592 if (hasBitTest(X
, Y
)) {
593 // One interesting pattern that we'd want to form is 'bit test':
594 // ((1 << Y) & C) ==/!= 0
595 // But we also need to be careful not to try to reverse that fold.
597 // Is this '1 << Y' ?
598 if (OldShiftOpcode
== ISD::SHL
&& CC
->isOne())
599 return false; // Keep the 'bit test' pattern.
601 // Will it be '1 << Y' after the transform ?
602 if (XC
&& NewShiftOpcode
== ISD::SHL
&& XC
->isOne())
603 return true; // Do form the 'bit test' pattern.
606 // If 'X' is a constant, and we transform, then we will immediately
607 // try to undo the fold, thus causing endless combine loop.
608 // So by default, let's assume everyone prefers the fold
609 // iff 'X' is not a constant.
613 /// These two forms are equivalent:
614 /// sub %y, (xor %x, -1)
615 /// add (add %x, 1), %y
616 /// The variant with two add's is IR-canonical.
617 /// Some targets may prefer one to the other.
618 virtual bool preferIncOfAddToSubOfNot(EVT VT
) const {
619 // By default, let's assume that everyone prefers the form with two add's.
623 /// Return true if the target wants to use the optimization that
624 /// turns ext(promotableInst1(...(promotableInstN(load)))) into
625 /// promotedInst1(...(promotedInstN(ext(load)))).
626 bool enableExtLdPromotion() const { return EnableExtLdPromotion
; }
628 /// Return true if the target can combine store(extractelement VectorTy,
630 /// \p Cost[out] gives the cost of that transformation when this is true.
631 virtual bool canCombineStoreAndExtract(Type
*VectorTy
, Value
*Idx
,
632 unsigned &Cost
) const {
636 /// Return true if inserting a scalar into a variable element of an undef
637 /// vector is more efficiently handled by splatting the scalar instead.
638 virtual bool shouldSplatInsEltVarIndex(EVT
) const {
642 /// Return true if target always beneficiates from combining into FMA for a
643 /// given value type. This must typically return false on targets where FMA
644 /// takes more cycles to execute than FADD.
645 virtual bool enableAggressiveFMAFusion(EVT VT
) const {
649 /// Return the ValueType of the result of SETCC operations.
650 virtual EVT
getSetCCResultType(const DataLayout
&DL
, LLVMContext
&Context
,
653 /// Return the ValueType for comparison libcalls. Comparions libcalls include
654 /// floating point comparion calls, and Ordered/Unordered check calls on
655 /// floating point numbers.
657 MVT::SimpleValueType
getCmpLibcallReturnType() const;
659 /// For targets without i1 registers, this gives the nature of the high-bits
660 /// of boolean values held in types wider than i1.
662 /// "Boolean values" are special true/false values produced by nodes like
663 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
664 /// Not to be confused with general values promoted from i1. Some cpus
665 /// distinguish between vectors of boolean and scalars; the isVec parameter
666 /// selects between the two kinds. For example on X86 a scalar boolean should
667 /// be zero extended from i1, while the elements of a vector of booleans
668 /// should be sign extended from i1.
670 /// Some cpus also treat floating point types the same way as they treat
671 /// vectors instead of the way they treat scalars.
672 BooleanContent
getBooleanContents(bool isVec
, bool isFloat
) const {
674 return BooleanVectorContents
;
675 return isFloat
? BooleanFloatContents
: BooleanContents
;
678 BooleanContent
getBooleanContents(EVT Type
) const {
679 return getBooleanContents(Type
.isVector(), Type
.isFloatingPoint());
682 /// Return target scheduling preference.
683 Sched::Preference
getSchedulingPreference() const {
684 return SchedPreferenceInfo
;
687 /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
688 /// for different nodes. This function returns the preference (or none) for
690 virtual Sched::Preference
getSchedulingPreference(SDNode
*) const {
694 /// Return the register class that should be used for the specified value
696 virtual const TargetRegisterClass
*getRegClassFor(MVT VT
, bool isDivergent
= false) const {
698 const TargetRegisterClass
*RC
= RegClassForVT
[VT
.SimpleTy
];
699 assert(RC
&& "This value type is not natively supported!");
703 /// Allows target to decide about the register class of the
704 /// specific value that is live outside the defining block.
705 /// Returns true if the value needs uniform register class.
706 virtual bool requiresUniformRegister(MachineFunction
&MF
,
707 const Value
*) const {
711 /// Return the 'representative' register class for the specified value
714 /// The 'representative' register class is the largest legal super-reg
715 /// register class for the register class of the value type. For example, on
716 /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
717 /// register class is GR64 on x86_64.
718 virtual const TargetRegisterClass
*getRepRegClassFor(MVT VT
) const {
719 const TargetRegisterClass
*RC
= RepRegClassForVT
[VT
.SimpleTy
];
723 /// Return the cost of the 'representative' register class for the specified
725 virtual uint8_t getRepRegClassCostFor(MVT VT
) const {
726 return RepRegClassCostForVT
[VT
.SimpleTy
];
729 /// Return true if SHIFT instructions should be expanded to SHIFT_PARTS
730 /// instructions, and false if a library call is preferred (e.g for code-size
732 virtual bool shouldExpandShift(SelectionDAG
&DAG
, SDNode
*N
) const {
736 /// Return true if the target has native support for the specified value type.
737 /// This means that it has a register that directly holds it without
738 /// promotions or expansions.
739 bool isTypeLegal(EVT VT
) const {
740 assert(!VT
.isSimple() ||
741 (unsigned)VT
.getSimpleVT().SimpleTy
< array_lengthof(RegClassForVT
));
742 return VT
.isSimple() && RegClassForVT
[VT
.getSimpleVT().SimpleTy
] != nullptr;
745 class ValueTypeActionImpl
{
746 /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
747 /// that indicates how instruction selection should deal with the type.
748 LegalizeTypeAction ValueTypeActions
[MVT::LAST_VALUETYPE
];
751 ValueTypeActionImpl() {
752 std::fill(std::begin(ValueTypeActions
), std::end(ValueTypeActions
),
756 LegalizeTypeAction
getTypeAction(MVT VT
) const {
757 return ValueTypeActions
[VT
.SimpleTy
];
760 void setTypeAction(MVT VT
, LegalizeTypeAction Action
) {
761 ValueTypeActions
[VT
.SimpleTy
] = Action
;
765 const ValueTypeActionImpl
&getValueTypeActions() const {
766 return ValueTypeActions
;
769 /// Return how we should legalize values of this type, either it is already
770 /// legal (return 'Legal') or we need to promote it to a larger type (return
771 /// 'Promote'), or we need to expand it into multiple registers of smaller
772 /// integer type (return 'Expand'). 'Custom' is not an option.
773 LegalizeTypeAction
getTypeAction(LLVMContext
&Context
, EVT VT
) const {
774 return getTypeConversion(Context
, VT
).first
;
776 LegalizeTypeAction
getTypeAction(MVT VT
) const {
777 return ValueTypeActions
.getTypeAction(VT
);
780 /// For types supported by the target, this is an identity function. For
781 /// types that must be promoted to larger types, this returns the larger type
782 /// to promote to. For integer types that are larger than the largest integer
783 /// register, this contains one step in the expansion to get to the smaller
784 /// register. For illegal floating point types, this returns the integer type
786 EVT
getTypeToTransformTo(LLVMContext
&Context
, EVT VT
) const {
787 return getTypeConversion(Context
, VT
).second
;
790 /// For types supported by the target, this is an identity function. For
791 /// types that must be expanded (i.e. integer types that are larger than the
792 /// largest integer register or illegal floating point types), this returns
793 /// the largest legal type it will be expanded to.
794 EVT
getTypeToExpandTo(LLVMContext
&Context
, EVT VT
) const {
795 assert(!VT
.isVector());
797 switch (getTypeAction(Context
, VT
)) {
800 case TypeExpandInteger
:
801 VT
= getTypeToTransformTo(Context
, VT
);
804 llvm_unreachable("Type is not legal nor is it to be expanded!");
809 /// Vector types are broken down into some number of legal first class types.
810 /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
811 /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64
812 /// turns into 4 EVT::i32 values with both PPC and X86.
814 /// This method returns the number of registers needed, and the VT for each
815 /// register. It also returns the VT and quantity of the intermediate values
816 /// before they are promoted/expanded.
817 unsigned getVectorTypeBreakdown(LLVMContext
&Context
, EVT VT
,
819 unsigned &NumIntermediates
,
820 MVT
&RegisterVT
) const;
822 /// Certain targets such as MIPS require that some types such as vectors are
823 /// always broken down into scalars in some contexts. This occurs even if the
824 /// vector type is legal.
825 virtual unsigned getVectorTypeBreakdownForCallingConv(
826 LLVMContext
&Context
, CallingConv::ID CC
, EVT VT
, EVT
&IntermediateVT
,
827 unsigned &NumIntermediates
, MVT
&RegisterVT
) const {
828 return getVectorTypeBreakdown(Context
, VT
, IntermediateVT
, NumIntermediates
,
832 struct IntrinsicInfo
{
833 unsigned opc
= 0; // target opcode
834 EVT memVT
; // memory VT
836 // value representing memory location
837 PointerUnion
<const Value
*, const PseudoSourceValue
*> ptrVal
;
839 int offset
= 0; // offset off of ptrVal
840 unsigned size
= 0; // the size of the memory location
841 // (taken from memVT if zero)
842 MaybeAlign align
= Align(1); // alignment
844 MachineMemOperand::Flags flags
= MachineMemOperand::MONone
;
845 IntrinsicInfo() = default;
848 /// Given an intrinsic, checks if on the target the intrinsic will need to map
849 /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
850 /// true and store the intrinsic information into the IntrinsicInfo that was
851 /// passed to the function.
852 virtual bool getTgtMemIntrinsic(IntrinsicInfo
&, const CallInst
&,
854 unsigned /*Intrinsic*/) const {
858 /// Returns true if the target can instruction select the specified FP
859 /// immediate natively. If false, the legalizer will materialize the FP
860 /// immediate as a load from a constant pool.
861 virtual bool isFPImmLegal(const APFloat
& /*Imm*/, EVT
/*VT*/,
862 bool ForCodeSize
= false) const {
866 /// Targets can use this to indicate that they only support *some*
867 /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
868 /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
870 virtual bool isShuffleMaskLegal(ArrayRef
<int> /*Mask*/, EVT
/*VT*/) const {
874 /// Returns true if the operation can trap for the value type.
876 /// VT must be a legal type. By default, we optimistically assume most
877 /// operations don't trap except for integer divide and remainder.
878 virtual bool canOpTrap(unsigned Op
, EVT VT
) const;
880 /// Similar to isShuffleMaskLegal. Targets can use this to indicate if there
881 /// is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a
882 /// constant pool entry.
883 virtual bool isVectorClearMaskLegal(ArrayRef
<int> /*Mask*/,
888 /// Return how this operation should be treated: either it is legal, needs to
889 /// be promoted to a larger size, needs to be expanded to some other code
890 /// sequence, or the target has a custom expander for it.
891 LegalizeAction
getOperationAction(unsigned Op
, EVT VT
) const {
892 if (VT
.isExtended()) return Expand
;
893 // If a target-specific SDNode requires legalization, require the target
894 // to provide custom legalization for it.
895 if (Op
>= array_lengthof(OpActions
[0])) return Custom
;
896 return OpActions
[(unsigned)VT
.getSimpleVT().SimpleTy
][Op
];
899 /// Custom method defined by each target to indicate if an operation which
900 /// may require a scale is supported natively by the target.
901 /// If not, the operation is illegal.
902 virtual bool isSupportedFixedPointOperation(unsigned Op
, EVT VT
,
903 unsigned Scale
) const {
907 /// Some fixed point operations may be natively supported by the target but
908 /// only for specific scales. This method allows for checking
909 /// if the width is supported by the target for a given operation that may
911 LegalizeAction
getFixedPointOperationAction(unsigned Op
, EVT VT
,
912 unsigned Scale
) const {
913 auto Action
= getOperationAction(Op
, VT
);
917 // This operation is supported in this type but may only work on specific
922 llvm_unreachable("Unexpected fixed point operation.");
924 case ISD::SMULFIXSAT
:
926 Supported
= isSupportedFixedPointOperation(Op
, VT
, Scale
);
930 return Supported
? Action
: Expand
;
933 // If Op is a strict floating-point operation, return the result
934 // of getOperationAction for the equivalent non-strict operation.
935 LegalizeAction
getStrictFPOperationAction(unsigned Op
, EVT VT
) const {
938 default: llvm_unreachable("Unexpected FP pseudo-opcode");
939 case ISD::STRICT_FADD
: EqOpc
= ISD::FADD
; break;
940 case ISD::STRICT_FSUB
: EqOpc
= ISD::FSUB
; break;
941 case ISD::STRICT_FMUL
: EqOpc
= ISD::FMUL
; break;
942 case ISD::STRICT_FDIV
: EqOpc
= ISD::FDIV
; break;
943 case ISD::STRICT_FREM
: EqOpc
= ISD::FREM
; break;
944 case ISD::STRICT_FSQRT
: EqOpc
= ISD::FSQRT
; break;
945 case ISD::STRICT_FPOW
: EqOpc
= ISD::FPOW
; break;
946 case ISD::STRICT_FPOWI
: EqOpc
= ISD::FPOWI
; break;
947 case ISD::STRICT_FMA
: EqOpc
= ISD::FMA
; break;
948 case ISD::STRICT_FSIN
: EqOpc
= ISD::FSIN
; break;
949 case ISD::STRICT_FCOS
: EqOpc
= ISD::FCOS
; break;
950 case ISD::STRICT_FEXP
: EqOpc
= ISD::FEXP
; break;
951 case ISD::STRICT_FEXP2
: EqOpc
= ISD::FEXP2
; break;
952 case ISD::STRICT_FLOG
: EqOpc
= ISD::FLOG
; break;
953 case ISD::STRICT_FLOG10
: EqOpc
= ISD::FLOG10
; break;
954 case ISD::STRICT_FLOG2
: EqOpc
= ISD::FLOG2
; break;
955 case ISD::STRICT_FRINT
: EqOpc
= ISD::FRINT
; break;
956 case ISD::STRICT_FNEARBYINT
: EqOpc
= ISD::FNEARBYINT
; break;
957 case ISD::STRICT_FMAXNUM
: EqOpc
= ISD::FMAXNUM
; break;
958 case ISD::STRICT_FMINNUM
: EqOpc
= ISD::FMINNUM
; break;
959 case ISD::STRICT_FCEIL
: EqOpc
= ISD::FCEIL
; break;
960 case ISD::STRICT_FFLOOR
: EqOpc
= ISD::FFLOOR
; break;
961 case ISD::STRICT_FROUND
: EqOpc
= ISD::FROUND
; break;
962 case ISD::STRICT_FTRUNC
: EqOpc
= ISD::FTRUNC
; break;
963 case ISD::STRICT_FP_ROUND
: EqOpc
= ISD::FP_ROUND
; break;
964 case ISD::STRICT_FP_EXTEND
: EqOpc
= ISD::FP_EXTEND
; break;
967 return getOperationAction(EqOpc
, VT
);
970 /// Return true if the specified operation is legal on this target or can be
971 /// made legal with custom lowering. This is used to help guide high-level
972 /// lowering decisions.
973 bool isOperationLegalOrCustom(unsigned Op
, EVT VT
) const {
974 return (VT
== MVT::Other
|| isTypeLegal(VT
)) &&
975 (getOperationAction(Op
, VT
) == Legal
||
976 getOperationAction(Op
, VT
) == Custom
);
979 /// Return true if the specified operation is legal on this target or can be
980 /// made legal using promotion. This is used to help guide high-level lowering
982 bool isOperationLegalOrPromote(unsigned Op
, EVT VT
) const {
983 return (VT
== MVT::Other
|| isTypeLegal(VT
)) &&
984 (getOperationAction(Op
, VT
) == Legal
||
985 getOperationAction(Op
, VT
) == Promote
);
988 /// Return true if the specified operation is legal on this target or can be
989 /// made legal with custom lowering or using promotion. This is used to help
990 /// guide high-level lowering decisions.
991 bool isOperationLegalOrCustomOrPromote(unsigned Op
, EVT VT
) const {
992 return (VT
== MVT::Other
|| isTypeLegal(VT
)) &&
993 (getOperationAction(Op
, VT
) == Legal
||
994 getOperationAction(Op
, VT
) == Custom
||
995 getOperationAction(Op
, VT
) == Promote
);
998 /// Return true if the operation uses custom lowering, regardless of whether
999 /// the type is legal or not.
1000 bool isOperationCustom(unsigned Op
, EVT VT
) const {
1001 return getOperationAction(Op
, VT
) == Custom
;
1004 /// Return true if lowering to a jump table is allowed.
1005 virtual bool areJTsAllowed(const Function
*Fn
) const {
1006 if (Fn
->getFnAttribute("no-jump-tables").getValueAsString() == "true")
1009 return isOperationLegalOrCustom(ISD::BR_JT
, MVT::Other
) ||
1010 isOperationLegalOrCustom(ISD::BRIND
, MVT::Other
);
1013 /// Check whether the range [Low,High] fits in a machine word.
1014 bool rangeFitsInWord(const APInt
&Low
, const APInt
&High
,
1015 const DataLayout
&DL
) const {
1016 // FIXME: Using the pointer type doesn't seem ideal.
1017 uint64_t BW
= DL
.getIndexSizeInBits(0u);
1018 uint64_t Range
= (High
- Low
).getLimitedValue(UINT64_MAX
- 1) + 1;
1022 /// Return true if lowering to a jump table is suitable for a set of case
1023 /// clusters which may contain \p NumCases cases, \p Range range of values.
1024 virtual bool isSuitableForJumpTable(const SwitchInst
*SI
, uint64_t NumCases
,
1025 uint64_t Range
) const {
1026 // FIXME: This function check the maximum table size and density, but the
1027 // minimum size is not checked. It would be nice if the minimum size is
1028 // also combined within this function. Currently, the minimum size check is
1029 // performed in findJumpTable() in SelectionDAGBuiler and
1030 // getEstimatedNumberOfCaseClusters() in BasicTTIImpl.
1031 const bool OptForSize
= SI
->getParent()->getParent()->hasOptSize();
1032 const unsigned MinDensity
= getMinimumJumpTableDensity(OptForSize
);
1033 const unsigned MaxJumpTableSize
= getMaximumJumpTableSize();
1035 // Check whether the number of cases is small enough and
1036 // the range is dense enough for a jump table.
1037 if ((OptForSize
|| Range
<= MaxJumpTableSize
) &&
1038 (NumCases
* 100 >= Range
* MinDensity
)) {
1044 /// Return true if lowering to a bit test is suitable for a set of case
1045 /// clusters which contains \p NumDests unique destinations, \p Low and
1046 /// \p High as its lowest and highest case values, and expects \p NumCmps
1047 /// case value comparisons. Check if the number of destinations, comparison
1048 /// metric, and range are all suitable.
1049 bool isSuitableForBitTests(unsigned NumDests
, unsigned NumCmps
,
1050 const APInt
&Low
, const APInt
&High
,
1051 const DataLayout
&DL
) const {
1052 // FIXME: I don't think NumCmps is the correct metric: a single case and a
1053 // range of cases both require only one branch to lower. Just looking at the
1054 // number of clusters and destinations should be enough to decide whether to
1057 // To lower a range with bit tests, the range must fit the bitwidth of a
1059 if (!rangeFitsInWord(Low
, High
, DL
))
1062 // Decide whether it's profitable to lower this range with bit tests. Each
1063 // destination requires a bit test and branch, and there is an overall range
1064 // check branch. For a small number of clusters, separate comparisons might
1065 // be cheaper, and for many destinations, splitting the range might be
1067 return (NumDests
== 1 && NumCmps
>= 3) || (NumDests
== 2 && NumCmps
>= 5) ||
1068 (NumDests
== 3 && NumCmps
>= 6);
1071 /// Return true if the specified operation is illegal on this target or
1072 /// unlikely to be made legal with custom lowering. This is used to help guide
1073 /// high-level lowering decisions.
1074 bool isOperationExpand(unsigned Op
, EVT VT
) const {
1075 return (!isTypeLegal(VT
) || getOperationAction(Op
, VT
) == Expand
);
1078 /// Return true if the specified operation is legal on this target.
1079 bool isOperationLegal(unsigned Op
, EVT VT
) const {
1080 return (VT
== MVT::Other
|| isTypeLegal(VT
)) &&
1081 getOperationAction(Op
, VT
) == Legal
;
1084 /// Return how this load with extension should be treated: either it is legal,
1085 /// needs to be promoted to a larger size, needs to be expanded to some other
1086 /// code sequence, or the target has a custom expander for it.
1087 LegalizeAction
getLoadExtAction(unsigned ExtType
, EVT ValVT
,
1089 if (ValVT
.isExtended() || MemVT
.isExtended()) return Expand
;
1090 unsigned ValI
= (unsigned) ValVT
.getSimpleVT().SimpleTy
;
1091 unsigned MemI
= (unsigned) MemVT
.getSimpleVT().SimpleTy
;
1092 assert(ExtType
< ISD::LAST_LOADEXT_TYPE
&& ValI
< MVT::LAST_VALUETYPE
&&
1093 MemI
< MVT::LAST_VALUETYPE
&& "Table isn't big enough!");
1094 unsigned Shift
= 4 * ExtType
;
1095 return (LegalizeAction
)((LoadExtActions
[ValI
][MemI
] >> Shift
) & 0xf);
1098 /// Return true if the specified load with extension is legal on this target.
1099 bool isLoadExtLegal(unsigned ExtType
, EVT ValVT
, EVT MemVT
) const {
1100 return getLoadExtAction(ExtType
, ValVT
, MemVT
) == Legal
;
1103 /// Return true if the specified load with extension is legal or custom
1105 bool isLoadExtLegalOrCustom(unsigned ExtType
, EVT ValVT
, EVT MemVT
) const {
1106 return getLoadExtAction(ExtType
, ValVT
, MemVT
) == Legal
||
1107 getLoadExtAction(ExtType
, ValVT
, MemVT
) == Custom
;
1110 /// Return how this store with truncation should be treated: either it is
1111 /// legal, needs to be promoted to a larger size, needs to be expanded to some
1112 /// other code sequence, or the target has a custom expander for it.
1113 LegalizeAction
getTruncStoreAction(EVT ValVT
, EVT MemVT
) const {
1114 if (ValVT
.isExtended() || MemVT
.isExtended()) return Expand
;
1115 unsigned ValI
= (unsigned) ValVT
.getSimpleVT().SimpleTy
;
1116 unsigned MemI
= (unsigned) MemVT
.getSimpleVT().SimpleTy
;
1117 assert(ValI
< MVT::LAST_VALUETYPE
&& MemI
< MVT::LAST_VALUETYPE
&&
1118 "Table isn't big enough!");
1119 return TruncStoreActions
[ValI
][MemI
];
1122 /// Return true if the specified store with truncation is legal on this
1124 bool isTruncStoreLegal(EVT ValVT
, EVT MemVT
) const {
1125 return isTypeLegal(ValVT
) && getTruncStoreAction(ValVT
, MemVT
) == Legal
;
1128 /// Return true if the specified store with truncation has solution on this
1130 bool isTruncStoreLegalOrCustom(EVT ValVT
, EVT MemVT
) const {
1131 return isTypeLegal(ValVT
) &&
1132 (getTruncStoreAction(ValVT
, MemVT
) == Legal
||
1133 getTruncStoreAction(ValVT
, MemVT
) == Custom
);
1136 /// Return how the indexed load should be treated: either it is legal, needs
1137 /// to be promoted to a larger size, needs to be expanded to some other code
1138 /// sequence, or the target has a custom expander for it.
1140 getIndexedLoadAction(unsigned IdxMode
, MVT VT
) const {
1141 assert(IdxMode
< ISD::LAST_INDEXED_MODE
&& VT
.isValid() &&
1142 "Table isn't big enough!");
1143 unsigned Ty
= (unsigned)VT
.SimpleTy
;
1144 return (LegalizeAction
)((IndexedModeActions
[Ty
][IdxMode
] & 0xf0) >> 4);
1147 /// Return true if the specified indexed load is legal on this target.
1148 bool isIndexedLoadLegal(unsigned IdxMode
, EVT VT
) const {
1149 return VT
.isSimple() &&
1150 (getIndexedLoadAction(IdxMode
, VT
.getSimpleVT()) == Legal
||
1151 getIndexedLoadAction(IdxMode
, VT
.getSimpleVT()) == Custom
);
1154 /// Return how the indexed store should be treated: either it is legal, needs
1155 /// to be promoted to a larger size, needs to be expanded to some other code
1156 /// sequence, or the target has a custom expander for it.
1158 getIndexedStoreAction(unsigned IdxMode
, MVT VT
) const {
1159 assert(IdxMode
< ISD::LAST_INDEXED_MODE
&& VT
.isValid() &&
1160 "Table isn't big enough!");
1161 unsigned Ty
= (unsigned)VT
.SimpleTy
;
1162 return (LegalizeAction
)(IndexedModeActions
[Ty
][IdxMode
] & 0x0f);
1165 /// Return true if the specified indexed load is legal on this target.
1166 bool isIndexedStoreLegal(unsigned IdxMode
, EVT VT
) const {
1167 return VT
.isSimple() &&
1168 (getIndexedStoreAction(IdxMode
, VT
.getSimpleVT()) == Legal
||
1169 getIndexedStoreAction(IdxMode
, VT
.getSimpleVT()) == Custom
);
1172 /// Return how the condition code should be treated: either it is legal, needs
1173 /// to be expanded to some other code sequence, or the target has a custom
1174 /// expander for it.
1176 getCondCodeAction(ISD::CondCode CC
, MVT VT
) const {
1177 assert((unsigned)CC
< array_lengthof(CondCodeActions
) &&
1178 ((unsigned)VT
.SimpleTy
>> 3) < array_lengthof(CondCodeActions
[0]) &&
1179 "Table isn't big enough!");
1180 // See setCondCodeAction for how this is encoded.
1181 uint32_t Shift
= 4 * (VT
.SimpleTy
& 0x7);
1182 uint32_t Value
= CondCodeActions
[CC
][VT
.SimpleTy
>> 3];
1183 LegalizeAction Action
= (LegalizeAction
) ((Value
>> Shift
) & 0xF);
1184 assert(Action
!= Promote
&& "Can't promote condition code!");
1188 /// Return true if the specified condition code is legal on this target.
1189 bool isCondCodeLegal(ISD::CondCode CC
, MVT VT
) const {
1190 return getCondCodeAction(CC
, VT
) == Legal
;
1193 /// Return true if the specified condition code is legal or custom on this
1195 bool isCondCodeLegalOrCustom(ISD::CondCode CC
, MVT VT
) const {
1196 return getCondCodeAction(CC
, VT
) == Legal
||
1197 getCondCodeAction(CC
, VT
) == Custom
;
1200 /// If the action for this operation is to promote, this method returns the
1201 /// ValueType to promote to.
1202 MVT
getTypeToPromoteTo(unsigned Op
, MVT VT
) const {
1203 assert(getOperationAction(Op
, VT
) == Promote
&&
1204 "This operation isn't promoted!");
1206 // See if this has an explicit type specified.
1207 std::map
<std::pair
<unsigned, MVT::SimpleValueType
>,
1208 MVT::SimpleValueType
>::const_iterator PTTI
=
1209 PromoteToType
.find(std::make_pair(Op
, VT
.SimpleTy
));
1210 if (PTTI
!= PromoteToType
.end()) return PTTI
->second
;
1212 assert((VT
.isInteger() || VT
.isFloatingPoint()) &&
1213 "Cannot autopromote this type, add it with AddPromotedToType.");
1217 NVT
= (MVT::SimpleValueType
)(NVT
.SimpleTy
+1);
1218 assert(NVT
.isInteger() == VT
.isInteger() && NVT
!= MVT::isVoid
&&
1219 "Didn't find type to promote to!");
1220 } while (!isTypeLegal(NVT
) ||
1221 getOperationAction(Op
, NVT
) == Promote
);
1225 /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM
1226 /// operations except for the pointer size. If AllowUnknown is true, this
1227 /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
1228 /// otherwise it will assert.
1229 EVT
getValueType(const DataLayout
&DL
, Type
*Ty
,
1230 bool AllowUnknown
= false) const {
1231 // Lower scalar pointers to native pointer types.
1232 if (auto *PTy
= dyn_cast
<PointerType
>(Ty
))
1233 return getPointerTy(DL
, PTy
->getAddressSpace());
1235 if (auto *VTy
= dyn_cast
<VectorType
>(Ty
)) {
1236 Type
*EltTy
= VTy
->getElementType();
1237 // Lower vectors of pointers to native pointer types.
1238 if (auto *PTy
= dyn_cast
<PointerType
>(EltTy
)) {
1239 EVT
PointerTy(getPointerTy(DL
, PTy
->getAddressSpace()));
1240 EltTy
= PointerTy
.getTypeForEVT(Ty
->getContext());
1242 return EVT::getVectorVT(Ty
->getContext(), EVT::getEVT(EltTy
, false),
1243 VTy
->getElementCount());
1246 return EVT::getEVT(Ty
, AllowUnknown
);
1249 EVT
getMemValueType(const DataLayout
&DL
, Type
*Ty
,
1250 bool AllowUnknown
= false) const {
1251 // Lower scalar pointers to native pointer types.
1252 if (PointerType
*PTy
= dyn_cast
<PointerType
>(Ty
))
1253 return getPointerMemTy(DL
, PTy
->getAddressSpace());
1254 else if (VectorType
*VTy
= dyn_cast
<VectorType
>(Ty
)) {
1255 Type
*Elm
= VTy
->getElementType();
1256 if (PointerType
*PT
= dyn_cast
<PointerType
>(Elm
)) {
1257 EVT
PointerTy(getPointerMemTy(DL
, PT
->getAddressSpace()));
1258 Elm
= PointerTy
.getTypeForEVT(Ty
->getContext());
1260 return EVT::getVectorVT(Ty
->getContext(), EVT::getEVT(Elm
, false),
1261 VTy
->getNumElements());
1264 return getValueType(DL
, Ty
, AllowUnknown
);
1268 /// Return the MVT corresponding to this LLVM type. See getValueType.
1269 MVT
getSimpleValueType(const DataLayout
&DL
, Type
*Ty
,
1270 bool AllowUnknown
= false) const {
1271 return getValueType(DL
, Ty
, AllowUnknown
).getSimpleVT();
1274 /// Return the desired alignment for ByVal or InAlloca aggregate function
1275 /// arguments in the caller parameter area. This is the actual alignment, not
1277 virtual unsigned getByValTypeAlignment(Type
*Ty
, const DataLayout
&DL
) const;
1279 /// Return the type of registers that this ValueType will eventually require.
1280 MVT
getRegisterType(MVT VT
) const {
1281 assert((unsigned)VT
.SimpleTy
< array_lengthof(RegisterTypeForVT
));
1282 return RegisterTypeForVT
[VT
.SimpleTy
];
1285 /// Return the type of registers that this ValueType will eventually require.
1286 MVT
getRegisterType(LLVMContext
&Context
, EVT VT
) const {
1287 if (VT
.isSimple()) {
1288 assert((unsigned)VT
.getSimpleVT().SimpleTy
<
1289 array_lengthof(RegisterTypeForVT
));
1290 return RegisterTypeForVT
[VT
.getSimpleVT().SimpleTy
];
1292 if (VT
.isVector()) {
1295 unsigned NumIntermediates
;
1296 (void)getVectorTypeBreakdown(Context
, VT
, VT1
,
1297 NumIntermediates
, RegisterVT
);
1300 if (VT
.isInteger()) {
1301 return getRegisterType(Context
, getTypeToTransformTo(Context
, VT
));
1303 llvm_unreachable("Unsupported extended type!");
1306 /// Return the number of registers that this ValueType will eventually
1309 /// This is one for any types promoted to live in larger registers, but may be
1310 /// more than one for types (like i64) that are split into pieces. For types
1311 /// like i140, which are first promoted then expanded, it is the number of
1312 /// registers needed to hold all the bits of the original type. For an i140
1313 /// on a 32 bit machine this means 5 registers.
1314 unsigned getNumRegisters(LLVMContext
&Context
, EVT VT
) const {
1315 if (VT
.isSimple()) {
1316 assert((unsigned)VT
.getSimpleVT().SimpleTy
<
1317 array_lengthof(NumRegistersForVT
));
1318 return NumRegistersForVT
[VT
.getSimpleVT().SimpleTy
];
1320 if (VT
.isVector()) {
1323 unsigned NumIntermediates
;
1324 return getVectorTypeBreakdown(Context
, VT
, VT1
, NumIntermediates
, VT2
);
1326 if (VT
.isInteger()) {
1327 unsigned BitWidth
= VT
.getSizeInBits();
1328 unsigned RegWidth
= getRegisterType(Context
, VT
).getSizeInBits();
1329 return (BitWidth
+ RegWidth
- 1) / RegWidth
;
1331 llvm_unreachable("Unsupported extended type!");
1334 /// Certain combinations of ABIs, Targets and features require that types
1335 /// are legal for some operations and not for other operations.
1336 /// For MIPS all vector types must be passed through the integer register set.
1337 virtual MVT
getRegisterTypeForCallingConv(LLVMContext
&Context
,
1338 CallingConv::ID CC
, EVT VT
) const {
1339 return getRegisterType(Context
, VT
);
1342 /// Certain targets require unusual breakdowns of certain types. For MIPS,
1343 /// this occurs when a vector type is used, as vector are passed through the
1344 /// integer register set.
1345 virtual unsigned getNumRegistersForCallingConv(LLVMContext
&Context
,
1348 return getNumRegisters(Context
, VT
);
1351 /// Certain targets have context senstive alignment requirements, where one
1352 /// type has the alignment requirement of another type.
1353 virtual unsigned getABIAlignmentForCallingConv(Type
*ArgTy
,
1354 DataLayout DL
) const {
1355 return DL
.getABITypeAlignment(ArgTy
);
1358 /// If true, then instruction selection should seek to shrink the FP constant
1359 /// of the specified type to a smaller type in order to save space and / or
1361 virtual bool ShouldShrinkFPConstant(EVT
) const { return true; }
1363 /// Return true if it is profitable to reduce a load to a smaller type.
1364 /// Example: (i16 (trunc (i32 (load x))) -> i16 load x
1365 virtual bool shouldReduceLoadWidth(SDNode
*Load
, ISD::LoadExtType ExtTy
,
1367 // By default, assume that it is cheaper to extract a subvector from a wide
1368 // vector load rather than creating multiple narrow vector loads.
1369 if (NewVT
.isVector() && !Load
->hasOneUse())
1375 /// When splitting a value of the specified type into parts, does the Lo
1376 /// or Hi part come first? This usually follows the endianness, except
1377 /// for ppcf128, where the Hi part always comes first.
1378 bool hasBigEndianPartOrdering(EVT VT
, const DataLayout
&DL
) const {
1379 return DL
.isBigEndian() || VT
== MVT::ppcf128
;
1382 /// If true, the target has custom DAG combine transformations that it can
1383 /// perform for the specified node.
1384 bool hasTargetDAGCombine(ISD::NodeType NT
) const {
1385 assert(unsigned(NT
>> 3) < array_lengthof(TargetDAGCombineArray
));
1386 return TargetDAGCombineArray
[NT
>> 3] & (1 << (NT
&7));
1389 unsigned getGatherAllAliasesMaxDepth() const {
1390 return GatherAllAliasesMaxDepth
;
1393 /// Returns the size of the platform's va_list object.
1394 virtual unsigned getVaListSizeInBits(const DataLayout
&DL
) const {
1395 return getPointerTy(DL
).getSizeInBits();
1398 /// Get maximum # of store operations permitted for llvm.memset
1400 /// This function returns the maximum number of store operations permitted
1401 /// to replace a call to llvm.memset. The value is set by the target at the
1402 /// performance threshold for such a replacement. If OptSize is true,
1403 /// return the limit for functions that have OptSize attribute.
1404 unsigned getMaxStoresPerMemset(bool OptSize
) const {
1405 return OptSize
? MaxStoresPerMemsetOptSize
: MaxStoresPerMemset
;
1408 /// Get maximum # of store operations permitted for llvm.memcpy
1410 /// This function returns the maximum number of store operations permitted
1411 /// to replace a call to llvm.memcpy. The value is set by the target at the
1412 /// performance threshold for such a replacement. If OptSize is true,
1413 /// return the limit for functions that have OptSize attribute.
1414 unsigned getMaxStoresPerMemcpy(bool OptSize
) const {
1415 return OptSize
? MaxStoresPerMemcpyOptSize
: MaxStoresPerMemcpy
;
1418 /// \brief Get maximum # of store operations to be glued together
1420 /// This function returns the maximum number of store operations permitted
1421 /// to glue together during lowering of llvm.memcpy. The value is set by
1422 // the target at the performance threshold for such a replacement.
1423 virtual unsigned getMaxGluedStoresPerMemcpy() const {
1424 return MaxGluedStoresPerMemcpy
;
1427 /// Get maximum # of load operations permitted for memcmp
1429 /// This function returns the maximum number of load operations permitted
1430 /// to replace a call to memcmp. The value is set by the target at the
1431 /// performance threshold for such a replacement. If OptSize is true,
1432 /// return the limit for functions that have OptSize attribute.
1433 unsigned getMaxExpandSizeMemcmp(bool OptSize
) const {
1434 return OptSize
? MaxLoadsPerMemcmpOptSize
: MaxLoadsPerMemcmp
;
1437 /// Get maximum # of store operations permitted for llvm.memmove
1439 /// This function returns the maximum number of store operations permitted
1440 /// to replace a call to llvm.memmove. The value is set by the target at the
1441 /// performance threshold for such a replacement. If OptSize is true,
1442 /// return the limit for functions that have OptSize attribute.
1443 unsigned getMaxStoresPerMemmove(bool OptSize
) const {
1444 return OptSize
? MaxStoresPerMemmoveOptSize
: MaxStoresPerMemmove
;
1447 /// Determine if the target supports unaligned memory accesses.
1449 /// This function returns true if the target allows unaligned memory accesses
1450 /// of the specified type in the given address space. If true, it also returns
1451 /// whether the unaligned memory access is "fast" in the last argument by
1452 /// reference. This is used, for example, in situations where an array
1453 /// copy/move/set is converted to a sequence of store operations. Its use
1454 /// helps to ensure that such replacements don't generate code that causes an
1455 /// alignment error (trap) on the target machine.
1456 virtual bool allowsMisalignedMemoryAccesses(
1457 EVT
, unsigned AddrSpace
= 0, unsigned Align
= 1,
1458 MachineMemOperand::Flags Flags
= MachineMemOperand::MONone
,
1459 bool * /*Fast*/ = nullptr) const {
1463 /// LLT handling variant.
1464 virtual bool allowsMisalignedMemoryAccesses(
1465 LLT
, unsigned AddrSpace
= 0, unsigned Align
= 1,
1466 MachineMemOperand::Flags Flags
= MachineMemOperand::MONone
,
1467 bool * /*Fast*/ = nullptr) const {
1471 /// Return true if the target supports a memory access of this type for the
1472 /// given address space and alignment. If the access is allowed, the optional
1473 /// final parameter returns if the access is also fast (as defined by the
1476 allowsMemoryAccess(LLVMContext
&Context
, const DataLayout
&DL
, EVT VT
,
1477 unsigned AddrSpace
= 0, unsigned Alignment
= 1,
1478 MachineMemOperand::Flags Flags
= MachineMemOperand::MONone
,
1479 bool *Fast
= nullptr) const;
1481 /// Return true if the target supports a memory access of this type for the
1482 /// given MachineMemOperand. If the access is allowed, the optional
1483 /// final parameter returns if the access is also fast (as defined by the
1485 bool allowsMemoryAccess(LLVMContext
&Context
, const DataLayout
&DL
, EVT VT
,
1486 const MachineMemOperand
&MMO
,
1487 bool *Fast
= nullptr) const;
1489 /// Returns the target specific optimal type for load and store operations as
1490 /// a result of memset, memcpy, and memmove lowering.
1492 /// If DstAlign is zero that means it's safe to destination alignment can
1493 /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
1494 /// a need to check it against alignment requirement, probably because the
1495 /// source does not need to be loaded. If 'IsMemset' is true, that means it's
1496 /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
1497 /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
1498 /// does not need to be loaded. It returns EVT::Other if the type should be
1499 /// determined using generic target-independent logic.
1501 getOptimalMemOpType(uint64_t /*Size*/, unsigned /*DstAlign*/,
1502 unsigned /*SrcAlign*/, bool /*IsMemset*/,
1503 bool /*ZeroMemset*/, bool /*MemcpyStrSrc*/,
1504 const AttributeList
& /*FuncAttributes*/) const {
1509 /// LLT returning variant.
1511 getOptimalMemOpLLT(uint64_t /*Size*/, unsigned /*DstAlign*/,
1512 unsigned /*SrcAlign*/, bool /*IsMemset*/,
1513 bool /*ZeroMemset*/, bool /*MemcpyStrSrc*/,
1514 const AttributeList
& /*FuncAttributes*/) const {
1518 /// Returns true if it's safe to use load / store of the specified type to
1519 /// expand memcpy / memset inline.
1521 /// This is mostly true for all types except for some special cases. For
1522 /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
1523 /// fstpl which also does type conversion. Note the specified type doesn't
1524 /// have to be legal as the hook is used before type legalization.
1525 virtual bool isSafeMemOpType(MVT
/*VT*/) const { return true; }
1527 /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
1528 bool usesUnderscoreSetJmp() const {
1529 return UseUnderscoreSetJmp
;
1532 /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
1533 bool usesUnderscoreLongJmp() const {
1534 return UseUnderscoreLongJmp
;
1537 /// Return lower limit for number of blocks in a jump table.
1538 virtual unsigned getMinimumJumpTableEntries() const;
1540 /// Return lower limit of the density in a jump table.
1541 unsigned getMinimumJumpTableDensity(bool OptForSize
) const;
1543 /// Return upper limit for number of entries in a jump table.
1544 /// Zero if no limit.
1545 unsigned getMaximumJumpTableSize() const;
1547 virtual bool isJumpTableRelative() const {
1548 return TM
.isPositionIndependent();
1551 /// If a physical register, this specifies the register that
1552 /// llvm.savestack/llvm.restorestack should save and restore.
1553 unsigned getStackPointerRegisterToSaveRestore() const {
1554 return StackPointerRegisterToSaveRestore
;
1557 /// If a physical register, this returns the register that receives the
1558 /// exception address on entry to an EH pad.
1560 getExceptionPointerRegister(const Constant
*PersonalityFn
) const {
1561 // 0 is guaranteed to be the NoRegister value on all targets
1565 /// If a physical register, this returns the register that receives the
1566 /// exception typeid on entry to a landing pad.
1568 getExceptionSelectorRegister(const Constant
*PersonalityFn
) const {
1569 // 0 is guaranteed to be the NoRegister value on all targets
1573 virtual bool needsFixedCatchObjects() const {
1574 report_fatal_error("Funclet EH is not implemented for this target");
1577 /// Return the minimum stack alignment of an argument.
1578 unsigned getMinStackArgumentAlignment() const {
1579 return MinStackArgumentAlignment
;
1582 /// Return the minimum function alignment.
1583 unsigned getMinFunctionAlignment() const {
1584 return MinFunctionAlignment
;
1587 /// Return the preferred function alignment.
1588 unsigned getPrefFunctionAlignment() const {
1589 return PrefFunctionAlignment
;
1592 /// Return the preferred loop alignment.
1593 virtual unsigned getPrefLoopAlignment(MachineLoop
*ML
= nullptr) const {
1594 return PrefLoopAlignment
;
1597 /// Should loops be aligned even when the function is marked OptSize (but not
1599 virtual bool alignLoopsWithOptSize() const {
1603 /// If the target has a standard location for the stack protector guard,
1604 /// returns the address of that location. Otherwise, returns nullptr.
1605 /// DEPRECATED: please override useLoadStackGuardNode and customize
1606 /// LOAD_STACK_GUARD, or customize \@llvm.stackguard().
1607 virtual Value
*getIRStackGuard(IRBuilder
<> &IRB
) const;
1609 /// Inserts necessary declarations for SSP (stack protection) purpose.
1610 /// Should be used only when getIRStackGuard returns nullptr.
1611 virtual void insertSSPDeclarations(Module
&M
) const;
1613 /// Return the variable that's previously inserted by insertSSPDeclarations,
1614 /// if any, otherwise return nullptr. Should be used only when
1615 /// getIRStackGuard returns nullptr.
1616 virtual Value
*getSDagStackGuard(const Module
&M
) const;
1618 /// If this function returns true, stack protection checks should XOR the
1619 /// frame pointer (or whichever pointer is used to address locals) into the
1620 /// stack guard value before checking it. getIRStackGuard must return nullptr
1621 /// if this returns true.
1622 virtual bool useStackGuardXorFP() const { return false; }
1624 /// If the target has a standard stack protection check function that
1625 /// performs validation and error handling, returns the function. Otherwise,
1626 /// returns nullptr. Must be previously inserted by insertSSPDeclarations.
1627 /// Should be used only when getIRStackGuard returns nullptr.
1628 virtual Function
*getSSPStackGuardCheck(const Module
&M
) const;
1631 Value
*getDefaultSafeStackPointerLocation(IRBuilder
<> &IRB
,
1635 /// Returns the target-specific address of the unsafe stack pointer.
1636 virtual Value
*getSafeStackPointerLocation(IRBuilder
<> &IRB
) const;
1638 /// Returns the name of the symbol used to emit stack probes or the empty
1639 /// string if not applicable.
1640 virtual StringRef
getStackProbeSymbolName(MachineFunction
&MF
) const {
1644 /// Returns true if a cast between SrcAS and DestAS is a noop.
1645 virtual bool isNoopAddrSpaceCast(unsigned SrcAS
, unsigned DestAS
) const {
1649 /// Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g. we
1650 /// are happy to sink it into basic blocks. A cast may be free, but not
1651 /// necessarily a no-op. e.g. a free truncate from a 64-bit to 32-bit pointer.
1652 virtual bool isFreeAddrSpaceCast(unsigned SrcAS
, unsigned DestAS
) const {
1653 return isNoopAddrSpaceCast(SrcAS
, DestAS
);
1656 /// Return true if the pointer arguments to CI should be aligned by aligning
1657 /// the object whose address is being passed. If so then MinSize is set to the
1658 /// minimum size the object must be to be aligned and PrefAlign is set to the
1659 /// preferred alignment.
1660 virtual bool shouldAlignPointerArgs(CallInst
* /*CI*/, unsigned & /*MinSize*/,
1661 unsigned & /*PrefAlign*/) const {
1665 //===--------------------------------------------------------------------===//
1666 /// \name Helpers for TargetTransformInfo implementations
1669 /// Get the ISD node that corresponds to the Instruction class opcode.
1670 int InstructionOpcodeToISD(unsigned Opcode
) const;
1672 /// Estimate the cost of type-legalization and the legalized type.
1673 std::pair
<int, MVT
> getTypeLegalizationCost(const DataLayout
&DL
,
1678 //===--------------------------------------------------------------------===//
1679 /// \name Helpers for atomic expansion.
1682 /// Returns the maximum atomic operation size (in bits) supported by
1683 /// the backend. Atomic operations greater than this size (as well
1684 /// as ones that are not naturally aligned), will be expanded by
1685 /// AtomicExpandPass into an __atomic_* library call.
1686 unsigned getMaxAtomicSizeInBitsSupported() const {
1687 return MaxAtomicSizeInBitsSupported
;
1690 /// Returns the size of the smallest cmpxchg or ll/sc instruction
1691 /// the backend supports. Any smaller operations are widened in
1692 /// AtomicExpandPass.
1694 /// Note that *unlike* operations above the maximum size, atomic ops
1695 /// are still natively supported below the minimum; they just
1696 /// require a more complex expansion.
1697 unsigned getMinCmpXchgSizeInBits() const { return MinCmpXchgSizeInBits
; }
1699 /// Whether the target supports unaligned atomic operations.
1700 bool supportsUnalignedAtomics() const { return SupportsUnalignedAtomics
; }
1702 /// Whether AtomicExpandPass should automatically insert fences and reduce
1703 /// ordering for this atomic. This should be true for most architectures with
1704 /// weak memory ordering. Defaults to false.
1705 virtual bool shouldInsertFencesForAtomic(const Instruction
*I
) const {
1709 /// Perform a load-linked operation on Addr, returning a "Value *" with the
1710 /// corresponding pointee type. This may entail some non-trivial operations to
1711 /// truncate or reconstruct types that will be illegal in the backend. See
1712 /// ARMISelLowering for an example implementation.
1713 virtual Value
*emitLoadLinked(IRBuilder
<> &Builder
, Value
*Addr
,
1714 AtomicOrdering Ord
) const {
1715 llvm_unreachable("Load linked unimplemented on this target");
1718 /// Perform a store-conditional operation to Addr. Return the status of the
1719 /// store. This should be 0 if the store succeeded, non-zero otherwise.
1720 virtual Value
*emitStoreConditional(IRBuilder
<> &Builder
, Value
*Val
,
1721 Value
*Addr
, AtomicOrdering Ord
) const {
1722 llvm_unreachable("Store conditional unimplemented on this target");
1725 /// Perform a masked atomicrmw using a target-specific intrinsic. This
1726 /// represents the core LL/SC loop which will be lowered at a late stage by
1728 virtual Value
*emitMaskedAtomicRMWIntrinsic(IRBuilder
<> &Builder
,
1730 Value
*AlignedAddr
, Value
*Incr
,
1731 Value
*Mask
, Value
*ShiftAmt
,
1732 AtomicOrdering Ord
) const {
1733 llvm_unreachable("Masked atomicrmw expansion unimplemented on this target");
1736 /// Perform a masked cmpxchg using a target-specific intrinsic. This
1737 /// represents the core LL/SC loop which will be lowered at a late stage by
1739 virtual Value
*emitMaskedAtomicCmpXchgIntrinsic(
1740 IRBuilder
<> &Builder
, AtomicCmpXchgInst
*CI
, Value
*AlignedAddr
,
1741 Value
*CmpVal
, Value
*NewVal
, Value
*Mask
, AtomicOrdering Ord
) const {
1742 llvm_unreachable("Masked cmpxchg expansion unimplemented on this target");
1745 /// Inserts in the IR a target-specific intrinsic specifying a fence.
1746 /// It is called by AtomicExpandPass before expanding an
1747 /// AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad
1748 /// if shouldInsertFencesForAtomic returns true.
1750 /// Inst is the original atomic instruction, prior to other expansions that
1751 /// may be performed.
1753 /// This function should either return a nullptr, or a pointer to an IR-level
1754 /// Instruction*. Even complex fence sequences can be represented by a
1755 /// single Instruction* through an intrinsic to be lowered later.
1756 /// Backends should override this method to produce target-specific intrinsic
1757 /// for their fences.
1758 /// FIXME: Please note that the default implementation here in terms of
1759 /// IR-level fences exists for historical/compatibility reasons and is
1760 /// *unsound* ! Fences cannot, in general, be used to restore sequential
1761 /// consistency. For example, consider the following example:
1762 /// atomic<int> x = y = 0;
1763 /// int r1, r2, r3, r4;
1774 /// r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all
1775 /// seq_cst. But if they are lowered to monotonic accesses, no amount of
1776 /// IR-level fences can prevent it.
1778 virtual Instruction
*emitLeadingFence(IRBuilder
<> &Builder
, Instruction
*Inst
,
1779 AtomicOrdering Ord
) const {
1780 if (isReleaseOrStronger(Ord
) && Inst
->hasAtomicStore())
1781 return Builder
.CreateFence(Ord
);
1786 virtual Instruction
*emitTrailingFence(IRBuilder
<> &Builder
,
1788 AtomicOrdering Ord
) const {
1789 if (isAcquireOrStronger(Ord
))
1790 return Builder
.CreateFence(Ord
);
1796 // Emits code that executes when the comparison result in the ll/sc
1797 // expansion of a cmpxchg instruction is such that the store-conditional will
1798 // not execute. This makes it possible to balance out the load-linked with
1799 // a dedicated instruction, if desired.
1800 // E.g., on ARM, if ldrex isn't followed by strex, the exclusive monitor would
1801 // be unnecessarily held, except if clrex, inserted by this hook, is executed.
1802 virtual void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder
<> &Builder
) const {}
1804 /// Returns true if the given (atomic) store should be expanded by the
1805 /// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
1806 virtual bool shouldExpandAtomicStoreInIR(StoreInst
*SI
) const {
1810 /// Returns true if arguments should be sign-extended in lib calls.
1811 virtual bool shouldSignExtendTypeInLibCall(EVT Type
, bool IsSigned
) const {
1815 /// Returns how the given (atomic) load should be expanded by the
1816 /// IR-level AtomicExpand pass.
1817 virtual AtomicExpansionKind
shouldExpandAtomicLoadInIR(LoadInst
*LI
) const {
1818 return AtomicExpansionKind::None
;
1821 /// Returns how the given atomic cmpxchg should be expanded by the IR-level
1822 /// AtomicExpand pass.
1823 virtual AtomicExpansionKind
1824 shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst
*AI
) const {
1825 return AtomicExpansionKind::None
;
1828 /// Returns how the IR-level AtomicExpand pass should expand the given
1829 /// AtomicRMW, if at all. Default is to never expand.
1830 virtual AtomicExpansionKind
shouldExpandAtomicRMWInIR(AtomicRMWInst
*RMW
) const {
1831 return RMW
->isFloatingPointOperation() ?
1832 AtomicExpansionKind::CmpXChg
: AtomicExpansionKind::None
;
1835 /// On some platforms, an AtomicRMW that never actually modifies the value
1836 /// (such as fetch_add of 0) can be turned into a fence followed by an
1837 /// atomic load. This may sound useless, but it makes it possible for the
1838 /// processor to keep the cacheline shared, dramatically improving
1839 /// performance. And such idempotent RMWs are useful for implementing some
1840 /// kinds of locks, see for example (justification + benchmarks):
1841 /// http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf
1842 /// This method tries doing that transformation, returning the atomic load if
1843 /// it succeeds, and nullptr otherwise.
1844 /// If shouldExpandAtomicLoadInIR returns true on that load, it will undergo
1845 /// another round of expansion.
1847 lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst
*RMWI
) const {
1851 /// Returns how the platform's atomic operations are extended (ZERO_EXTEND,
1852 /// SIGN_EXTEND, or ANY_EXTEND).
1853 virtual ISD::NodeType
getExtendForAtomicOps() const {
1854 return ISD::ZERO_EXTEND
;
1859 /// Returns true if we should normalize
1860 /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
1861 /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely
1862 /// that it saves us from materializing N0 and N1 in an integer register.
1863 /// Targets that are able to perform and/or on flags should return false here.
1864 virtual bool shouldNormalizeToSelectSequence(LLVMContext
&Context
,
1866 // If a target has multiple condition registers, then it likely has logical
1867 // operations on those registers.
1868 if (hasMultipleConditionRegisters())
1870 // Only do the transform if the value won't be split into multiple
1872 LegalizeTypeAction Action
= getTypeAction(Context
, VT
);
1873 return Action
!= TypeExpandInteger
&& Action
!= TypeExpandFloat
&&
1874 Action
!= TypeSplitVector
;
1877 virtual bool isProfitableToCombineMinNumMaxNum(EVT VT
) const { return true; }
1879 /// Return true if a select of constants (select Cond, C1, C2) should be
1880 /// transformed into simple math ops with the condition value. For example:
1881 /// select Cond, C1, C1-1 --> add (zext Cond), C1-1
1882 virtual bool convertSelectOfConstantsToMath(EVT VT
) const {
1886 /// Return true if it is profitable to transform an integer
1887 /// multiplication-by-constant into simpler operations like shifts and adds.
1888 /// This may be true if the target does not directly support the
1889 /// multiplication operation for the specified type or the sequence of simpler
1890 /// ops is faster than the multiply.
1891 virtual bool decomposeMulByConstant(LLVMContext
&Context
,
1892 EVT VT
, SDValue C
) const {
1896 /// Return true if it is more correct/profitable to use strict FP_TO_INT
1897 /// conversion operations - canonicalizing the FP source value instead of
1898 /// converting all cases and then selecting based on value.
1899 /// This may be true if the target throws exceptions for out of bounds
1900 /// conversions or has fast FP CMOV.
1901 virtual bool shouldUseStrictFP_TO_INT(EVT FpVT
, EVT IntVT
,
1902 bool IsSigned
) const {
1906 //===--------------------------------------------------------------------===//
1907 // TargetLowering Configuration Methods - These methods should be invoked by
1908 // the derived class constructor to configure this object for the target.
1911 /// Specify how the target extends the result of integer and floating point
1912 /// boolean values from i1 to a wider type. See getBooleanContents.
1913 void setBooleanContents(BooleanContent Ty
) {
1914 BooleanContents
= Ty
;
1915 BooleanFloatContents
= Ty
;
1918 /// Specify how the target extends the result of integer and floating point
1919 /// boolean values from i1 to a wider type. See getBooleanContents.
1920 void setBooleanContents(BooleanContent IntTy
, BooleanContent FloatTy
) {
1921 BooleanContents
= IntTy
;
1922 BooleanFloatContents
= FloatTy
;
1925 /// Specify how the target extends the result of a vector boolean value from a
1926 /// vector of i1 to a wider type. See getBooleanContents.
1927 void setBooleanVectorContents(BooleanContent Ty
) {
1928 BooleanVectorContents
= Ty
;
1931 /// Specify the target scheduling preference.
1932 void setSchedulingPreference(Sched::Preference Pref
) {
1933 SchedPreferenceInfo
= Pref
;
1936 /// Indicate whether this target prefers to use _setjmp to implement
1937 /// llvm.setjmp or the version without _. Defaults to false.
1938 void setUseUnderscoreSetJmp(bool Val
) {
1939 UseUnderscoreSetJmp
= Val
;
1942 /// Indicate whether this target prefers to use _longjmp to implement
1943 /// llvm.longjmp or the version without _. Defaults to false.
1944 void setUseUnderscoreLongJmp(bool Val
) {
1945 UseUnderscoreLongJmp
= Val
;
1948 /// Indicate the minimum number of blocks to generate jump tables.
1949 void setMinimumJumpTableEntries(unsigned Val
);
1951 /// Indicate the maximum number of entries in jump tables.
1952 /// Set to zero to generate unlimited jump tables.
1953 void setMaximumJumpTableSize(unsigned);
1955 /// If set to a physical register, this specifies the register that
1956 /// llvm.savestack/llvm.restorestack should save and restore.
1957 void setStackPointerRegisterToSaveRestore(unsigned R
) {
1958 StackPointerRegisterToSaveRestore
= R
;
1961 /// Tells the code generator that the target has multiple (allocatable)
1962 /// condition registers that can be used to store the results of comparisons
1963 /// for use by selects and conditional branches. With multiple condition
1964 /// registers, the code generator will not aggressively sink comparisons into
1965 /// the blocks of their users.
1966 void setHasMultipleConditionRegisters(bool hasManyRegs
= true) {
1967 HasMultipleConditionRegisters
= hasManyRegs
;
1970 /// Tells the code generator that the target has BitExtract instructions.
1971 /// The code generator will aggressively sink "shift"s into the blocks of
1972 /// their users if the users will generate "and" instructions which can be
1973 /// combined with "shift" to BitExtract instructions.
1974 void setHasExtractBitsInsn(bool hasExtractInsn
= true) {
1975 HasExtractBitsInsn
= hasExtractInsn
;
1978 /// Tells the code generator not to expand logic operations on comparison
1979 /// predicates into separate sequences that increase the amount of flow
1981 void setJumpIsExpensive(bool isExpensive
= true);
1983 /// Tells the code generator which bitwidths to bypass.
1984 void addBypassSlowDiv(unsigned int SlowBitWidth
, unsigned int FastBitWidth
) {
1985 BypassSlowDivWidths
[SlowBitWidth
] = FastBitWidth
;
1988 /// Add the specified register class as an available regclass for the
1989 /// specified value type. This indicates the selector can handle values of
1990 /// that class natively.
1991 void addRegisterClass(MVT VT
, const TargetRegisterClass
*RC
) {
1992 assert((unsigned)VT
.SimpleTy
< array_lengthof(RegClassForVT
));
1993 RegClassForVT
[VT
.SimpleTy
] = RC
;
1996 /// Return the largest legal super-reg register class of the register class
1997 /// for the specified type and its associated "cost".
1998 virtual std::pair
<const TargetRegisterClass
*, uint8_t>
1999 findRepresentativeClass(const TargetRegisterInfo
*TRI
, MVT VT
) const;
2001 /// Once all of the register classes are added, this allows us to compute
2002 /// derived properties we expose.
2003 void computeRegisterProperties(const TargetRegisterInfo
*TRI
);
2005 /// Indicate that the specified operation does not work with the specified
2006 /// type and indicate what to do about it. Note that VT may refer to either
2007 /// the type of a result or that of an operand of Op.
2008 void setOperationAction(unsigned Op
, MVT VT
,
2009 LegalizeAction Action
) {
2010 assert(Op
< array_lengthof(OpActions
[0]) && "Table isn't big enough!");
2011 OpActions
[(unsigned)VT
.SimpleTy
][Op
] = Action
;
2014 /// Indicate that the specified load with extension does not work with the
2015 /// specified type and indicate what to do about it.
2016 void setLoadExtAction(unsigned ExtType
, MVT ValVT
, MVT MemVT
,
2017 LegalizeAction Action
) {
2018 assert(ExtType
< ISD::LAST_LOADEXT_TYPE
&& ValVT
.isValid() &&
2019 MemVT
.isValid() && "Table isn't big enough!");
2020 assert((unsigned)Action
< 0x10 && "too many bits for bitfield array");
2021 unsigned Shift
= 4 * ExtType
;
2022 LoadExtActions
[ValVT
.SimpleTy
][MemVT
.SimpleTy
] &= ~((uint16_t)0xF << Shift
);
2023 LoadExtActions
[ValVT
.SimpleTy
][MemVT
.SimpleTy
] |= (uint16_t)Action
<< Shift
;
2026 /// Indicate that the specified truncating store does not work with the
2027 /// specified type and indicate what to do about it.
2028 void setTruncStoreAction(MVT ValVT
, MVT MemVT
,
2029 LegalizeAction Action
) {
2030 assert(ValVT
.isValid() && MemVT
.isValid() && "Table isn't big enough!");
2031 TruncStoreActions
[(unsigned)ValVT
.SimpleTy
][MemVT
.SimpleTy
] = Action
;
2034 /// Indicate that the specified indexed load does or does not work with the
2035 /// specified type and indicate what to do abort it.
2037 /// NOTE: All indexed mode loads are initialized to Expand in
2038 /// TargetLowering.cpp
2039 void setIndexedLoadAction(unsigned IdxMode
, MVT VT
,
2040 LegalizeAction Action
) {
2041 assert(VT
.isValid() && IdxMode
< ISD::LAST_INDEXED_MODE
&&
2042 (unsigned)Action
< 0xf && "Table isn't big enough!");
2043 // Load action are kept in the upper half.
2044 IndexedModeActions
[(unsigned)VT
.SimpleTy
][IdxMode
] &= ~0xf0;
2045 IndexedModeActions
[(unsigned)VT
.SimpleTy
][IdxMode
] |= ((uint8_t)Action
) <<4;
2048 /// Indicate that the specified indexed store does or does not work with the
2049 /// specified type and indicate what to do about it.
2051 /// NOTE: All indexed mode stores are initialized to Expand in
2052 /// TargetLowering.cpp
2053 void setIndexedStoreAction(unsigned IdxMode
, MVT VT
,
2054 LegalizeAction Action
) {
2055 assert(VT
.isValid() && IdxMode
< ISD::LAST_INDEXED_MODE
&&
2056 (unsigned)Action
< 0xf && "Table isn't big enough!");
2057 // Store action are kept in the lower half.
2058 IndexedModeActions
[(unsigned)VT
.SimpleTy
][IdxMode
] &= ~0x0f;
2059 IndexedModeActions
[(unsigned)VT
.SimpleTy
][IdxMode
] |= ((uint8_t)Action
);
2062 /// Indicate that the specified condition code is or isn't supported on the
2063 /// target and indicate what to do about it.
2064 void setCondCodeAction(ISD::CondCode CC
, MVT VT
,
2065 LegalizeAction Action
) {
2066 assert(VT
.isValid() && (unsigned)CC
< array_lengthof(CondCodeActions
) &&
2067 "Table isn't big enough!");
2068 assert((unsigned)Action
< 0x10 && "too many bits for bitfield array");
2069 /// The lower 3 bits of the SimpleTy index into Nth 4bit set from the 32-bit
2070 /// value and the upper 29 bits index into the second dimension of the array
2071 /// to select what 32-bit value to use.
2072 uint32_t Shift
= 4 * (VT
.SimpleTy
& 0x7);
2073 CondCodeActions
[CC
][VT
.SimpleTy
>> 3] &= ~((uint32_t)0xF << Shift
);
2074 CondCodeActions
[CC
][VT
.SimpleTy
>> 3] |= (uint32_t)Action
<< Shift
;
2077 /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
2078 /// to trying a larger integer/fp until it can find one that works. If that
2079 /// default is insufficient, this method can be used by the target to override
2081 void AddPromotedToType(unsigned Opc
, MVT OrigVT
, MVT DestVT
) {
2082 PromoteToType
[std::make_pair(Opc
, OrigVT
.SimpleTy
)] = DestVT
.SimpleTy
;
2085 /// Convenience method to set an operation to Promote and specify the type
2086 /// in a single call.
2087 void setOperationPromotedToType(unsigned Opc
, MVT OrigVT
, MVT DestVT
) {
2088 setOperationAction(Opc
, OrigVT
, Promote
);
2089 AddPromotedToType(Opc
, OrigVT
, DestVT
);
2092 /// Targets should invoke this method for each target independent node that
2093 /// they want to provide a custom DAG combiner for by implementing the
2094 /// PerformDAGCombine virtual method.
2095 void setTargetDAGCombine(ISD::NodeType NT
) {
2096 assert(unsigned(NT
>> 3) < array_lengthof(TargetDAGCombineArray
));
2097 TargetDAGCombineArray
[NT
>> 3] |= 1 << (NT
&7);
2100 /// Set the target's minimum function alignment (in log2(bytes))
2101 void setMinFunctionAlignment(unsigned Align
) {
2102 MinFunctionAlignment
= Align
;
2105 /// Set the target's preferred function alignment. This should be set if
2106 /// there is a performance benefit to higher-than-minimum alignment (in
2108 void setPrefFunctionAlignment(unsigned Align
) {
2109 PrefFunctionAlignment
= Align
;
2112 /// Set the target's preferred loop alignment. Default alignment is zero, it
2113 /// means the target does not care about loop alignment. The alignment is
2114 /// specified in log2(bytes). The target may also override
2115 /// getPrefLoopAlignment to provide per-loop values.
2116 void setPrefLoopAlignment(unsigned Align
) {
2117 PrefLoopAlignment
= Align
;
2120 /// Set the minimum stack alignment of an argument (in log2(bytes)).
2121 void setMinStackArgumentAlignment(unsigned Align
) {
2122 MinStackArgumentAlignment
= Align
;
2125 /// Set the maximum atomic operation size supported by the
2126 /// backend. Atomic operations greater than this size (as well as
2127 /// ones that are not naturally aligned), will be expanded by
2128 /// AtomicExpandPass into an __atomic_* library call.
2129 void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits
) {
2130 MaxAtomicSizeInBitsSupported
= SizeInBits
;
2133 /// Sets the minimum cmpxchg or ll/sc size supported by the backend.
2134 void setMinCmpXchgSizeInBits(unsigned SizeInBits
) {
2135 MinCmpXchgSizeInBits
= SizeInBits
;
2138 /// Sets whether unaligned atomic operations are supported.
2139 void setSupportsUnalignedAtomics(bool UnalignedSupported
) {
2140 SupportsUnalignedAtomics
= UnalignedSupported
;
2144 //===--------------------------------------------------------------------===//
2145 // Addressing mode description hooks (used by LSR etc).
2148 /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
2149 /// instructions reading the address. This allows as much computation as
2150 /// possible to be done in the address mode for that operand. This hook lets
2151 /// targets also pass back when this should be done on intrinsics which
2153 virtual bool getAddrModeArguments(IntrinsicInst
* /*I*/,
2154 SmallVectorImpl
<Value
*> &/*Ops*/,
2155 Type
*&/*AccessTy*/) const {
2159 /// This represents an addressing mode of:
2160 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
2161 /// If BaseGV is null, there is no BaseGV.
2162 /// If BaseOffs is zero, there is no base offset.
2163 /// If HasBaseReg is false, there is no base register.
2164 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
2167 GlobalValue
*BaseGV
= nullptr;
2168 int64_t BaseOffs
= 0;
2169 bool HasBaseReg
= false;
2171 AddrMode() = default;
2174 /// Return true if the addressing mode represented by AM is legal for this
2175 /// target, for a load/store of the specified type.
2177 /// The type may be VoidTy, in which case only return true if the addressing
2178 /// mode is legal for a load/store of any legal type. TODO: Handle
2179 /// pre/postinc as well.
2181 /// If the address space cannot be determined, it will be -1.
2183 /// TODO: Remove default argument
2184 virtual bool isLegalAddressingMode(const DataLayout
&DL
, const AddrMode
&AM
,
2185 Type
*Ty
, unsigned AddrSpace
,
2186 Instruction
*I
= nullptr) const;
2188 /// Return the cost of the scaling factor used in the addressing mode
2189 /// represented by AM for this target, for a load/store of the specified type.
2191 /// If the AM is supported, the return value must be >= 0.
2192 /// If the AM is not supported, it returns a negative value.
2193 /// TODO: Handle pre/postinc as well.
2194 /// TODO: Remove default argument
2195 virtual int getScalingFactorCost(const DataLayout
&DL
, const AddrMode
&AM
,
2196 Type
*Ty
, unsigned AS
= 0) const {
2197 // Default: assume that any scaling factor used in a legal AM is free.
2198 if (isLegalAddressingMode(DL
, AM
, Ty
, AS
))
2203 /// Return true if the specified immediate is legal icmp immediate, that is
2204 /// the target has icmp instructions which can compare a register against the
2205 /// immediate without having to materialize the immediate into a register.
2206 virtual bool isLegalICmpImmediate(int64_t) const {
2210 /// Return true if the specified immediate is legal add immediate, that is the
2211 /// target has add instructions which can add a register with the immediate
2212 /// without having to materialize the immediate into a register.
2213 virtual bool isLegalAddImmediate(int64_t) const {
2217 /// Return true if the specified immediate is legal for the value input of a
2218 /// store instruction.
2219 virtual bool isLegalStoreImmediate(int64_t Value
) const {
2220 // Default implementation assumes that at least 0 works since it is likely
2221 // that a zero register exists or a zero immediate is allowed.
2225 /// Return true if it's significantly cheaper to shift a vector by a uniform
2226 /// scalar than by an amount which will vary across each lane. On x86, for
2227 /// example, there is a "psllw" instruction for the former case, but no simple
2228 /// instruction for a general "a << b" operation on vectors.
2229 virtual bool isVectorShiftByScalarCheap(Type
*Ty
) const {
2233 /// Returns true if the opcode is a commutative binary operation.
2234 virtual bool isCommutativeBinOp(unsigned Opcode
) const {
2235 // FIXME: This should get its info from the td file.
2245 case ISD::SMUL_LOHI
:
2246 case ISD::UMUL_LOHI
:
2260 case ISD::FMINNUM_IEEE
:
2261 case ISD::FMAXNUM_IEEE
:
2265 default: return false;
2269 /// Return true if the node is a math/logic binary operator.
2270 virtual bool isBinOp(unsigned Opcode
) const {
2271 // A commutative binop must be a binop.
2272 if (isCommutativeBinOp(Opcode
))
2274 // These are non-commutative binops.
2293 /// Return true if it's free to truncate a value of type FromTy to type
2294 /// ToTy. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
2295 /// by referencing its sub-register AX.
2296 /// Targets must return false when FromTy <= ToTy.
2297 virtual bool isTruncateFree(Type
*FromTy
, Type
*ToTy
) const {
2301 /// Return true if a truncation from FromTy to ToTy is permitted when deciding
2302 /// whether a call is in tail position. Typically this means that both results
2303 /// would be assigned to the same register or stack slot, but it could mean
2304 /// the target performs adequate checks of its own before proceeding with the
2305 /// tail call. Targets must return false when FromTy <= ToTy.
2306 virtual bool allowTruncateForTailCall(Type
*FromTy
, Type
*ToTy
) const {
2310 virtual bool isTruncateFree(EVT FromVT
, EVT ToVT
) const {
2314 virtual bool isProfitableToHoist(Instruction
*I
) const { return true; }
2316 /// Return true if the extension represented by \p I is free.
2317 /// Unlikely the is[Z|FP]ExtFree family which is based on types,
2318 /// this method can use the context provided by \p I to decide
2319 /// whether or not \p I is free.
2320 /// This method extends the behavior of the is[Z|FP]ExtFree family.
2321 /// In other words, if is[Z|FP]Free returns true, then this method
2322 /// returns true as well. The converse is not true.
2323 /// The target can perform the adequate checks by overriding isExtFreeImpl.
2324 /// \pre \p I must be a sign, zero, or fp extension.
2325 bool isExtFree(const Instruction
*I
) const {
2326 switch (I
->getOpcode()) {
2327 case Instruction::FPExt
:
2328 if (isFPExtFree(EVT::getEVT(I
->getType()),
2329 EVT::getEVT(I
->getOperand(0)->getType())))
2332 case Instruction::ZExt
:
2333 if (isZExtFree(I
->getOperand(0)->getType(), I
->getType()))
2336 case Instruction::SExt
:
2339 llvm_unreachable("Instruction is not an extension");
2341 return isExtFreeImpl(I
);
2344 /// Return true if \p Load and \p Ext can form an ExtLoad.
2345 /// For example, in AArch64
2346 /// %L = load i8, i8* %ptr
2347 /// %E = zext i8 %L to i32
2348 /// can be lowered into one load instruction
2350 bool isExtLoad(const LoadInst
*Load
, const Instruction
*Ext
,
2351 const DataLayout
&DL
) const {
2352 EVT VT
= getValueType(DL
, Ext
->getType());
2353 EVT LoadVT
= getValueType(DL
, Load
->getType());
2355 // If the load has other users and the truncate is not free, the ext
2356 // probably isn't free.
2357 if (!Load
->hasOneUse() && (isTypeLegal(LoadVT
) || !isTypeLegal(VT
)) &&
2358 !isTruncateFree(Ext
->getType(), Load
->getType()))
2361 // Check whether the target supports casts folded into loads.
2363 if (isa
<ZExtInst
>(Ext
))
2364 LType
= ISD::ZEXTLOAD
;
2366 assert(isa
<SExtInst
>(Ext
) && "Unexpected ext type!");
2367 LType
= ISD::SEXTLOAD
;
2370 return isLoadExtLegal(LType
, VT
, LoadVT
);
2373 /// Return true if any actual instruction that defines a value of type FromTy
2374 /// implicitly zero-extends the value to ToTy in the result register.
2376 /// The function should return true when it is likely that the truncate can
2377 /// be freely folded with an instruction defining a value of FromTy. If
2378 /// the defining instruction is unknown (because you're looking at a
2379 /// function argument, PHI, etc.) then the target may require an
2380 /// explicit truncate, which is not necessarily free, but this function
2381 /// does not deal with those cases.
2382 /// Targets must return false when FromTy >= ToTy.
2383 virtual bool isZExtFree(Type
*FromTy
, Type
*ToTy
) const {
2387 virtual bool isZExtFree(EVT FromTy
, EVT ToTy
) const {
2391 /// Return true if sign-extension from FromTy to ToTy is cheaper than
2393 virtual bool isSExtCheaperThanZExt(EVT FromTy
, EVT ToTy
) const {
2397 /// Return true if sinking I's operands to the same basic block as I is
2398 /// profitable, e.g. because the operands can be folded into a target
2399 /// instruction during instruction selection. After calling the function
2400 /// \p Ops contains the Uses to sink ordered by dominance (dominating users
2402 virtual bool shouldSinkOperands(Instruction
*I
,
2403 SmallVectorImpl
<Use
*> &Ops
) const {
2407 /// Return true if the target supplies and combines to a paired load
2408 /// two loaded values of type LoadedType next to each other in memory.
2409 /// RequiredAlignment gives the minimal alignment constraints that must be met
2410 /// to be able to select this paired load.
2412 /// This information is *not* used to generate actual paired loads, but it is
2413 /// used to generate a sequence of loads that is easier to combine into a
2415 /// For instance, something like this:
2416 /// a = load i64* addr
2417 /// b = trunc i64 a to i32
2418 /// c = lshr i64 a, 32
2419 /// d = trunc i64 c to i32
2420 /// will be optimized into:
2421 /// b = load i32* addr1
2422 /// d = load i32* addr2
2423 /// Where addr1 = addr2 +/- sizeof(i32).
2425 /// In other words, unless the target performs a post-isel load combining,
2426 /// this information should not be provided because it will generate more
2428 virtual bool hasPairedLoad(EVT
/*LoadedType*/,
2429 unsigned & /*RequiredAlignment*/) const {
2433 /// Return true if the target has a vector blend instruction.
2434 virtual bool hasVectorBlend() const { return false; }
2436 /// Get the maximum supported factor for interleaved memory accesses.
2437 /// Default to be the minimum interleave factor: 2.
2438 virtual unsigned getMaxSupportedInterleaveFactor() const { return 2; }
2440 /// Lower an interleaved load to target specific intrinsics. Return
2441 /// true on success.
2443 /// \p LI is the vector load instruction.
2444 /// \p Shuffles is the shufflevector list to DE-interleave the loaded vector.
2445 /// \p Indices is the corresponding indices for each shufflevector.
2446 /// \p Factor is the interleave factor.
2447 virtual bool lowerInterleavedLoad(LoadInst
*LI
,
2448 ArrayRef
<ShuffleVectorInst
*> Shuffles
,
2449 ArrayRef
<unsigned> Indices
,
2450 unsigned Factor
) const {
2454 /// Lower an interleaved store to target specific intrinsics. Return
2455 /// true on success.
2457 /// \p SI is the vector store instruction.
2458 /// \p SVI is the shufflevector to RE-interleave the stored vector.
2459 /// \p Factor is the interleave factor.
2460 virtual bool lowerInterleavedStore(StoreInst
*SI
, ShuffleVectorInst
*SVI
,
2461 unsigned Factor
) const {
2465 /// Return true if zero-extending the specific node Val to type VT2 is free
2466 /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
2467 /// because it's folded such as X86 zero-extending loads).
2468 virtual bool isZExtFree(SDValue Val
, EVT VT2
) const {
2469 return isZExtFree(Val
.getValueType(), VT2
);
2472 /// Return true if an fpext operation is free (for instance, because
2473 /// single-precision floating-point numbers are implicitly extended to
2474 /// double-precision).
2475 virtual bool isFPExtFree(EVT DestVT
, EVT SrcVT
) const {
2476 assert(SrcVT
.isFloatingPoint() && DestVT
.isFloatingPoint() &&
2477 "invalid fpext types");
2481 /// Return true if an fpext operation input to an \p Opcode operation is free
2482 /// (for instance, because half-precision floating-point numbers are
2483 /// implicitly extended to float-precision) for an FMA instruction.
2484 virtual bool isFPExtFoldable(unsigned Opcode
, EVT DestVT
, EVT SrcVT
) const {
2485 assert(DestVT
.isFloatingPoint() && SrcVT
.isFloatingPoint() &&
2486 "invalid fpext types");
2487 return isFPExtFree(DestVT
, SrcVT
);
2490 /// Return true if folding a vector load into ExtVal (a sign, zero, or any
2491 /// extend node) is profitable.
2492 virtual bool isVectorLoadExtDesirable(SDValue ExtVal
) const { return false; }
2494 /// Return true if an fneg operation is free to the point where it is never
2495 /// worthwhile to replace it with a bitwise operation.
2496 virtual bool isFNegFree(EVT VT
) const {
2497 assert(VT
.isFloatingPoint());
2501 /// Return true if an fabs operation is free to the point where it is never
2502 /// worthwhile to replace it with a bitwise operation.
2503 virtual bool isFAbsFree(EVT VT
) const {
2504 assert(VT
.isFloatingPoint());
2508 /// Return true if an FMA operation is faster than a pair of fmul and fadd
2509 /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
2510 /// returns true, otherwise fmuladd is expanded to fmul + fadd.
2512 /// NOTE: This may be called before legalization on types for which FMAs are
2513 /// not legal, but should return true if those types will eventually legalize
2514 /// to types that support FMAs. After legalization, it will only be called on
2515 /// types that support FMAs (via Legal or Custom actions)
2516 virtual bool isFMAFasterThanFMulAndFAdd(EVT
) const {
2520 /// Return true if it's profitable to narrow operations of type VT1 to
2521 /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
2523 virtual bool isNarrowingProfitable(EVT
/*VT1*/, EVT
/*VT2*/) const {
2527 /// Return true if it is beneficial to convert a load of a constant to
2528 /// just the constant itself.
2529 /// On some targets it might be more efficient to use a combination of
2530 /// arithmetic instructions to materialize the constant instead of loading it
2531 /// from a constant pool.
2532 virtual bool shouldConvertConstantLoadToIntImm(const APInt
&Imm
,
2537 /// Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type
2538 /// from this source type with this index. This is needed because
2539 /// EXTRACT_SUBVECTOR usually has custom lowering that depends on the index of
2540 /// the first element, and only the target knows which lowering is cheap.
2541 virtual bool isExtractSubvectorCheap(EVT ResVT
, EVT SrcVT
,
2542 unsigned Index
) const {
2546 /// Try to convert an extract element of a vector binary operation into an
2547 /// extract element followed by a scalar operation.
2548 virtual bool shouldScalarizeBinop(SDValue VecOp
) const {
2552 /// Return true if extraction of a scalar element from the given vector type
2553 /// at the given index is cheap. For example, if scalar operations occur on
2554 /// the same register file as vector operations, then an extract element may
2555 /// be a sub-register rename rather than an actual instruction.
2556 virtual bool isExtractVecEltCheap(EVT VT
, unsigned Index
) const {
2560 /// Try to convert math with an overflow comparison into the corresponding DAG
2561 /// node operation. Targets may want to override this independently of whether
2562 /// the operation is legal/custom for the given type because it may obscure
2563 /// matching of other patterns.
2564 virtual bool shouldFormOverflowOp(unsigned Opcode
, EVT VT
) const {
2565 // TODO: The default logic is inherited from code in CodeGenPrepare.
2566 // The opcode should not make a difference by default?
2567 if (Opcode
!= ISD::UADDO
)
2570 // Allow the transform as long as we have an integer type that is not
2571 // obviously illegal and unsupported.
2574 return VT
.isSimple() || !isOperationExpand(Opcode
, VT
);
2577 // Return true if it is profitable to use a scalar input to a BUILD_VECTOR
2578 // even if the vector itself has multiple uses.
2579 virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT
) const {
2583 // Return true if CodeGenPrepare should consider splitting large offset of a
2584 // GEP to make the GEP fit into the addressing mode and can be sunk into the
2585 // same blocks of its users.
2586 virtual bool shouldConsiderGEPOffsetSplit() const { return false; }
2588 //===--------------------------------------------------------------------===//
2589 // Runtime Library hooks
2592 /// Rename the default libcall routine name for the specified libcall.
2593 void setLibcallName(RTLIB::Libcall Call
, const char *Name
) {
2594 LibcallRoutineNames
[Call
] = Name
;
2597 /// Get the libcall routine name for the specified libcall.
2598 const char *getLibcallName(RTLIB::Libcall Call
) const {
2599 return LibcallRoutineNames
[Call
];
2602 /// Override the default CondCode to be used to test the result of the
2603 /// comparison libcall against zero.
2604 void setCmpLibcallCC(RTLIB::Libcall Call
, ISD::CondCode CC
) {
2605 CmpLibcallCCs
[Call
] = CC
;
2608 /// Get the CondCode that's to be used to test the result of the comparison
2609 /// libcall against zero.
2610 ISD::CondCode
getCmpLibcallCC(RTLIB::Libcall Call
) const {
2611 return CmpLibcallCCs
[Call
];
2614 /// Set the CallingConv that should be used for the specified libcall.
2615 void setLibcallCallingConv(RTLIB::Libcall Call
, CallingConv::ID CC
) {
2616 LibcallCallingConvs
[Call
] = CC
;
2619 /// Get the CallingConv that should be used for the specified libcall.
2620 CallingConv::ID
getLibcallCallingConv(RTLIB::Libcall Call
) const {
2621 return LibcallCallingConvs
[Call
];
2624 /// Execute target specific actions to finalize target lowering.
2625 /// This is used to set extra flags in MachineFrameInformation and freezing
2626 /// the set of reserved registers.
2627 /// The default implementation just freezes the set of reserved registers.
2628 virtual void finalizeLowering(MachineFunction
&MF
) const;
2631 const TargetMachine
&TM
;
2633 /// Tells the code generator that the target has multiple (allocatable)
2634 /// condition registers that can be used to store the results of comparisons
2635 /// for use by selects and conditional branches. With multiple condition
2636 /// registers, the code generator will not aggressively sink comparisons into
2637 /// the blocks of their users.
2638 bool HasMultipleConditionRegisters
;
2640 /// Tells the code generator that the target has BitExtract instructions.
2641 /// The code generator will aggressively sink "shift"s into the blocks of
2642 /// their users if the users will generate "and" instructions which can be
2643 /// combined with "shift" to BitExtract instructions.
2644 bool HasExtractBitsInsn
;
2646 /// Tells the code generator to bypass slow divide or remainder
2647 /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
2648 /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
2649 /// div/rem when the operands are positive and less than 256.
2650 DenseMap
<unsigned int, unsigned int> BypassSlowDivWidths
;
2652 /// Tells the code generator that it shouldn't generate extra flow control
2653 /// instructions and should attempt to combine flow control instructions via
2655 bool JumpIsExpensive
;
2657 /// This target prefers to use _setjmp to implement llvm.setjmp.
2659 /// Defaults to false.
2660 bool UseUnderscoreSetJmp
;
2662 /// This target prefers to use _longjmp to implement llvm.longjmp.
2664 /// Defaults to false.
2665 bool UseUnderscoreLongJmp
;
2667 /// Information about the contents of the high-bits in boolean values held in
2668 /// a type wider than i1. See getBooleanContents.
2669 BooleanContent BooleanContents
;
2671 /// Information about the contents of the high-bits in boolean values held in
2672 /// a type wider than i1. See getBooleanContents.
2673 BooleanContent BooleanFloatContents
;
2675 /// Information about the contents of the high-bits in boolean vector values
2676 /// when the element type is wider than i1. See getBooleanContents.
2677 BooleanContent BooleanVectorContents
;
2679 /// The target scheduling preference: shortest possible total cycles or lowest
2681 Sched::Preference SchedPreferenceInfo
;
2683 /// The minimum alignment that any argument on the stack needs to have.
2684 unsigned MinStackArgumentAlignment
;
2686 /// The minimum function alignment (used when optimizing for size, and to
2687 /// prevent explicitly provided alignment from leading to incorrect code).
2688 unsigned MinFunctionAlignment
;
2690 /// The preferred function alignment (used when alignment unspecified and
2691 /// optimizing for speed).
2692 unsigned PrefFunctionAlignment
;
2694 /// The preferred loop alignment.
2695 unsigned PrefLoopAlignment
;
2697 /// Size in bits of the maximum atomics size the backend supports.
2698 /// Accesses larger than this will be expanded by AtomicExpandPass.
2699 unsigned MaxAtomicSizeInBitsSupported
;
2701 /// Size in bits of the minimum cmpxchg or ll/sc operation the
2702 /// backend supports.
2703 unsigned MinCmpXchgSizeInBits
;
2705 /// This indicates if the target supports unaligned atomic operations.
2706 bool SupportsUnalignedAtomics
;
2708 /// If set to a physical register, this specifies the register that
2709 /// llvm.savestack/llvm.restorestack should save and restore.
2710 unsigned StackPointerRegisterToSaveRestore
;
2712 /// This indicates the default register class to use for each ValueType the
2713 /// target supports natively.
2714 const TargetRegisterClass
*RegClassForVT
[MVT::LAST_VALUETYPE
];
2715 unsigned char NumRegistersForVT
[MVT::LAST_VALUETYPE
];
2716 MVT RegisterTypeForVT
[MVT::LAST_VALUETYPE
];
2718 /// This indicates the "representative" register class to use for each
2719 /// ValueType the target supports natively. This information is used by the
2720 /// scheduler to track register pressure. By default, the representative
2721 /// register class is the largest legal super-reg register class of the
2722 /// register class of the specified type. e.g. On x86, i8, i16, and i32's
2723 /// representative class would be GR32.
2724 const TargetRegisterClass
*RepRegClassForVT
[MVT::LAST_VALUETYPE
];
2726 /// This indicates the "cost" of the "representative" register class for each
2727 /// ValueType. The cost is used by the scheduler to approximate register
2729 uint8_t RepRegClassCostForVT
[MVT::LAST_VALUETYPE
];
2731 /// For any value types we are promoting or expanding, this contains the value
2732 /// type that we are changing to. For Expanded types, this contains one step
2733 /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
2734 /// (e.g. i64 -> i16). For types natively supported by the system, this holds
2735 /// the same type (e.g. i32 -> i32).
2736 MVT TransformToType
[MVT::LAST_VALUETYPE
];
2738 /// For each operation and each value type, keep a LegalizeAction that
2739 /// indicates how instruction selection should deal with the operation. Most
2740 /// operations are Legal (aka, supported natively by the target), but
2741 /// operations that are not should be described. Note that operations on
2742 /// non-legal value types are not described here.
2743 LegalizeAction OpActions
[MVT::LAST_VALUETYPE
][ISD::BUILTIN_OP_END
];
2745 /// For each load extension type and each value type, keep a LegalizeAction
2746 /// that indicates how instruction selection should deal with a load of a
2747 /// specific value type and extension type. Uses 4-bits to store the action
2748 /// for each of the 4 load ext types.
2749 uint16_t LoadExtActions
[MVT::LAST_VALUETYPE
][MVT::LAST_VALUETYPE
];
2751 /// For each value type pair keep a LegalizeAction that indicates whether a
2752 /// truncating store of a specific value type and truncating type is legal.
2753 LegalizeAction TruncStoreActions
[MVT::LAST_VALUETYPE
][MVT::LAST_VALUETYPE
];
2755 /// For each indexed mode and each value type, keep a pair of LegalizeAction
2756 /// that indicates how instruction selection should deal with the load /
2759 /// The first dimension is the value_type for the reference. The second
2760 /// dimension represents the various modes for load store.
2761 uint8_t IndexedModeActions
[MVT::LAST_VALUETYPE
][ISD::LAST_INDEXED_MODE
];
2763 /// For each condition code (ISD::CondCode) keep a LegalizeAction that
2764 /// indicates how instruction selection should deal with the condition code.
2766 /// Because each CC action takes up 4 bits, we need to have the array size be
2767 /// large enough to fit all of the value types. This can be done by rounding
2768 /// up the MVT::LAST_VALUETYPE value to the next multiple of 8.
2769 uint32_t CondCodeActions
[ISD::SETCC_INVALID
][(MVT::LAST_VALUETYPE
+ 7) / 8];
2772 ValueTypeActionImpl ValueTypeActions
;
2775 LegalizeKind
getTypeConversion(LLVMContext
&Context
, EVT VT
) const;
2777 /// Targets can specify ISD nodes that they would like PerformDAGCombine
2778 /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
2781 TargetDAGCombineArray
[(ISD::BUILTIN_OP_END
+CHAR_BIT
-1)/CHAR_BIT
];
2783 /// For operations that must be promoted to a specific type, this holds the
2784 /// destination type. This map should be sparse, so don't hold it as an
2787 /// Targets add entries to this map with AddPromotedToType(..), clients access
2788 /// this with getTypeToPromoteTo(..).
2789 std::map
<std::pair
<unsigned, MVT::SimpleValueType
>, MVT::SimpleValueType
>
2792 /// Stores the name each libcall.
2793 const char *LibcallRoutineNames
[RTLIB::UNKNOWN_LIBCALL
+ 1];
2795 /// The ISD::CondCode that should be used to test the result of each of the
2796 /// comparison libcall against zero.
2797 ISD::CondCode CmpLibcallCCs
[RTLIB::UNKNOWN_LIBCALL
];
2799 /// Stores the CallingConv that should be used for each libcall.
2800 CallingConv::ID LibcallCallingConvs
[RTLIB::UNKNOWN_LIBCALL
];
2802 /// Set default libcall names and calling conventions.
2803 void InitLibcalls(const Triple
&TT
);
2806 /// Return true if the extension represented by \p I is free.
2807 /// \pre \p I is a sign, zero, or fp extension and
2808 /// is[Z|FP]ExtFree of the related types is not true.
2809 virtual bool isExtFreeImpl(const Instruction
*I
) const { return false; }
2811 /// Depth that GatherAllAliases should should continue looking for chain
2812 /// dependencies when trying to find a more preferable chain. As an
2813 /// approximation, this should be more than the number of consecutive stores
2814 /// expected to be merged.
2815 unsigned GatherAllAliasesMaxDepth
;
2817 /// \brief Specify maximum number of store instructions per memset call.
2819 /// When lowering \@llvm.memset this field specifies the maximum number of
2820 /// store operations that may be substituted for the call to memset. Targets
2821 /// must set this value based on the cost threshold for that target. Targets
2822 /// should assume that the memset will be done using as many of the largest
2823 /// store operations first, followed by smaller ones, if necessary, per
2824 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
2825 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
2826 /// store. This only applies to setting a constant array of a constant size.
2827 unsigned MaxStoresPerMemset
;
2828 /// Likewise for functions with the OptSize attribute.
2829 unsigned MaxStoresPerMemsetOptSize
;
2831 /// \brief Specify maximum number of store instructions per memcpy call.
2833 /// When lowering \@llvm.memcpy this field specifies the maximum number of
2834 /// store operations that may be substituted for a call to memcpy. Targets
2835 /// must set this value based on the cost threshold for that target. Targets
2836 /// should assume that the memcpy will be done using as many of the largest
2837 /// store operations first, followed by smaller ones, if necessary, per
2838 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
2839 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
2840 /// and one 1-byte store. This only applies to copying a constant array of
2842 unsigned MaxStoresPerMemcpy
;
2843 /// Likewise for functions with the OptSize attribute.
2844 unsigned MaxStoresPerMemcpyOptSize
;
2845 /// \brief Specify max number of store instructions to glue in inlined memcpy.
2847 /// When memcpy is inlined based on MaxStoresPerMemcpy, specify maximum number
2848 /// of store instructions to keep together. This helps in pairing and
2849 // vectorization later on.
2850 unsigned MaxGluedStoresPerMemcpy
= 0;
2852 /// \brief Specify maximum number of load instructions per memcmp call.
2854 /// When lowering \@llvm.memcmp this field specifies the maximum number of
2855 /// pairs of load operations that may be substituted for a call to memcmp.
2856 /// Targets must set this value based on the cost threshold for that target.
2857 /// Targets should assume that the memcmp will be done using as many of the
2858 /// largest load operations first, followed by smaller ones, if necessary, per
2859 /// alignment restrictions. For example, loading 7 bytes on a 32-bit machine
2860 /// with 32-bit alignment would result in one 4-byte load, a one 2-byte load
2861 /// and one 1-byte load. This only applies to copying a constant array of
2863 unsigned MaxLoadsPerMemcmp
;
2864 /// Likewise for functions with the OptSize attribute.
2865 unsigned MaxLoadsPerMemcmpOptSize
;
2867 /// \brief Specify maximum number of store instructions per memmove call.
2869 /// When lowering \@llvm.memmove this field specifies the maximum number of
2870 /// store instructions that may be substituted for a call to memmove. Targets
2871 /// must set this value based on the cost threshold for that target. Targets
2872 /// should assume that the memmove will be done using as many of the largest
2873 /// store operations first, followed by smaller ones, if necessary, per
2874 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
2875 /// with 8-bit alignment would result in nine 1-byte stores. This only
2876 /// applies to copying a constant array of constant size.
2877 unsigned MaxStoresPerMemmove
;
2878 /// Likewise for functions with the OptSize attribute.
2879 unsigned MaxStoresPerMemmoveOptSize
;
2881 /// Tells the code generator that select is more expensive than a branch if
2882 /// the branch is usually predicted right.
2883 bool PredictableSelectIsExpensive
;
2885 /// \see enableExtLdPromotion.
2886 bool EnableExtLdPromotion
;
2888 /// Return true if the value types that can be represented by the specified
2889 /// register class are all legal.
2890 bool isLegalRC(const TargetRegisterInfo
&TRI
,
2891 const TargetRegisterClass
&RC
) const;
2893 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
2894 /// sequence of memory operands that is recognized by PrologEpilogInserter.
2895 MachineBasicBlock
*emitPatchPoint(MachineInstr
&MI
,
2896 MachineBasicBlock
*MBB
) const;
2898 /// Replace/modify the XRay custom event operands with target-dependent
2900 MachineBasicBlock
*emitXRayCustomEvent(MachineInstr
&MI
,
2901 MachineBasicBlock
*MBB
) const;
2903 /// Replace/modify the XRay typed event operands with target-dependent
2905 MachineBasicBlock
*emitXRayTypedEvent(MachineInstr
&MI
,
2906 MachineBasicBlock
*MBB
) const;
2909 /// This class defines information used to lower LLVM code to legal SelectionDAG
2910 /// operators that the target instruction selector can accept natively.
2912 /// This class also defines callbacks that targets must implement to lower
2913 /// target-specific constructs to SelectionDAG operators.
2914 class TargetLowering
: public TargetLoweringBase
{
2916 struct DAGCombinerInfo
;
2917 struct MakeLibCallOptions
;
2919 TargetLowering(const TargetLowering
&) = delete;
2920 TargetLowering
&operator=(const TargetLowering
&) = delete;
2922 /// NOTE: The TargetMachine owns TLOF.
2923 explicit TargetLowering(const TargetMachine
&TM
);
2925 bool isPositionIndependent() const;
2927 virtual bool isSDNodeSourceOfDivergence(const SDNode
*N
,
2928 FunctionLoweringInfo
*FLI
,
2929 LegacyDivergenceAnalysis
*DA
) const {
2933 virtual bool isSDNodeAlwaysUniform(const SDNode
* N
) const {
2937 /// Returns true by value, base pointer and offset pointer and addressing mode
2938 /// by reference if the node's address can be legally represented as
2939 /// pre-indexed load / store address.
2940 virtual bool getPreIndexedAddressParts(SDNode
* /*N*/, SDValue
&/*Base*/,
2941 SDValue
&/*Offset*/,
2942 ISD::MemIndexedMode
&/*AM*/,
2943 SelectionDAG
&/*DAG*/) const {
2947 /// Returns true by value, base pointer and offset pointer and addressing mode
2948 /// by reference if this node can be combined with a load / store to form a
2949 /// post-indexed load / store.
2950 virtual bool getPostIndexedAddressParts(SDNode
* /*N*/, SDNode
* /*Op*/,
2952 SDValue
&/*Offset*/,
2953 ISD::MemIndexedMode
&/*AM*/,
2954 SelectionDAG
&/*DAG*/) const {
2958 /// Return the entry encoding for a jump table in the current function. The
2959 /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
2960 virtual unsigned getJumpTableEncoding() const;
2962 virtual const MCExpr
*
2963 LowerCustomJumpTableEntry(const MachineJumpTableInfo
* /*MJTI*/,
2964 const MachineBasicBlock
* /*MBB*/, unsigned /*uid*/,
2965 MCContext
&/*Ctx*/) const {
2966 llvm_unreachable("Need to implement this hook if target has custom JTIs");
2969 /// Returns relocation base for the given PIC jumptable.
2970 virtual SDValue
getPICJumpTableRelocBase(SDValue Table
,
2971 SelectionDAG
&DAG
) const;
2973 /// This returns the relocation base for the given PIC jumptable, the same as
2974 /// getPICJumpTableRelocBase, but as an MCExpr.
2975 virtual const MCExpr
*
2976 getPICJumpTableRelocBaseExpr(const MachineFunction
*MF
,
2977 unsigned JTI
, MCContext
&Ctx
) const;
2979 /// Return true if folding a constant offset with the given GlobalAddress is
2980 /// legal. It is frequently not legal in PIC relocation models.
2981 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode
*GA
) const;
2983 bool isInTailCallPosition(SelectionDAG
&DAG
, SDNode
*Node
,
2984 SDValue
&Chain
) const;
2986 void softenSetCCOperands(SelectionDAG
&DAG
, EVT VT
, SDValue
&NewLHS
,
2987 SDValue
&NewRHS
, ISD::CondCode
&CCCode
,
2988 const SDLoc
&DL
) const;
2990 /// Returns a pair of (return value, chain).
2991 /// It is an error to pass RTLIB::UNKNOWN_LIBCALL as \p LC.
2992 std::pair
<SDValue
, SDValue
> makeLibCall(SelectionDAG
&DAG
, RTLIB::Libcall LC
,
2993 EVT RetVT
, ArrayRef
<SDValue
> Ops
,
2994 MakeLibCallOptions CallOptions
,
2995 const SDLoc
&dl
) const;
2997 /// Check whether parameters to a call that are passed in callee saved
2998 /// registers are the same as from the calling function. This needs to be
2999 /// checked for tail call eligibility.
3000 bool parametersInCSRMatch(const MachineRegisterInfo
&MRI
,
3001 const uint32_t *CallerPreservedMask
,
3002 const SmallVectorImpl
<CCValAssign
> &ArgLocs
,
3003 const SmallVectorImpl
<SDValue
> &OutVals
) const;
3005 //===--------------------------------------------------------------------===//
3006 // TargetLowering Optimization Methods
3009 /// A convenience struct that encapsulates a DAG, and two SDValues for
3010 /// returning information from TargetLowering to its clients that want to
3012 struct TargetLoweringOpt
{
3019 explicit TargetLoweringOpt(SelectionDAG
&InDAG
,
3021 DAG(InDAG
), LegalTys(LT
), LegalOps(LO
) {}
3023 bool LegalTypes() const { return LegalTys
; }
3024 bool LegalOperations() const { return LegalOps
; }
3026 bool CombineTo(SDValue O
, SDValue N
) {
3033 /// Determines the optimal series of memory ops to replace the memset / memcpy.
3034 /// Return true if the number of memory ops is below the threshold (Limit).
3035 /// It returns the types of the sequence of memory ops to perform
3036 /// memset / memcpy by reference.
3037 bool findOptimalMemOpLowering(std::vector
<EVT
> &MemOps
,
3038 unsigned Limit
, uint64_t Size
,
3039 unsigned DstAlign
, unsigned SrcAlign
,
3044 unsigned DstAS
, unsigned SrcAS
,
3045 const AttributeList
&FuncAttributes
) const;
3047 /// Check to see if the specified operand of the specified instruction is a
3048 /// constant integer. If so, check to see if there are any bits set in the
3049 /// constant that are not demanded. If so, shrink the constant and return
3051 bool ShrinkDemandedConstant(SDValue Op
, const APInt
&Demanded
,
3052 TargetLoweringOpt
&TLO
) const;
3054 // Target hook to do target-specific const optimization, which is called by
3055 // ShrinkDemandedConstant. This function should return true if the target
3056 // doesn't want ShrinkDemandedConstant to further optimize the constant.
3057 virtual bool targetShrinkDemandedConstant(SDValue Op
, const APInt
&Demanded
,
3058 TargetLoweringOpt
&TLO
) const {
3062 /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This
3063 /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
3064 /// generalized for targets with other types of implicit widening casts.
3065 bool ShrinkDemandedOp(SDValue Op
, unsigned BitWidth
, const APInt
&Demanded
,
3066 TargetLoweringOpt
&TLO
) const;
3068 /// Look at Op. At this point, we know that only the DemandedBits bits of the
3069 /// result of Op are ever used downstream. If we can use this information to
3070 /// simplify Op, create a new simplified DAG node and return true, returning
3071 /// the original and new nodes in Old and New. Otherwise, analyze the
3072 /// expression and return a mask of KnownOne and KnownZero bits for the
3073 /// expression (used to simplify the caller). The KnownZero/One bits may only
3074 /// be accurate for those bits in the Demanded masks.
3075 /// \p AssumeSingleUse When this parameter is true, this function will
3076 /// attempt to simplify \p Op even if there are multiple uses.
3077 /// Callers are responsible for correctly updating the DAG based on the
3078 /// results of this function, because simply replacing replacing TLO.Old
3079 /// with TLO.New will be incorrect when this parameter is true and TLO.Old
3080 /// has multiple uses.
3081 bool SimplifyDemandedBits(SDValue Op
, const APInt
&DemandedBits
,
3082 const APInt
&DemandedElts
, KnownBits
&Known
,
3083 TargetLoweringOpt
&TLO
, unsigned Depth
= 0,
3084 bool AssumeSingleUse
= false) const;
3086 /// Helper wrapper around SimplifyDemandedBits, demanding all elements.
3087 /// Adds Op back to the worklist upon success.
3088 bool SimplifyDemandedBits(SDValue Op
, const APInt
&DemandedBits
,
3089 KnownBits
&Known
, TargetLoweringOpt
&TLO
,
3091 bool AssumeSingleUse
= false) const;
3093 /// Helper wrapper around SimplifyDemandedBits.
3094 /// Adds Op back to the worklist upon success.
3095 bool SimplifyDemandedBits(SDValue Op
, const APInt
&DemandedMask
,
3096 DAGCombinerInfo
&DCI
) const;
3098 /// More limited version of SimplifyDemandedBits that can be used to "look
3099 /// through" ops that don't contribute to the DemandedBits/DemandedElts -
3100 /// bitwise ops etc.
3101 SDValue
SimplifyMultipleUseDemandedBits(SDValue Op
, const APInt
&DemandedBits
,
3102 const APInt
&DemandedElts
,
3104 unsigned Depth
) const;
3106 /// Look at Vector Op. At this point, we know that only the DemandedElts
3107 /// elements of the result of Op are ever used downstream. If we can use
3108 /// this information to simplify Op, create a new simplified DAG node and
3109 /// return true, storing the original and new nodes in TLO.
3110 /// Otherwise, analyze the expression and return a mask of KnownUndef and
3111 /// KnownZero elements for the expression (used to simplify the caller).
3112 /// The KnownUndef/Zero elements may only be accurate for those bits
3113 /// in the DemandedMask.
3114 /// \p AssumeSingleUse When this parameter is true, this function will
3115 /// attempt to simplify \p Op even if there are multiple uses.
3116 /// Callers are responsible for correctly updating the DAG based on the
3117 /// results of this function, because simply replacing replacing TLO.Old
3118 /// with TLO.New will be incorrect when this parameter is true and TLO.Old
3119 /// has multiple uses.
3120 bool SimplifyDemandedVectorElts(SDValue Op
, const APInt
&DemandedEltMask
,
3121 APInt
&KnownUndef
, APInt
&KnownZero
,
3122 TargetLoweringOpt
&TLO
, unsigned Depth
= 0,
3123 bool AssumeSingleUse
= false) const;
3125 /// Helper wrapper around SimplifyDemandedVectorElts.
3126 /// Adds Op back to the worklist upon success.
3127 bool SimplifyDemandedVectorElts(SDValue Op
, const APInt
&DemandedElts
,
3128 APInt
&KnownUndef
, APInt
&KnownZero
,
3129 DAGCombinerInfo
&DCI
) const;
3131 /// Determine which of the bits specified in Mask are known to be either zero
3132 /// or one and return them in the KnownZero/KnownOne bitsets. The DemandedElts
3133 /// argument allows us to only collect the known bits that are shared by the
3134 /// requested vector elements.
3135 virtual void computeKnownBitsForTargetNode(const SDValue Op
,
3137 const APInt
&DemandedElts
,
3138 const SelectionDAG
&DAG
,
3139 unsigned Depth
= 0) const;
3140 /// Determine which of the bits specified in Mask are known to be either zero
3141 /// or one and return them in the KnownZero/KnownOne bitsets. The DemandedElts
3142 /// argument allows us to only collect the known bits that are shared by the
3143 /// requested vector elements. This is for GISel.
3144 virtual void computeKnownBitsForTargetInstr(Register R
, KnownBits
&Known
,
3145 const APInt
&DemandedElts
,
3146 const MachineRegisterInfo
&MRI
,
3147 unsigned Depth
= 0) const;
3149 /// Determine which of the bits of FrameIndex \p FIOp are known to be 0.
3150 /// Default implementation computes low bits based on alignment
3151 /// information. This should preserve known bits passed into it.
3152 virtual void computeKnownBitsForFrameIndex(const SDValue FIOp
,
3154 const APInt
&DemandedElts
,
3155 const SelectionDAG
&DAG
,
3156 unsigned Depth
= 0) const;
3158 /// This method can be implemented by targets that want to expose additional
3159 /// information about sign bits to the DAG Combiner. The DemandedElts
3160 /// argument allows us to only collect the minimum sign bits that are shared
3161 /// by the requested vector elements.
3162 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op
,
3163 const APInt
&DemandedElts
,
3164 const SelectionDAG
&DAG
,
3165 unsigned Depth
= 0) const;
3167 /// Attempt to simplify any target nodes based on the demanded vector
3168 /// elements, returning true on success. Otherwise, analyze the expression and
3169 /// return a mask of KnownUndef and KnownZero elements for the expression
3170 /// (used to simplify the caller). The KnownUndef/Zero elements may only be
3171 /// accurate for those bits in the DemandedMask.
3172 virtual bool SimplifyDemandedVectorEltsForTargetNode(
3173 SDValue Op
, const APInt
&DemandedElts
, APInt
&KnownUndef
,
3174 APInt
&KnownZero
, TargetLoweringOpt
&TLO
, unsigned Depth
= 0) const;
3176 /// Attempt to simplify any target nodes based on the demanded bits/elts,
3177 /// returning true on success. Otherwise, analyze the
3178 /// expression and return a mask of KnownOne and KnownZero bits for the
3179 /// expression (used to simplify the caller). The KnownZero/One bits may only
3180 /// be accurate for those bits in the Demanded masks.
3181 virtual bool SimplifyDemandedBitsForTargetNode(SDValue Op
,
3182 const APInt
&DemandedBits
,
3183 const APInt
&DemandedElts
,
3185 TargetLoweringOpt
&TLO
,
3186 unsigned Depth
= 0) const;
3188 /// More limited version of SimplifyDemandedBits that can be used to "look
3189 /// through" ops that don't contribute to the DemandedBits/DemandedElts -
3190 /// bitwise ops etc.
3191 virtual SDValue
SimplifyMultipleUseDemandedBitsForTargetNode(
3192 SDValue Op
, const APInt
&DemandedBits
, const APInt
&DemandedElts
,
3193 SelectionDAG
&DAG
, unsigned Depth
) const;
3195 /// This method returns the constant pool value that will be loaded by LD.
3196 /// NOTE: You must check for implicit extensions of the constant by LD.
3197 virtual const Constant
*getTargetConstantFromLoad(LoadSDNode
*LD
) const;
3199 /// If \p SNaN is false, \returns true if \p Op is known to never be any
3200 /// NaN. If \p sNaN is true, returns if \p Op is known to never be a signaling
3202 virtual bool isKnownNeverNaNForTargetNode(SDValue Op
,
3203 const SelectionDAG
&DAG
,
3205 unsigned Depth
= 0) const;
3206 struct DAGCombinerInfo
{
3207 void *DC
; // The DAG Combiner object.
3209 bool CalledByLegalizer
;
3214 DAGCombinerInfo(SelectionDAG
&dag
, CombineLevel level
, bool cl
, void *dc
)
3215 : DC(dc
), Level(level
), CalledByLegalizer(cl
), DAG(dag
) {}
3217 bool isBeforeLegalize() const { return Level
== BeforeLegalizeTypes
; }
3218 bool isBeforeLegalizeOps() const { return Level
< AfterLegalizeVectorOps
; }
3219 bool isAfterLegalizeDAG() const {
3220 return Level
== AfterLegalizeDAG
;
3222 CombineLevel
getDAGCombineLevel() { return Level
; }
3223 bool isCalledByLegalizer() const { return CalledByLegalizer
; }
3225 void AddToWorklist(SDNode
*N
);
3226 SDValue
CombineTo(SDNode
*N
, ArrayRef
<SDValue
> To
, bool AddTo
= true);
3227 SDValue
CombineTo(SDNode
*N
, SDValue Res
, bool AddTo
= true);
3228 SDValue
CombineTo(SDNode
*N
, SDValue Res0
, SDValue Res1
, bool AddTo
= true);
3230 void CommitTargetLoweringOpt(const TargetLoweringOpt
&TLO
);
3233 /// Return if the N is a constant or constant vector equal to the true value
3234 /// from getBooleanContents().
3235 bool isConstTrueVal(const SDNode
*N
) const;
3237 /// Return if the N is a constant or constant vector equal to the false value
3238 /// from getBooleanContents().
3239 bool isConstFalseVal(const SDNode
*N
) const;
3241 /// Return if \p N is a True value when extended to \p VT.
3242 bool isExtendedTrueVal(const ConstantSDNode
*N
, EVT VT
, bool SExt
) const;
3244 /// Try to simplify a setcc built with the specified operands and cc. If it is
3245 /// unable to simplify it, return a null SDValue.
3246 SDValue
SimplifySetCC(EVT VT
, SDValue N0
, SDValue N1
, ISD::CondCode Cond
,
3247 bool foldBooleans
, DAGCombinerInfo
&DCI
,
3248 const SDLoc
&dl
) const;
3250 // For targets which wrap address, unwrap for analysis.
3251 virtual SDValue
unwrapAddress(SDValue N
) const { return N
; }
3253 /// Returns true (and the GlobalValue and the offset) if the node is a
3254 /// GlobalAddress + offset.
3256 isGAPlusOffset(SDNode
*N
, const GlobalValue
* &GA
, int64_t &Offset
) const;
3258 /// This method will be invoked for all target nodes and for any
3259 /// target-independent nodes that the target has registered with invoke it
3262 /// The semantics are as follows:
3264 /// SDValue.Val == 0 - No change was made
3265 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
3266 /// otherwise - N should be replaced by the returned Operand.
3268 /// In addition, methods provided by DAGCombinerInfo may be used to perform
3269 /// more complex transformations.
3271 virtual SDValue
PerformDAGCombine(SDNode
*N
, DAGCombinerInfo
&DCI
) const;
3273 /// Return true if it is profitable to move this shift by a constant amount
3274 /// though its operand, adjusting any immediate operands as necessary to
3275 /// preserve semantics. This transformation may not be desirable if it
3276 /// disrupts a particularly auspicious target-specific tree (e.g. bitfield
3277 /// extraction in AArch64). By default, it returns true.
3279 /// @param N the shift node
3280 /// @param Level the current DAGCombine legalization level.
3281 virtual bool isDesirableToCommuteWithShift(const SDNode
*N
,
3282 CombineLevel Level
) const {
3286 // Return true if it is profitable to combine a BUILD_VECTOR with a stride-pattern
3287 // to a shuffle and a truncate.
3288 // Example of such a combine:
3289 // v4i32 build_vector((extract_elt V, 1),
3290 // (extract_elt V, 3),
3291 // (extract_elt V, 5),
3292 // (extract_elt V, 7))
3294 // v4i32 truncate (bitcast (shuffle<1,u,3,u,5,u,7,u> V, u) to v4i64)
3295 virtual bool isDesirableToCombineBuildVectorToShuffleTruncate(
3296 ArrayRef
<int> ShuffleMask
, EVT SrcVT
, EVT TruncVT
) const {
3300 /// Return true if the target has native support for the specified value type
3301 /// and it is 'desirable' to use the type for the given node type. e.g. On x86
3302 /// i16 is legal, but undesirable since i16 instruction encodings are longer
3303 /// and some i16 instructions are slow.
3304 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT
) const {
3305 // By default, assume all legal types are desirable.
3306 return isTypeLegal(VT
);
3309 /// Return true if it is profitable for dag combiner to transform a floating
3310 /// point op of specified opcode to a equivalent op of an integer
3311 /// type. e.g. f32 load -> i32 load can be profitable on ARM.
3312 virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
3317 /// This method query the target whether it is beneficial for dag combiner to
3318 /// promote the specified node. If true, it should return the desired
3319 /// promotion type by reference.
3320 virtual bool IsDesirableToPromoteOp(SDValue
/*Op*/, EVT
&/*PVT*/) const {
3324 /// Return true if the target supports swifterror attribute. It optimizes
3325 /// loads and stores to reading and writing a specific register.
3326 virtual bool supportSwiftError() const {
3330 /// Return true if the target supports that a subset of CSRs for the given
3331 /// machine function is handled explicitly via copies.
3332 virtual bool supportSplitCSR(MachineFunction
*MF
) const {
3336 /// Perform necessary initialization to handle a subset of CSRs explicitly
3337 /// via copies. This function is called at the beginning of instruction
3339 virtual void initializeSplitCSR(MachineBasicBlock
*Entry
) const {
3340 llvm_unreachable("Not Implemented");
3343 /// Insert explicit copies in entry and exit blocks. We copy a subset of
3344 /// CSRs to virtual registers in the entry block, and copy them back to
3345 /// physical registers in the exit blocks. This function is called at the end
3346 /// of instruction selection.
3347 virtual void insertCopiesSplitCSR(
3348 MachineBasicBlock
*Entry
,
3349 const SmallVectorImpl
<MachineBasicBlock
*> &Exits
) const {
3350 llvm_unreachable("Not Implemented");
3353 //===--------------------------------------------------------------------===//
3354 // Lowering methods - These methods must be implemented by targets so that
3355 // the SelectionDAGBuilder code knows how to lower these.
3358 /// This hook must be implemented to lower the incoming (formal) arguments,
3359 /// described by the Ins array, into the specified DAG. The implementation
3360 /// should fill in the InVals array with legal-type argument values, and
3361 /// return the resulting token chain value.
3362 virtual SDValue
LowerFormalArguments(
3363 SDValue
/*Chain*/, CallingConv::ID
/*CallConv*/, bool /*isVarArg*/,
3364 const SmallVectorImpl
<ISD::InputArg
> & /*Ins*/, const SDLoc
& /*dl*/,
3365 SelectionDAG
& /*DAG*/, SmallVectorImpl
<SDValue
> & /*InVals*/) const {
3366 llvm_unreachable("Not Implemented");
3369 /// This structure contains all information that is necessary for lowering
3370 /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
3371 /// needs to lower a call, and targets will see this struct in their LowerCall
3373 struct CallLoweringInfo
{
3375 Type
*RetTy
= nullptr;
3380 bool DoesNotReturn
: 1;
3381 bool IsReturnValueUsed
: 1;
3382 bool IsConvergent
: 1;
3383 bool IsPatchPoint
: 1;
3385 // IsTailCall should be modified by implementations of
3386 // TargetLowering::LowerCall that perform tail call conversions.
3387 bool IsTailCall
= false;
3389 // Is Call lowering done post SelectionDAG type legalization.
3390 bool IsPostTypeLegalization
= false;
3392 unsigned NumFixedArgs
= -1;
3393 CallingConv::ID CallConv
= CallingConv::C
;
3398 ImmutableCallSite CS
;
3399 SmallVector
<ISD::OutputArg
, 32> Outs
;
3400 SmallVector
<SDValue
, 32> OutVals
;
3401 SmallVector
<ISD::InputArg
, 32> Ins
;
3402 SmallVector
<SDValue
, 4> InVals
;
3404 CallLoweringInfo(SelectionDAG
&DAG
)
3405 : RetSExt(false), RetZExt(false), IsVarArg(false), IsInReg(false),
3406 DoesNotReturn(false), IsReturnValueUsed(true), IsConvergent(false),
3407 IsPatchPoint(false), DAG(DAG
) {}
3409 CallLoweringInfo
&setDebugLoc(const SDLoc
&dl
) {
3414 CallLoweringInfo
&setChain(SDValue InChain
) {
3419 // setCallee with target/module-specific attributes
3420 CallLoweringInfo
&setLibCallee(CallingConv::ID CC
, Type
*ResultType
,
3421 SDValue Target
, ArgListTy
&&ArgsList
) {
3425 NumFixedArgs
= ArgsList
.size();
3426 Args
= std::move(ArgsList
);
3428 DAG
.getTargetLoweringInfo().markLibCallAttributes(
3429 &(DAG
.getMachineFunction()), CC
, Args
);
3433 CallLoweringInfo
&setCallee(CallingConv::ID CC
, Type
*ResultType
,
3434 SDValue Target
, ArgListTy
&&ArgsList
) {
3438 NumFixedArgs
= ArgsList
.size();
3439 Args
= std::move(ArgsList
);
3443 CallLoweringInfo
&setCallee(Type
*ResultType
, FunctionType
*FTy
,
3444 SDValue Target
, ArgListTy
&&ArgsList
,
3445 ImmutableCallSite Call
) {
3448 IsInReg
= Call
.hasRetAttr(Attribute::InReg
);
3450 Call
.doesNotReturn() ||
3451 (!Call
.isInvoke() &&
3452 isa
<UnreachableInst
>(Call
.getInstruction()->getNextNode()));
3453 IsVarArg
= FTy
->isVarArg();
3454 IsReturnValueUsed
= !Call
.getInstruction()->use_empty();
3455 RetSExt
= Call
.hasRetAttr(Attribute::SExt
);
3456 RetZExt
= Call
.hasRetAttr(Attribute::ZExt
);
3460 CallConv
= Call
.getCallingConv();
3461 NumFixedArgs
= FTy
->getNumParams();
3462 Args
= std::move(ArgsList
);
3469 CallLoweringInfo
&setInRegister(bool Value
= true) {
3474 CallLoweringInfo
&setNoReturn(bool Value
= true) {
3475 DoesNotReturn
= Value
;
3479 CallLoweringInfo
&setVarArg(bool Value
= true) {
3484 CallLoweringInfo
&setTailCall(bool Value
= true) {
3489 CallLoweringInfo
&setDiscardResult(bool Value
= true) {
3490 IsReturnValueUsed
= !Value
;
3494 CallLoweringInfo
&setConvergent(bool Value
= true) {
3495 IsConvergent
= Value
;
3499 CallLoweringInfo
&setSExtResult(bool Value
= true) {
3504 CallLoweringInfo
&setZExtResult(bool Value
= true) {
3509 CallLoweringInfo
&setIsPatchPoint(bool Value
= true) {
3510 IsPatchPoint
= Value
;
3514 CallLoweringInfo
&setIsPostTypeLegalization(bool Value
=true) {
3515 IsPostTypeLegalization
= Value
;
3519 ArgListTy
&getArgs() {
3524 /// This structure is used to pass arguments to makeLibCall function.
3525 struct MakeLibCallOptions
{
3527 bool DoesNotReturn
: 1;
3528 bool IsReturnValueUsed
: 1;
3529 bool IsPostTypeLegalization
: 1;
3531 MakeLibCallOptions()
3532 : IsSExt(false), DoesNotReturn(false), IsReturnValueUsed(true),
3533 IsPostTypeLegalization(false) {}
3535 MakeLibCallOptions
&setSExt(bool Value
= true) {
3540 MakeLibCallOptions
&setNoReturn(bool Value
= true) {
3541 DoesNotReturn
= Value
;
3545 MakeLibCallOptions
&setDiscardResult(bool Value
= true) {
3546 IsReturnValueUsed
= !Value
;
3550 MakeLibCallOptions
&setIsPostTypeLegalization(bool Value
= true) {
3551 IsPostTypeLegalization
= Value
;
3556 /// This function lowers an abstract call to a function into an actual call.
3557 /// This returns a pair of operands. The first element is the return value
3558 /// for the function (if RetTy is not VoidTy). The second element is the
3559 /// outgoing token chain. It calls LowerCall to do the actual lowering.
3560 std::pair
<SDValue
, SDValue
> LowerCallTo(CallLoweringInfo
&CLI
) const;
3562 /// This hook must be implemented to lower calls into the specified
3563 /// DAG. The outgoing arguments to the call are described by the Outs array,
3564 /// and the values to be returned by the call are described by the Ins
3565 /// array. The implementation should fill in the InVals array with legal-type
3566 /// return values from the call, and return the resulting token chain value.
3568 LowerCall(CallLoweringInfo
&/*CLI*/,
3569 SmallVectorImpl
<SDValue
> &/*InVals*/) const {
3570 llvm_unreachable("Not Implemented");
3573 /// Target-specific cleanup for formal ByVal parameters.
3574 virtual void HandleByVal(CCState
*, unsigned &, unsigned) const {}
3576 /// This hook should be implemented to check whether the return values
3577 /// described by the Outs array can fit into the return registers. If false
3578 /// is returned, an sret-demotion is performed.
3579 virtual bool CanLowerReturn(CallingConv::ID
/*CallConv*/,
3580 MachineFunction
&/*MF*/, bool /*isVarArg*/,
3581 const SmallVectorImpl
<ISD::OutputArg
> &/*Outs*/,
3582 LLVMContext
&/*Context*/) const
3584 // Return true by default to get preexisting behavior.
3588 /// This hook must be implemented to lower outgoing return values, described
3589 /// by the Outs array, into the specified DAG. The implementation should
3590 /// return the resulting token chain value.
3591 virtual SDValue
LowerReturn(SDValue
/*Chain*/, CallingConv::ID
/*CallConv*/,
3593 const SmallVectorImpl
<ISD::OutputArg
> & /*Outs*/,
3594 const SmallVectorImpl
<SDValue
> & /*OutVals*/,
3595 const SDLoc
& /*dl*/,
3596 SelectionDAG
& /*DAG*/) const {
3597 llvm_unreachable("Not Implemented");
3600 /// Return true if result of the specified node is used by a return node
3601 /// only. It also compute and return the input chain for the tail call.
3603 /// This is used to determine whether it is possible to codegen a libcall as
3604 /// tail call at legalization time.
3605 virtual bool isUsedByReturnOnly(SDNode
*, SDValue
&/*Chain*/) const {
3609 /// Return true if the target may be able emit the call instruction as a tail
3610 /// call. This is used by optimization passes to determine if it's profitable
3611 /// to duplicate return instructions to enable tailcall optimization.
3612 virtual bool mayBeEmittedAsTailCall(const CallInst
*) const {
3616 /// Return the builtin name for the __builtin___clear_cache intrinsic
3617 /// Default is to invoke the clear cache library call
3618 virtual const char * getClearCacheBuiltinName() const {
3619 return "__clear_cache";
3622 /// Return the register ID of the name passed in. Used by named register
3623 /// global variables extension. There is no target-independent behaviour
3624 /// so the default action is to bail.
3625 virtual unsigned getRegisterByName(const char* RegName
, EVT VT
,
3626 SelectionDAG
&DAG
) const {
3627 report_fatal_error("Named registers not implemented for this target");
3630 /// Return the type that should be used to zero or sign extend a
3631 /// zeroext/signext integer return value. FIXME: Some C calling conventions
3632 /// require the return type to be promoted, but this is not true all the time,
3633 /// e.g. i1/i8/i16 on x86/x86_64. It is also not necessary for non-C calling
3634 /// conventions. The frontend should handle this and include all of the
3635 /// necessary information.
3636 virtual EVT
getTypeForExtReturn(LLVMContext
&Context
, EVT VT
,
3637 ISD::NodeType
/*ExtendKind*/) const {
3638 EVT MinVT
= getRegisterType(Context
, MVT::i32
);
3639 return VT
.bitsLT(MinVT
) ? MinVT
: VT
;
3642 /// For some targets, an LLVM struct type must be broken down into multiple
3643 /// simple types, but the calling convention specifies that the entire struct
3644 /// must be passed in a block of consecutive registers.
3646 functionArgumentNeedsConsecutiveRegisters(Type
*Ty
, CallingConv::ID CallConv
,
3647 bool isVarArg
) const {
3651 /// For most targets, an LLVM type must be broken down into multiple
3652 /// smaller types. Usually the halves are ordered according to the endianness
3653 /// but for some platform that would break. So this method will default to
3654 /// matching the endianness but can be overridden.
3656 shouldSplitFunctionArgumentsAsLittleEndian(const DataLayout
&DL
) const {
3657 return DL
.isLittleEndian();
3660 /// Returns a 0 terminated array of registers that can be safely used as
3661 /// scratch registers.
3662 virtual const MCPhysReg
*getScratchRegisters(CallingConv::ID CC
) const {
3666 /// This callback is used to prepare for a volatile or atomic load.
3667 /// It takes a chain node as input and returns the chain for the load itself.
3669 /// Having a callback like this is necessary for targets like SystemZ,
3670 /// which allows a CPU to reuse the result of a previous load indefinitely,
3671 /// even if a cache-coherent store is performed by another CPU. The default
3672 /// implementation does nothing.
3673 virtual SDValue
prepareVolatileOrAtomicLoad(SDValue Chain
, const SDLoc
&DL
,
3674 SelectionDAG
&DAG
) const {
3678 /// This callback is used to inspect load/store instructions and add
3679 /// target-specific MachineMemOperand flags to them. The default
3680 /// implementation does nothing.
3681 virtual MachineMemOperand::Flags
getMMOFlags(const Instruction
&I
) const {
3682 return MachineMemOperand::MONone
;
3685 /// This callback is invoked by the type legalizer to legalize nodes with an
3686 /// illegal operand type but legal result types. It replaces the
3687 /// LowerOperation callback in the type Legalizer. The reason we can not do
3688 /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
3689 /// use this callback.
3691 /// TODO: Consider merging with ReplaceNodeResults.
3693 /// The target places new result values for the node in Results (their number
3694 /// and types must exactly match those of the original return values of
3695 /// the node), or leaves Results empty, which indicates that the node is not
3696 /// to be custom lowered after all.
3697 /// The default implementation calls LowerOperation.
3698 virtual void LowerOperationWrapper(SDNode
*N
,
3699 SmallVectorImpl
<SDValue
> &Results
,
3700 SelectionDAG
&DAG
) const;
3702 /// This callback is invoked for operations that are unsupported by the
3703 /// target, which are registered to use 'custom' lowering, and whose defined
3704 /// values are all legal. If the target has no operations that require custom
3705 /// lowering, it need not implement this. The default implementation of this
3707 virtual SDValue
LowerOperation(SDValue Op
, SelectionDAG
&DAG
) const;
3709 /// This callback is invoked when a node result type is illegal for the
3710 /// target, and the operation was registered to use 'custom' lowering for that
3711 /// result type. The target places new result values for the node in Results
3712 /// (their number and types must exactly match those of the original return
3713 /// values of the node), or leaves Results empty, which indicates that the
3714 /// node is not to be custom lowered after all.
3716 /// If the target has no operations that require custom lowering, it need not
3717 /// implement this. The default implementation aborts.
3718 virtual void ReplaceNodeResults(SDNode
* /*N*/,
3719 SmallVectorImpl
<SDValue
> &/*Results*/,
3720 SelectionDAG
&/*DAG*/) const {
3721 llvm_unreachable("ReplaceNodeResults not implemented for this target!");
3724 /// This method returns the name of a target specific DAG node.
3725 virtual const char *getTargetNodeName(unsigned Opcode
) const;
3727 /// This method returns a target specific FastISel object, or null if the
3728 /// target does not support "fast" ISel.
3729 virtual FastISel
*createFastISel(FunctionLoweringInfo
&,
3730 const TargetLibraryInfo
*) const {
3734 bool verifyReturnAddressArgumentIsConstant(SDValue Op
,
3735 SelectionDAG
&DAG
) const;
3737 //===--------------------------------------------------------------------===//
3738 // Inline Asm Support hooks
3741 /// This hook allows the target to expand an inline asm call to be explicit
3742 /// llvm code if it wants to. This is useful for turning simple inline asms
3743 /// into LLVM intrinsics, which gives the compiler more information about the
3744 /// behavior of the code.
3745 virtual bool ExpandInlineAsm(CallInst
*) const {
3749 enum ConstraintType
{
3750 C_Register
, // Constraint represents specific register(s).
3751 C_RegisterClass
, // Constraint represents any of register(s) in class.
3752 C_Memory
, // Memory constraint.
3753 C_Immediate
, // Requires an immediate.
3754 C_Other
, // Something else.
3755 C_Unknown
// Unsupported constraint.
3758 enum ConstraintWeight
{
3760 CW_Invalid
= -1, // No match.
3761 CW_Okay
= 0, // Acceptable.
3762 CW_Good
= 1, // Good weight.
3763 CW_Better
= 2, // Better weight.
3764 CW_Best
= 3, // Best weight.
3766 // Well-known weights.
3767 CW_SpecificReg
= CW_Okay
, // Specific register operands.
3768 CW_Register
= CW_Good
, // Register operands.
3769 CW_Memory
= CW_Better
, // Memory operands.
3770 CW_Constant
= CW_Best
, // Constant operand.
3771 CW_Default
= CW_Okay
// Default or don't know type.
3774 /// This contains information for each constraint that we are lowering.
3775 struct AsmOperandInfo
: public InlineAsm::ConstraintInfo
{
3776 /// This contains the actual string for the code, like "m". TargetLowering
3777 /// picks the 'best' code from ConstraintInfo::Codes that most closely
3778 /// matches the operand.
3779 std::string ConstraintCode
;
3781 /// Information about the constraint code, e.g. Register, RegisterClass,
3782 /// Memory, Other, Unknown.
3783 TargetLowering::ConstraintType ConstraintType
= TargetLowering::C_Unknown
;
3785 /// If this is the result output operand or a clobber, this is null,
3786 /// otherwise it is the incoming operand to the CallInst. This gets
3787 /// modified as the asm is processed.
3788 Value
*CallOperandVal
= nullptr;
3790 /// The ValueType for the operand value.
3791 MVT ConstraintVT
= MVT::Other
;
3793 /// Copy constructor for copying from a ConstraintInfo.
3794 AsmOperandInfo(InlineAsm::ConstraintInfo Info
)
3795 : InlineAsm::ConstraintInfo(std::move(Info
)) {}
3797 /// Return true of this is an input operand that is a matching constraint
3799 bool isMatchingInputConstraint() const;
3801 /// If this is an input matching constraint, this method returns the output
3802 /// operand it matches.
3803 unsigned getMatchedOperand() const;
3806 using AsmOperandInfoVector
= std::vector
<AsmOperandInfo
>;
3808 /// Split up the constraint string from the inline assembly value into the
3809 /// specific constraints and their prefixes, and also tie in the associated
3810 /// operand values. If this returns an empty vector, and if the constraint
3811 /// string itself isn't empty, there was an error parsing.
3812 virtual AsmOperandInfoVector
ParseConstraints(const DataLayout
&DL
,
3813 const TargetRegisterInfo
*TRI
,
3814 ImmutableCallSite CS
) const;
3816 /// Examine constraint type and operand type and determine a weight value.
3817 /// The operand object must already have been set up with the operand type.
3818 virtual ConstraintWeight
getMultipleConstraintMatchWeight(
3819 AsmOperandInfo
&info
, int maIndex
) const;
3821 /// Examine constraint string and operand type and determine a weight value.
3822 /// The operand object must already have been set up with the operand type.
3823 virtual ConstraintWeight
getSingleConstraintMatchWeight(
3824 AsmOperandInfo
&info
, const char *constraint
) const;
3826 /// Determines the constraint code and constraint type to use for the specific
3827 /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
3828 /// If the actual operand being passed in is available, it can be passed in as
3829 /// Op, otherwise an empty SDValue can be passed.
3830 virtual void ComputeConstraintToUse(AsmOperandInfo
&OpInfo
,
3832 SelectionDAG
*DAG
= nullptr) const;
3834 /// Given a constraint, return the type of constraint it is for this target.
3835 virtual ConstraintType
getConstraintType(StringRef Constraint
) const;
3837 /// Given a physical register constraint (e.g. {edx}), return the register
3838 /// number and the register class for the register.
3840 /// Given a register class constraint, like 'r', if this corresponds directly
3841 /// to an LLVM register class, return a register of 0 and the register class
3844 /// This should only be used for C_Register constraints. On error, this
3845 /// returns a register number of 0 and a null register class pointer.
3846 virtual std::pair
<unsigned, const TargetRegisterClass
*>
3847 getRegForInlineAsmConstraint(const TargetRegisterInfo
*TRI
,
3848 StringRef Constraint
, MVT VT
) const;
3850 virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode
) const {
3851 if (ConstraintCode
== "i")
3852 return InlineAsm::Constraint_i
;
3853 else if (ConstraintCode
== "m")
3854 return InlineAsm::Constraint_m
;
3855 return InlineAsm::Constraint_Unknown
;
3858 /// Try to replace an X constraint, which matches anything, with another that
3859 /// has more specific requirements based on the type of the corresponding
3860 /// operand. This returns null if there is no replacement to make.
3861 virtual const char *LowerXConstraint(EVT ConstraintVT
) const;
3863 /// Lower the specified operand into the Ops vector. If it is invalid, don't
3864 /// add anything to Ops.
3865 virtual void LowerAsmOperandForConstraint(SDValue Op
, std::string
&Constraint
,
3866 std::vector
<SDValue
> &Ops
,
3867 SelectionDAG
&DAG
) const;
3869 // Lower custom output constraints. If invalid, return SDValue().
3870 virtual SDValue
LowerAsmOutputForConstraint(SDValue
&Chain
, SDValue
&Flag
,
3872 const AsmOperandInfo
&OpInfo
,
3873 SelectionDAG
&DAG
) const;
3875 //===--------------------------------------------------------------------===//
3876 // Div utility functions
3878 SDValue
BuildSDIV(SDNode
*N
, SelectionDAG
&DAG
, bool IsAfterLegalization
,
3879 SmallVectorImpl
<SDNode
*> &Created
) const;
3880 SDValue
BuildUDIV(SDNode
*N
, SelectionDAG
&DAG
, bool IsAfterLegalization
,
3881 SmallVectorImpl
<SDNode
*> &Created
) const;
3883 /// Targets may override this function to provide custom SDIV lowering for
3884 /// power-of-2 denominators. If the target returns an empty SDValue, LLVM
3885 /// assumes SDIV is expensive and replaces it with a series of other integer
3887 virtual SDValue
BuildSDIVPow2(SDNode
*N
, const APInt
&Divisor
,
3889 SmallVectorImpl
<SDNode
*> &Created
) const;
3891 /// Indicate whether this target prefers to combine FDIVs with the same
3892 /// divisor. If the transform should never be done, return zero. If the
3893 /// transform should be done, return the minimum number of divisor uses
3894 /// that must exist.
3895 virtual unsigned combineRepeatedFPDivisors() const {
3899 /// Hooks for building estimates in place of slower divisions and square
3902 /// Return either a square root or its reciprocal estimate value for the input
3904 /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
3905 /// 'Enabled' as set by a potential default override attribute.
3906 /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
3907 /// refinement iterations required to generate a sufficient (though not
3908 /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
3909 /// The boolean UseOneConstNR output is used to select a Newton-Raphson
3910 /// algorithm implementation that uses either one or two constants.
3911 /// The boolean Reciprocal is used to select whether the estimate is for the
3912 /// square root of the input operand or the reciprocal of its square root.
3913 /// A target may choose to implement its own refinement within this function.
3914 /// If that's true, then return '0' as the number of RefinementSteps to avoid
3915 /// any further refinement of the estimate.
3916 /// An empty SDValue return means no estimate sequence can be created.
3917 virtual SDValue
getSqrtEstimate(SDValue Operand
, SelectionDAG
&DAG
,
3918 int Enabled
, int &RefinementSteps
,
3919 bool &UseOneConstNR
, bool Reciprocal
) const {
3923 /// Return a reciprocal estimate value for the input operand.
3924 /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
3925 /// 'Enabled' as set by a potential default override attribute.
3926 /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
3927 /// refinement iterations required to generate a sufficient (though not
3928 /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
3929 /// A target may choose to implement its own refinement within this function.
3930 /// If that's true, then return '0' as the number of RefinementSteps to avoid
3931 /// any further refinement of the estimate.
3932 /// An empty SDValue return means no estimate sequence can be created.
3933 virtual SDValue
getRecipEstimate(SDValue Operand
, SelectionDAG
&DAG
,
3934 int Enabled
, int &RefinementSteps
) const {
3938 //===--------------------------------------------------------------------===//
3939 // Legalization utility functions
3942 /// Expand a MUL or [US]MUL_LOHI of n-bit values into two or four nodes,
3943 /// respectively, each computing an n/2-bit part of the result.
3944 /// \param Result A vector that will be filled with the parts of the result
3945 /// in little-endian order.
3946 /// \param LL Low bits of the LHS of the MUL. You can use this parameter
3947 /// if you want to control how low bits are extracted from the LHS.
3948 /// \param LH High bits of the LHS of the MUL. See LL for meaning.
3949 /// \param RL Low bits of the RHS of the MUL. See LL for meaning
3950 /// \param RH High bits of the RHS of the MUL. See LL for meaning.
3951 /// \returns true if the node has been expanded, false if it has not
3952 bool expandMUL_LOHI(unsigned Opcode
, EVT VT
, SDLoc dl
, SDValue LHS
,
3953 SDValue RHS
, SmallVectorImpl
<SDValue
> &Result
, EVT HiLoVT
,
3954 SelectionDAG
&DAG
, MulExpansionKind Kind
,
3955 SDValue LL
= SDValue(), SDValue LH
= SDValue(),
3956 SDValue RL
= SDValue(), SDValue RH
= SDValue()) const;
3958 /// Expand a MUL into two nodes. One that computes the high bits of
3959 /// the result and one that computes the low bits.
3960 /// \param HiLoVT The value type to use for the Lo and Hi nodes.
3961 /// \param LL Low bits of the LHS of the MUL. You can use this parameter
3962 /// if you want to control how low bits are extracted from the LHS.
3963 /// \param LH High bits of the LHS of the MUL. See LL for meaning.
3964 /// \param RL Low bits of the RHS of the MUL. See LL for meaning
3965 /// \param RH High bits of the RHS of the MUL. See LL for meaning.
3966 /// \returns true if the node has been expanded. false if it has not
3967 bool expandMUL(SDNode
*N
, SDValue
&Lo
, SDValue
&Hi
, EVT HiLoVT
,
3968 SelectionDAG
&DAG
, MulExpansionKind Kind
,
3969 SDValue LL
= SDValue(), SDValue LH
= SDValue(),
3970 SDValue RL
= SDValue(), SDValue RH
= SDValue()) const;
3972 /// Expand funnel shift.
3973 /// \param N Node to expand
3974 /// \param Result output after conversion
3975 /// \returns True, if the expansion was successful, false otherwise
3976 bool expandFunnelShift(SDNode
*N
, SDValue
&Result
, SelectionDAG
&DAG
) const;
3978 /// Expand rotations.
3979 /// \param N Node to expand
3980 /// \param Result output after conversion
3981 /// \returns True, if the expansion was successful, false otherwise
3982 bool expandROT(SDNode
*N
, SDValue
&Result
, SelectionDAG
&DAG
) const;
3984 /// Expand float(f32) to SINT(i64) conversion
3985 /// \param N Node to expand
3986 /// \param Result output after conversion
3987 /// \returns True, if the expansion was successful, false otherwise
3988 bool expandFP_TO_SINT(SDNode
*N
, SDValue
&Result
, SelectionDAG
&DAG
) const;
3990 /// Expand float to UINT conversion
3991 /// \param N Node to expand
3992 /// \param Result output after conversion
3993 /// \returns True, if the expansion was successful, false otherwise
3994 bool expandFP_TO_UINT(SDNode
*N
, SDValue
&Result
, SelectionDAG
&DAG
) const;
3996 /// Expand UINT(i64) to double(f64) conversion
3997 /// \param N Node to expand
3998 /// \param Result output after conversion
3999 /// \returns True, if the expansion was successful, false otherwise
4000 bool expandUINT_TO_FP(SDNode
*N
, SDValue
&Result
, SelectionDAG
&DAG
) const;
4002 /// Expand fminnum/fmaxnum into fminnum_ieee/fmaxnum_ieee with quieted inputs.
4003 SDValue
expandFMINNUM_FMAXNUM(SDNode
*N
, SelectionDAG
&DAG
) const;
4005 /// Expand CTPOP nodes. Expands vector/scalar CTPOP nodes,
4006 /// vector nodes can only succeed if all operations are legal/custom.
4007 /// \param N Node to expand
4008 /// \param Result output after conversion
4009 /// \returns True, if the expansion was successful, false otherwise
4010 bool expandCTPOP(SDNode
*N
, SDValue
&Result
, SelectionDAG
&DAG
) const;
4012 /// Expand CTLZ/CTLZ_ZERO_UNDEF nodes. Expands vector/scalar CTLZ nodes,
4013 /// vector nodes can only succeed if all operations are legal/custom.
4014 /// \param N Node to expand
4015 /// \param Result output after conversion
4016 /// \returns True, if the expansion was successful, false otherwise
4017 bool expandCTLZ(SDNode
*N
, SDValue
&Result
, SelectionDAG
&DAG
) const;
4019 /// Expand CTTZ/CTTZ_ZERO_UNDEF nodes. Expands vector/scalar CTTZ nodes,
4020 /// vector nodes can only succeed if all operations are legal/custom.
4021 /// \param N Node to expand
4022 /// \param Result output after conversion
4023 /// \returns True, if the expansion was successful, false otherwise
4024 bool expandCTTZ(SDNode
*N
, SDValue
&Result
, SelectionDAG
&DAG
) const;
4026 /// Expand ABS nodes. Expands vector/scalar ABS nodes,
4027 /// vector nodes can only succeed if all operations are legal/custom.
4028 /// (ABS x) -> (XOR (ADD x, (SRA x, type_size)), (SRA x, type_size))
4029 /// \param N Node to expand
4030 /// \param Result output after conversion
4031 /// \returns True, if the expansion was successful, false otherwise
4032 bool expandABS(SDNode
*N
, SDValue
&Result
, SelectionDAG
&DAG
) const;
4034 /// Turn load of vector type into a load of the individual elements.
4035 /// \param LD load to expand
4036 /// \returns MERGE_VALUEs of the scalar loads with their chains.
4037 SDValue
scalarizeVectorLoad(LoadSDNode
*LD
, SelectionDAG
&DAG
) const;
4039 // Turn a store of a vector type into stores of the individual elements.
4040 /// \param ST Store with a vector value type
4041 /// \returns MERGE_VALUs of the individual store chains.
4042 SDValue
scalarizeVectorStore(StoreSDNode
*ST
, SelectionDAG
&DAG
) const;
4044 /// Expands an unaligned load to 2 half-size loads for an integer, and
4045 /// possibly more for vectors.
4046 std::pair
<SDValue
, SDValue
> expandUnalignedLoad(LoadSDNode
*LD
,
4047 SelectionDAG
&DAG
) const;
4049 /// Expands an unaligned store to 2 half-size stores for integer values, and
4050 /// possibly more for vectors.
4051 SDValue
expandUnalignedStore(StoreSDNode
*ST
, SelectionDAG
&DAG
) const;
4053 /// Increments memory address \p Addr according to the type of the value
4054 /// \p DataVT that should be stored. If the data is stored in compressed
4055 /// form, the memory address should be incremented according to the number of
4056 /// the stored elements. This number is equal to the number of '1's bits
4058 /// \p DataVT is a vector type. \p Mask is a vector value.
4059 /// \p DataVT and \p Mask have the same number of vector elements.
4060 SDValue
IncrementMemoryAddress(SDValue Addr
, SDValue Mask
, const SDLoc
&DL
,
4061 EVT DataVT
, SelectionDAG
&DAG
,
4062 bool IsCompressedMemory
) const;
4064 /// Get a pointer to vector element \p Idx located in memory for a vector of
4065 /// type \p VecVT starting at a base address of \p VecPtr. If \p Idx is out of
4066 /// bounds the returned pointer is unspecified, but will be within the vector
4068 SDValue
getVectorElementPointer(SelectionDAG
&DAG
, SDValue VecPtr
, EVT VecVT
,
4069 SDValue Index
) const;
4071 /// Method for building the DAG expansion of ISD::[US][ADD|SUB]SAT. This
4072 /// method accepts integers as its arguments.
4073 SDValue
expandAddSubSat(SDNode
*Node
, SelectionDAG
&DAG
) const;
4075 /// Method for building the DAG expansion of ISD::SMULFIX. This method accepts
4076 /// integers as its arguments.
4077 SDValue
expandFixedPointMul(SDNode
*Node
, SelectionDAG
&DAG
) const;
4079 /// Method for building the DAG expansion of ISD::U(ADD|SUB)O. Expansion
4080 /// always suceeds and populates the Result and Overflow arguments.
4081 void expandUADDSUBO(SDNode
*Node
, SDValue
&Result
, SDValue
&Overflow
,
4082 SelectionDAG
&DAG
) const;
4084 /// Method for building the DAG expansion of ISD::S(ADD|SUB)O. Expansion
4085 /// always suceeds and populates the Result and Overflow arguments.
4086 void expandSADDSUBO(SDNode
*Node
, SDValue
&Result
, SDValue
&Overflow
,
4087 SelectionDAG
&DAG
) const;
4089 /// Method for building the DAG expansion of ISD::[US]MULO. Returns whether
4090 /// expansion was successful and populates the Result and Overflow arguments.
4091 bool expandMULO(SDNode
*Node
, SDValue
&Result
, SDValue
&Overflow
,
4092 SelectionDAG
&DAG
) const;
4094 /// Expand a VECREDUCE_* into an explicit calculation. If Count is specified,
4095 /// only the first Count elements of the vector are used.
4096 SDValue
expandVecReduce(SDNode
*Node
, SelectionDAG
&DAG
) const;
4098 //===--------------------------------------------------------------------===//
4099 // Instruction Emitting Hooks
4102 /// This method should be implemented by targets that mark instructions with
4103 /// the 'usesCustomInserter' flag. These instructions are special in various
4104 /// ways, which require special support to insert. The specified MachineInstr
4105 /// is created but not inserted into any basic blocks, and this method is
4106 /// called to expand it into a sequence of instructions, potentially also
4107 /// creating new basic blocks and control flow.
4108 /// As long as the returned basic block is different (i.e., we created a new
4109 /// one), the custom inserter is free to modify the rest of \p MBB.
4110 virtual MachineBasicBlock
*
4111 EmitInstrWithCustomInserter(MachineInstr
&MI
, MachineBasicBlock
*MBB
) const;
4113 /// This method should be implemented by targets that mark instructions with
4114 /// the 'hasPostISelHook' flag. These instructions must be adjusted after
4115 /// instruction selection by target hooks. e.g. To fill in optional defs for
4116 /// ARM 's' setting instructions.
4117 virtual void AdjustInstrPostInstrSelection(MachineInstr
&MI
,
4118 SDNode
*Node
) const;
4120 /// If this function returns true, SelectionDAGBuilder emits a
4121 /// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
4122 virtual bool useLoadStackGuardNode() const {
4126 virtual SDValue
emitStackGuardXorFP(SelectionDAG
&DAG
, SDValue Val
,
4127 const SDLoc
&DL
) const {
4128 llvm_unreachable("not implemented for this target");
4131 /// Lower TLS global address SDNode for target independent emulated TLS model.
4132 virtual SDValue
LowerToTLSEmulatedModel(const GlobalAddressSDNode
*GA
,
4133 SelectionDAG
&DAG
) const;
4135 /// Expands target specific indirect branch for the case of JumpTable
4137 virtual SDValue
expandIndirectJTBranch(const SDLoc
& dl
, SDValue Value
, SDValue Addr
,
4138 SelectionDAG
&DAG
) const {
4139 return DAG
.getNode(ISD::BRIND
, dl
, MVT::Other
, Value
, Addr
);
4142 // seteq(x, 0) -> truncate(srl(ctlz(zext(x)), log2(#bits)))
4143 // If we're comparing for equality to zero and isCtlzFast is true, expose the
4144 // fact that this can be implemented as a ctlz/srl pair, so that the dag
4145 // combiner can fold the new nodes.
4146 SDValue
lowerCmpEqZeroToCtlzSrl(SDValue Op
, SelectionDAG
&DAG
) const;
4149 SDValue
foldSetCCWithAnd(EVT VT
, SDValue N0
, SDValue N1
, ISD::CondCode Cond
,
4150 const SDLoc
&DL
, DAGCombinerInfo
&DCI
) const;
4151 SDValue
foldSetCCWithBinOp(EVT VT
, SDValue N0
, SDValue N1
, ISD::CondCode Cond
,
4152 const SDLoc
&DL
, DAGCombinerInfo
&DCI
) const;
4154 SDValue
optimizeSetCCOfSignedTruncationCheck(EVT SCCVT
, SDValue N0
,
4155 SDValue N1
, ISD::CondCode Cond
,
4156 DAGCombinerInfo
&DCI
,
4157 const SDLoc
&DL
) const;
4159 // (X & (C l>>/<< Y)) ==/!= 0 --> ((X <</l>> Y) & C) ==/!= 0
4160 SDValue
optimizeSetCCByHoistingAndByConstFromLogicalShift(
4161 EVT SCCVT
, SDValue N0
, SDValue N1C
, ISD::CondCode Cond
,
4162 DAGCombinerInfo
&DCI
, const SDLoc
&DL
) const;
4164 SDValue
prepareUREMEqFold(EVT SETCCVT
, SDValue REMNode
,
4165 SDValue CompTargetNode
, ISD::CondCode Cond
,
4166 DAGCombinerInfo
&DCI
, const SDLoc
&DL
,
4167 SmallVectorImpl
<SDNode
*> &Created
) const;
4168 SDValue
buildUREMEqFold(EVT SETCCVT
, SDValue REMNode
, SDValue CompTargetNode
,
4169 ISD::CondCode Cond
, DAGCombinerInfo
&DCI
,
4170 const SDLoc
&DL
) const;
4172 SDValue
prepareSREMEqFold(EVT SETCCVT
, SDValue REMNode
,
4173 SDValue CompTargetNode
, ISD::CondCode Cond
,
4174 DAGCombinerInfo
&DCI
, const SDLoc
&DL
,
4175 SmallVectorImpl
<SDNode
*> &Created
) const;
4176 SDValue
buildSREMEqFold(EVT SETCCVT
, SDValue REMNode
, SDValue CompTargetNode
,
4177 ISD::CondCode Cond
, DAGCombinerInfo
&DCI
,
4178 const SDLoc
&DL
) const;
4181 /// Given an LLVM IR type and return type attributes, compute the return value
4182 /// EVTs and flags, and optionally also the offsets, if the return value is
4183 /// being lowered to memory.
4184 void GetReturnInfo(CallingConv::ID CC
, Type
*ReturnType
, AttributeList attr
,
4185 SmallVectorImpl
<ISD::OutputArg
> &Outs
,
4186 const TargetLowering
&TLI
, const DataLayout
&DL
);
4188 } // end namespace llvm
4190 #endif // LLVM_CODEGEN_TARGETLOWERING_H