lib/Target/X86/X86RegisterInfo.cpp

   1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the X86 implementation of the TargetRegisterInfo class.
  11 // This file is responsible for the frame pointer elimination optimization
  12 // on X86.
  13 //
  14 //===----------------------------------------------------------------------===//
  15
  16 #include "X86RegisterInfo.h"
  17 #include "X86FrameLowering.h"
  18 #include "X86MachineFunctionInfo.h"
  19 #include "X86Subtarget.h"
  20 #include "llvm/ADT/BitVector.h"
  21 #include "llvm/ADT/STLExtras.h"
  22 #include "llvm/CodeGen/MachineFrameInfo.h"
  23 #include "llvm/CodeGen/MachineFunction.h"
  24 #include "llvm/CodeGen/MachineFunctionPass.h"
  25 #include "llvm/CodeGen/MachineRegisterInfo.h"
  26 #include "llvm/CodeGen/TargetFrameLowering.h"
  27 #include "llvm/CodeGen/TargetInstrInfo.h"
  28 #include "llvm/IR/Constants.h"
  29 #include "llvm/IR/Function.h"
  30 #include "llvm/IR/Type.h"
  31 #include "llvm/Support/CommandLine.h"
  32 #include "llvm/Support/ErrorHandling.h"
  33 #include "llvm/Target/TargetMachine.h"
  34 #include "llvm/Target/TargetOptions.h"
  35
  36 using namespace llvm;
  37
  38 #define GET_REGINFO_TARGET_DESC
  39 #include "X86GenRegisterInfo.inc"
  40
  41 static cl::opt<bool>
  42 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
  43           cl::desc("Enable use of a base pointer for complex stack frames"));
  44
  45 X86RegisterInfo::X86RegisterInfo(const Triple &TT)
  46     : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP),
  47                          X86_MC::getDwarfRegFlavour(TT, false),
  48                          X86_MC::getDwarfRegFlavour(TT, true),
  49                          (TT.isArch64Bit() ? X86::RIP : X86::EIP)) {
  50   X86_MC::initLLVMToSEHAndCVRegMapping(this);
  51
  52   // Cache some information.
  53   Is64Bit = TT.isArch64Bit();
  54   IsWin64 = Is64Bit && TT.isOSWindows();
  55
  56   // Use a callee-saved register as the base pointer.  These registers must
  57   // not conflict with any ABI requirements.  For example, in 32-bit mode PIC
  58   // requires GOT in the EBX register before function calls via PLT GOT pointer.
  59   if (Is64Bit) {
  60     SlotSize = 8;
  61     // This matches the simplified 32-bit pointer code in the data layout
  62     // computation.
  63     // FIXME: Should use the data layout?
  64     bool Use64BitReg = TT.getEnvironment() != Triple::GNUX32;
  65     StackPtr = Use64BitReg ? X86::RSP : X86::ESP;
  66     FramePtr = Use64BitReg ? X86::RBP : X86::EBP;
  67     BasePtr = Use64BitReg ? X86::RBX : X86::EBX;
  68   } else {
  69     SlotSize = 4;
  70     StackPtr = X86::ESP;
  71     FramePtr = X86::EBP;
  72     BasePtr = X86::ESI;
  73   }
  74 }
  75
  76 bool
  77 X86RegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
  78   // ExecutionDomainFix, BreakFalseDeps and PostRAScheduler require liveness.
  79   return true;
  80 }
  81
  82 int
  83 X86RegisterInfo::getSEHRegNum(unsigned i) const {
  84   return getEncodingValue(i);
  85 }
  86
  87 const TargetRegisterClass *
  88 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
  89                                        unsigned Idx) const {
  90   // The sub_8bit sub-register index is more constrained in 32-bit mode.
  91   // It behaves just like the sub_8bit_hi index.
  92   if (!Is64Bit && Idx == X86::sub_8bit)
  93     Idx = X86::sub_8bit_hi;
  94
  95   // Forward to TableGen's default version.
  96   return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
  97 }
  98
  99 const TargetRegisterClass *
 100 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
 101                                           const TargetRegisterClass *B,
 102                                           unsigned SubIdx) const {
 103   // The sub_8bit sub-register index is more constrained in 32-bit mode.
 104   if (!Is64Bit && SubIdx == X86::sub_8bit) {
 105     A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
 106     if (!A)
 107       return nullptr;
 108   }
 109   return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
 110 }
 111
 112 const TargetRegisterClass *
 113 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
 114                                            const MachineFunction &MF) const {
 115   // Don't allow super-classes of GR8_NOREX.  This class is only used after
 116   // extracting sub_8bit_hi sub-registers.  The H sub-registers cannot be copied
 117   // to the full GR8 register class in 64-bit mode, so we cannot allow the
 118   // reigster class inflation.
 119   //
 120   // The GR8_NOREX class is always used in a way that won't be constrained to a
 121   // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
 122   // full GR8 class.
 123   if (RC == &X86::GR8_NOREXRegClass)
 124     return RC;
 125
 126   const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
 127
 128   const TargetRegisterClass *Super = RC;
 129   TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
 130   do {
 131     switch (Super->getID()) {
 132     case X86::FR32RegClassID:
 133     case X86::FR64RegClassID:
 134       // If AVX-512 isn't supported we should only inflate to these classes.
 135       if (!Subtarget.hasAVX512() &&
 136           getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
 137         return Super;
 138       break;
 139     case X86::VR128RegClassID:
 140     case X86::VR256RegClassID:
 141       // If VLX isn't supported we should only inflate to these classes.
 142       if (!Subtarget.hasVLX() &&
 143           getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
 144         return Super;
 145       break;
 146     case X86::VR128XRegClassID:
 147     case X86::VR256XRegClassID:
 148       // If VLX isn't support we shouldn't inflate to these classes.
 149       if (Subtarget.hasVLX() &&
 150           getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
 151         return Super;
 152       break;
 153     case X86::FR32XRegClassID:
 154     case X86::FR64XRegClassID:
 155       // If AVX-512 isn't support we shouldn't inflate to these classes.
 156       if (Subtarget.hasAVX512() &&
 157           getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
 158         return Super;
 159       break;
 160     case X86::GR8RegClassID:
 161     case X86::GR16RegClassID:
 162     case X86::GR32RegClassID:
 163     case X86::GR64RegClassID:
 164     case X86::RFP32RegClassID:
 165     case X86::RFP64RegClassID:
 166     case X86::RFP80RegClassID:
 167     case X86::VR512RegClassID:
 168       // Don't return a super-class that would shrink the spill size.
 169       // That can happen with the vector and float classes.
 170       if (getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
 171         return Super;
 172     }
 173     Super = *I++;
 174   } while (Super);
 175   return RC;
 176 }
 177
 178 const TargetRegisterClass *
 179 X86RegisterInfo::getPointerRegClass(const MachineFunction &MF,
 180                                     unsigned Kind) const {
 181   const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
 182   switch (Kind) {
 183   default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
 184   case 0: // Normal GPRs.
 185     if (Subtarget.isTarget64BitLP64())
 186       return &X86::GR64RegClass;
 187     // If the target is 64bit but we have been told to use 32bit addresses,
 188     // we can still use 64-bit register as long as we know the high bits
 189     // are zeros.
 190     // Reflect that in the returned register class.
 191     if (Is64Bit) {
 192       // When the target also allows 64-bit frame pointer and we do have a
 193       // frame, this is fine to use it for the address accesses as well.
 194       const X86FrameLowering *TFI = getFrameLowering(MF);
 195       return TFI->hasFP(MF) && TFI->Uses64BitFramePtr
 196                  ? &X86::LOW32_ADDR_ACCESS_RBPRegClass
 197                  : &X86::LOW32_ADDR_ACCESSRegClass;
 198     }
 199     return &X86::GR32RegClass;
 200   case 1: // Normal GPRs except the stack pointer (for encoding reasons).
 201     if (Subtarget.isTarget64BitLP64())
 202       return &X86::GR64_NOSPRegClass;
 203     // NOSP does not contain RIP, so no special case here.
 204     return &X86::GR32_NOSPRegClass;
 205   case 2: // NOREX GPRs.
 206     if (Subtarget.isTarget64BitLP64())
 207       return &X86::GR64_NOREXRegClass;
 208     return &X86::GR32_NOREXRegClass;
 209   case 3: // NOREX GPRs except the stack pointer (for encoding reasons).
 210     if (Subtarget.isTarget64BitLP64())
 211       return &X86::GR64_NOREX_NOSPRegClass;
 212     // NOSP does not contain RIP, so no special case here.
 213     return &X86::GR32_NOREX_NOSPRegClass;
 214   case 4: // Available for tailcall (not callee-saved GPRs).
 215     return getGPRsForTailCall(MF);
 216   }
 217 }
 218
 219 const TargetRegisterClass *
 220 X86RegisterInfo::getGPRsForTailCall(const MachineFunction &MF) const {
 221   const Function &F = MF.getFunction();
 222   if (IsWin64 || (F.getCallingConv() == CallingConv::Win64))
 223     return &X86::GR64_TCW64RegClass;
 224   else if (Is64Bit)
 225     return &X86::GR64_TCRegClass;
 226
 227   bool hasHipeCC = (F.getCallingConv() == CallingConv::HiPE);
 228   if (hasHipeCC)
 229     return &X86::GR32RegClass;
 230   return &X86::GR32_TCRegClass;
 231 }
 232
 233 const TargetRegisterClass *
 234 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
 235   if (RC == &X86::CCRRegClass) {
 236     if (Is64Bit)
 237       return &X86::GR64RegClass;
 238     else
 239       return &X86::GR32RegClass;
 240   }
 241   return RC;
 242 }
 243
 244 unsigned
 245 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
 246                                      MachineFunction &MF) const {
 247   const X86FrameLowering *TFI = getFrameLowering(MF);
 248
 249   unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
 250   switch (RC->getID()) {
 251   default:
 252     return 0;
 253   case X86::GR32RegClassID:
 254     return 4 - FPDiff;
 255   case X86::GR64RegClassID:
 256     return 12 - FPDiff;
 257   case X86::VR128RegClassID:
 258     return Is64Bit ? 10 : 4;
 259   case X86::VR64RegClassID:
 260     return 4;
 261   }
 262 }
 263
 264 const MCPhysReg *
 265 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
 266   assert(MF && "MachineFunction required");
 267
 268   const X86Subtarget &Subtarget = MF->getSubtarget<X86Subtarget>();
 269   const Function &F = MF->getFunction();
 270   bool HasSSE = Subtarget.hasSSE1();
 271   bool HasAVX = Subtarget.hasAVX();
 272   bool HasAVX512 = Subtarget.hasAVX512();
 273   bool CallsEHReturn = MF->callsEHReturn();
 274
 275   CallingConv::ID CC = F.getCallingConv();
 276
 277   // If attribute NoCallerSavedRegisters exists then we set X86_INTR calling
 278   // convention because it has the CSR list.
 279   if (MF->getFunction().hasFnAttribute("no_caller_saved_registers"))
 280     CC = CallingConv::X86_INTR;
 281
 282   switch (CC) {
 283   case CallingConv::GHC:
 284   case CallingConv::HiPE:
 285     return CSR_NoRegs_SaveList;
 286   case CallingConv::AnyReg:
 287     if (HasAVX)
 288       return CSR_64_AllRegs_AVX_SaveList;
 289     return CSR_64_AllRegs_SaveList;
 290   case CallingConv::PreserveMost:
 291     return CSR_64_RT_MostRegs_SaveList;
 292   case CallingConv::PreserveAll:
 293     if (HasAVX)
 294       return CSR_64_RT_AllRegs_AVX_SaveList;
 295     return CSR_64_RT_AllRegs_SaveList;
 296   case CallingConv::CXX_FAST_TLS:
 297     if (Is64Bit)
 298       return MF->getInfo<X86MachineFunctionInfo>()->isSplitCSR() ?
 299              CSR_64_CXX_TLS_Darwin_PE_SaveList : CSR_64_TLS_Darwin_SaveList;
 300     break;
 301   case CallingConv::Intel_OCL_BI: {
 302     if (HasAVX512 && IsWin64)
 303       return CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
 304     if (HasAVX512 && Is64Bit)
 305       return CSR_64_Intel_OCL_BI_AVX512_SaveList;
 306     if (HasAVX && IsWin64)
 307       return CSR_Win64_Intel_OCL_BI_AVX_SaveList;
 308     if (HasAVX && Is64Bit)
 309       return CSR_64_Intel_OCL_BI_AVX_SaveList;
 310     if (!HasAVX && !IsWin64 && Is64Bit)
 311       return CSR_64_Intel_OCL_BI_SaveList;
 312     break;
 313   }
 314   case CallingConv::HHVM:
 315     return CSR_64_HHVM_SaveList;
 316   case CallingConv::X86_RegCall:
 317     if (Is64Bit) {
 318       if (IsWin64) {
 319         return (HasSSE ? CSR_Win64_RegCall_SaveList :
 320                          CSR_Win64_RegCall_NoSSE_SaveList);
 321       } else {
 322         return (HasSSE ? CSR_SysV64_RegCall_SaveList :
 323                          CSR_SysV64_RegCall_NoSSE_SaveList);
 324       }
 325     } else {
 326       return (HasSSE ? CSR_32_RegCall_SaveList :
 327                        CSR_32_RegCall_NoSSE_SaveList);
 328     }
 329   case CallingConv::Cold:
 330     if (Is64Bit)
 331       return CSR_64_MostRegs_SaveList;
 332     break;
 333   case CallingConv::Win64:
 334     if (!HasSSE)
 335       return CSR_Win64_NoSSE_SaveList;
 336     return CSR_Win64_SaveList;
 337   case CallingConv::X86_64_SysV:
 338     if (CallsEHReturn)
 339       return CSR_64EHRet_SaveList;
 340     return CSR_64_SaveList;
 341   case CallingConv::X86_INTR:
 342     if (Is64Bit) {
 343       if (HasAVX512)
 344         return CSR_64_AllRegs_AVX512_SaveList;
 345       if (HasAVX)
 346         return CSR_64_AllRegs_AVX_SaveList;
 347       if (HasSSE)
 348         return CSR_64_AllRegs_SaveList;
 349       return CSR_64_AllRegs_NoSSE_SaveList;
 350     } else {
 351       if (HasAVX512)
 352         return CSR_32_AllRegs_AVX512_SaveList;
 353       if (HasAVX)
 354         return CSR_32_AllRegs_AVX_SaveList;
 355       if (HasSSE)
 356         return CSR_32_AllRegs_SSE_SaveList;
 357       return CSR_32_AllRegs_SaveList;
 358     }
 359   default:
 360     break;
 361   }
 362
 363   if (Is64Bit) {
 364     bool IsSwiftCC = Subtarget.getTargetLowering()->supportSwiftError() &&
 365                      F.getAttributes().hasAttrSomewhere(Attribute::SwiftError);
 366     if (IsSwiftCC)
 367       return IsWin64 ? CSR_Win64_SwiftError_SaveList
 368                      : CSR_64_SwiftError_SaveList;
 369
 370     if (IsWin64)
 371       return HasSSE ? CSR_Win64_SaveList : CSR_Win64_NoSSE_SaveList;
 372     if (CallsEHReturn)
 373       return CSR_64EHRet_SaveList;
 374     return CSR_64_SaveList;
 375   }
 376
 377   return CallsEHReturn ? CSR_32EHRet_SaveList : CSR_32_SaveList;
 378 }
 379
 380 const MCPhysReg *X86RegisterInfo::getCalleeSavedRegsViaCopy(
 381     const MachineFunction *MF) const {
 382   assert(MF && "Invalid MachineFunction pointer.");
 383   if (MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
 384       MF->getInfo<X86MachineFunctionInfo>()->isSplitCSR())
 385     return CSR_64_CXX_TLS_Darwin_ViaCopy_SaveList;
 386   return nullptr;
 387 }
 388
 389 const uint32_t *
 390 X86RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
 391                                       CallingConv::ID CC) const {
 392   const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
 393   bool HasSSE = Subtarget.hasSSE1();
 394   bool HasAVX = Subtarget.hasAVX();
 395   bool HasAVX512 = Subtarget.hasAVX512();
 396
 397   switch (CC) {
 398   case CallingConv::GHC:
 399   case CallingConv::HiPE:
 400     return CSR_NoRegs_RegMask;
 401   case CallingConv::AnyReg:
 402     if (HasAVX)
 403       return CSR_64_AllRegs_AVX_RegMask;
 404     return CSR_64_AllRegs_RegMask;
 405   case CallingConv::PreserveMost:
 406     return CSR_64_RT_MostRegs_RegMask;
 407   case CallingConv::PreserveAll:
 408     if (HasAVX)
 409       return CSR_64_RT_AllRegs_AVX_RegMask;
 410     return CSR_64_RT_AllRegs_RegMask;
 411   case CallingConv::CXX_FAST_TLS:
 412     if (Is64Bit)
 413       return CSR_64_TLS_Darwin_RegMask;
 414     break;
 415   case CallingConv::Intel_OCL_BI: {
 416     if (HasAVX512 && IsWin64)
 417       return CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
 418     if (HasAVX512 && Is64Bit)
 419       return CSR_64_Intel_OCL_BI_AVX512_RegMask;
 420     if (HasAVX && IsWin64)
 421       return CSR_Win64_Intel_OCL_BI_AVX_RegMask;
 422     if (HasAVX && Is64Bit)
 423       return CSR_64_Intel_OCL_BI_AVX_RegMask;
 424     if (!HasAVX && !IsWin64 && Is64Bit)
 425       return CSR_64_Intel_OCL_BI_RegMask;
 426     break;
 427   }
 428   case CallingConv::HHVM:
 429     return CSR_64_HHVM_RegMask;
 430   case CallingConv::X86_RegCall:
 431     if (Is64Bit) {
 432       if (IsWin64) {
 433         return (HasSSE ? CSR_Win64_RegCall_RegMask :
 434                          CSR_Win64_RegCall_NoSSE_RegMask);
 435       } else {
 436         return (HasSSE ? CSR_SysV64_RegCall_RegMask :
 437                          CSR_SysV64_RegCall_NoSSE_RegMask);
 438       }
 439     } else {
 440       return (HasSSE ? CSR_32_RegCall_RegMask :
 441                        CSR_32_RegCall_NoSSE_RegMask);
 442     }
 443   case CallingConv::Cold:
 444     if (Is64Bit)
 445       return CSR_64_MostRegs_RegMask;
 446     break;
 447   case CallingConv::Win64:
 448     return CSR_Win64_RegMask;
 449   case CallingConv::X86_64_SysV:
 450     return CSR_64_RegMask;
 451   case CallingConv::X86_INTR:
 452     if (Is64Bit) {
 453       if (HasAVX512)
 454         return CSR_64_AllRegs_AVX512_RegMask;
 455       if (HasAVX)
 456         return CSR_64_AllRegs_AVX_RegMask;
 457       if (HasSSE)
 458         return CSR_64_AllRegs_RegMask;
 459       return CSR_64_AllRegs_NoSSE_RegMask;
 460     } else {
 461       if (HasAVX512)
 462         return CSR_32_AllRegs_AVX512_RegMask;
 463       if (HasAVX)
 464         return CSR_32_AllRegs_AVX_RegMask;
 465       if (HasSSE)
 466         return CSR_32_AllRegs_SSE_RegMask;
 467       return CSR_32_AllRegs_RegMask;
 468     }
 469   default:
 470     break;
 471   }
 472
 473   // Unlike getCalleeSavedRegs(), we don't have MMI so we can't check
 474   // callsEHReturn().
 475   if (Is64Bit) {
 476     const Function &F = MF.getFunction();
 477     bool IsSwiftCC = Subtarget.getTargetLowering()->supportSwiftError() &&
 478                      F.getAttributes().hasAttrSomewhere(Attribute::SwiftError);
 479     if (IsSwiftCC)
 480       return IsWin64 ? CSR_Win64_SwiftError_RegMask : CSR_64_SwiftError_RegMask;
 481     return IsWin64 ? CSR_Win64_RegMask : CSR_64_RegMask;
 482   }
 483
 484   return CSR_32_RegMask;
 485 }
 486
 487 const uint32_t*
 488 X86RegisterInfo::getNoPreservedMask() const {
 489   return CSR_NoRegs_RegMask;
 490 }
 491
 492 const uint32_t *X86RegisterInfo::getDarwinTLSCallPreservedMask() const {
 493   return CSR_64_TLS_Darwin_RegMask;
 494 }
 495
 496 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
 497   BitVector Reserved(getNumRegs());
 498   const X86FrameLowering *TFI = getFrameLowering(MF);
 499
 500   // Set the stack-pointer register and its aliases as reserved.
 501   for (MCSubRegIterator I(X86::RSP, this, /*IncludeSelf=*/true); I.isValid();
 502        ++I)
 503     Reserved.set(*I);
 504
 505   // Set the Shadow Stack Pointer as reserved.
 506   Reserved.set(X86::SSP);
 507
 508   // Set the instruction pointer register and its aliases as reserved.
 509   for (MCSubRegIterator I(X86::RIP, this, /*IncludeSelf=*/true); I.isValid();
 510        ++I)
 511     Reserved.set(*I);
 512
 513   // Set the frame-pointer register and its aliases as reserved if needed.
 514   if (TFI->hasFP(MF)) {
 515     for (MCSubRegIterator I(X86::RBP, this, /*IncludeSelf=*/true); I.isValid();
 516          ++I)
 517       Reserved.set(*I);
 518   }
 519
 520   // Set the base-pointer register and its aliases as reserved if needed.
 521   if (hasBasePointer(MF)) {
 522     CallingConv::ID CC = MF.getFunction().getCallingConv();
 523     const uint32_t *RegMask = getCallPreservedMask(MF, CC);
 524     if (MachineOperand::clobbersPhysReg(RegMask, getBaseRegister()))
 525       report_fatal_error(
 526         "Stack realignment in presence of dynamic allocas is not supported with"
 527         "this calling convention.");
 528
 529     unsigned BasePtr = getX86SubSuperRegister(getBaseRegister(), 64);
 530     for (MCSubRegIterator I(BasePtr, this, /*IncludeSelf=*/true);
 531          I.isValid(); ++I)
 532       Reserved.set(*I);
 533   }
 534
 535   // Mark the segment registers as reserved.
 536   Reserved.set(X86::CS);
 537   Reserved.set(X86::SS);
 538   Reserved.set(X86::DS);
 539   Reserved.set(X86::ES);
 540   Reserved.set(X86::FS);
 541   Reserved.set(X86::GS);
 542
 543   // Mark the floating point stack registers as reserved.
 544   for (unsigned n = 0; n != 8; ++n)
 545     Reserved.set(X86::ST0 + n);
 546
 547   // Reserve the registers that only exist in 64-bit mode.
 548   if (!Is64Bit) {
 549     // These 8-bit registers are part of the x86-64 extension even though their
 550     // super-registers are old 32-bits.
 551     Reserved.set(X86::SIL);
 552     Reserved.set(X86::DIL);
 553     Reserved.set(X86::BPL);
 554     Reserved.set(X86::SPL);
 555     Reserved.set(X86::SIH);
 556     Reserved.set(X86::DIH);
 557     Reserved.set(X86::BPH);
 558     Reserved.set(X86::SPH);
 559
 560     for (unsigned n = 0; n != 8; ++n) {
 561       // R8, R9, ...
 562       for (MCRegAliasIterator AI(X86::R8 + n, this, true); AI.isValid(); ++AI)
 563         Reserved.set(*AI);
 564
 565       // XMM8, XMM9, ...
 566       for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI)
 567         Reserved.set(*AI);
 568     }
 569   }
 570   if (!Is64Bit || !MF.getSubtarget<X86Subtarget>().hasAVX512()) {
 571     for (unsigned n = 16; n != 32; ++n) {
 572       for (MCRegAliasIterator AI(X86::XMM0 + n, this, true); AI.isValid(); ++AI)
 573         Reserved.set(*AI);
 574     }
 575   }
 576
 577   assert(checkAllSuperRegsMarked(Reserved,
 578                                  {X86::SIL, X86::DIL, X86::BPL, X86::SPL,
 579                                   X86::SIH, X86::DIH, X86::BPH, X86::SPH}));
 580   return Reserved;
 581 }
 582
 583 void X86RegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const {
 584   // Check if the EFLAGS register is marked as live-out. This shouldn't happen,
 585   // because the calling convention defines the EFLAGS register as NOT
 586   // preserved.
 587   //
 588   // Unfortunatelly the EFLAGS show up as live-out after branch folding. Adding
 589   // an assert to track this and clear the register afterwards to avoid
 590   // unnecessary crashes during release builds.
 591   assert(!(Mask[X86::EFLAGS / 32] & (1U << (X86::EFLAGS % 32))) &&
 592          "EFLAGS are not live-out from a patchpoint.");
 593
 594   // Also clean other registers that don't need preserving (IP).
 595   for (auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP})
 596     Mask[Reg / 32] &= ~(1U << (Reg % 32));
 597 }
 598
 599 //===----------------------------------------------------------------------===//
 600 // Stack Frame Processing methods
 601 //===----------------------------------------------------------------------===//
 602
 603 static bool CantUseSP(const MachineFrameInfo &MFI) {
 604   return MFI.hasVarSizedObjects() || MFI.hasOpaqueSPAdjustment();
 605 }
 606
 607 bool X86RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
 608    const MachineFrameInfo &MFI = MF.getFrameInfo();
 609
 610    if (!EnableBasePointer)
 611      return false;
 612
 613    // When we need stack realignment, we can't address the stack from the frame
 614    // pointer.  When we have dynamic allocas or stack-adjusting inline asm, we
 615    // can't address variables from the stack pointer.  MS inline asm can
 616    // reference locals while also adjusting the stack pointer.  When we can't
 617    // use both the SP and the FP, we need a separate base pointer register.
 618    bool CantUseFP = needsStackRealignment(MF);
 619    return CantUseFP && CantUseSP(MFI);
 620 }
 621
 622 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
 623   if (!TargetRegisterInfo::canRealignStack(MF))
 624     return false;
 625
 626   const MachineFrameInfo &MFI = MF.getFrameInfo();
 627   const MachineRegisterInfo *MRI = &MF.getRegInfo();
 628
 629   // Stack realignment requires a frame pointer.  If we already started
 630   // register allocation with frame pointer elimination, it is too late now.
 631   if (!MRI->canReserveReg(FramePtr))
 632     return false;
 633
 634   // If a base pointer is necessary.  Check that it isn't too late to reserve
 635   // it.
 636   if (CantUseSP(MFI))
 637     return MRI->canReserveReg(BasePtr);
 638   return true;
 639 }
 640
 641 bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
 642                                            unsigned Reg, int &FrameIdx) const {
 643   // Since X86 defines assignCalleeSavedSpillSlots which always return true
 644   // this function neither used nor tested.
 645   llvm_unreachable("Unused function on X86. Otherwise need a test case.");
 646 }
 647
 648 // tryOptimizeLEAtoMOV - helper function that tries to replace a LEA instruction
 649 // of the form 'lea (%esp), %ebx' --> 'mov %esp, %ebx'.
 650 // TODO: In this case we should be really trying first to entirely eliminate
 651 // this instruction which is a plain copy.
 652 static bool tryOptimizeLEAtoMOV(MachineBasicBlock::iterator II) {
 653   MachineInstr &MI = *II;
 654   unsigned Opc = II->getOpcode();
 655   // Check if this is a LEA of the form 'lea (%esp), %ebx'
 656   if ((Opc != X86::LEA32r && Opc != X86::LEA64r && Opc != X86::LEA64_32r) ||
 657       MI.getOperand(2).getImm() != 1 ||
 658       MI.getOperand(3).getReg() != X86::NoRegister ||
 659       MI.getOperand(4).getImm() != 0 ||
 660       MI.getOperand(5).getReg() != X86::NoRegister)
 661     return false;
 662   unsigned BasePtr = MI.getOperand(1).getReg();
 663   // In X32 mode, ensure the base-pointer is a 32-bit operand, so the LEA will
 664   // be replaced with a 32-bit operand MOV which will zero extend the upper
 665   // 32-bits of the super register.
 666   if (Opc == X86::LEA64_32r)
 667     BasePtr = getX86SubSuperRegister(BasePtr, 32);
 668   unsigned NewDestReg = MI.getOperand(0).getReg();
 669   const X86InstrInfo *TII =
 670       MI.getParent()->getParent()->getSubtarget<X86Subtarget>().getInstrInfo();
 671   TII->copyPhysReg(*MI.getParent(), II, MI.getDebugLoc(), NewDestReg, BasePtr,
 672                    MI.getOperand(1).isKill());
 673   MI.eraseFromParent();
 674   return true;
 675 }
 676
 677 void
 678 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
 679                                      int SPAdj, unsigned FIOperandNum,
 680                                      RegScavenger *RS) const {
 681   MachineInstr &MI = *II;
 682   MachineFunction &MF = *MI.getParent()->getParent();
 683   const X86FrameLowering *TFI = getFrameLowering(MF);
 684   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
 685
 686   // Determine base register and offset.
 687   int FIOffset;
 688   unsigned BasePtr;
 689   if (MI.isReturn()) {
 690     assert((!needsStackRealignment(MF) ||
 691            MF.getFrameInfo().isFixedObjectIndex(FrameIndex)) &&
 692            "Return instruction can only reference SP relative frame objects");
 693     FIOffset = TFI->getFrameIndexReferenceSP(MF, FrameIndex, BasePtr, 0);
 694   } else {
 695     FIOffset = TFI->getFrameIndexReference(MF, FrameIndex, BasePtr);
 696   }
 697
 698   // LOCAL_ESCAPE uses a single offset, with no register. It only works in the
 699   // simple FP case, and doesn't work with stack realignment. On 32-bit, the
 700   // offset is from the traditional base pointer location.  On 64-bit, the
 701   // offset is from the SP at the end of the prologue, not the FP location. This
 702   // matches the behavior of llvm.frameaddress.
 703   unsigned Opc = MI.getOpcode();
 704   if (Opc == TargetOpcode::LOCAL_ESCAPE) {
 705     MachineOperand &FI = MI.getOperand(FIOperandNum);
 706     FI.ChangeToImmediate(FIOffset);
 707     return;
 708   }
 709
 710   // For LEA64_32r when BasePtr is 32-bits (X32) we can use full-size 64-bit
 711   // register as source operand, semantic is the same and destination is
 712   // 32-bits. It saves one byte per lea in code since 0x67 prefix is avoided.
 713   // Don't change BasePtr since it is used later for stack adjustment.
 714   unsigned MachineBasePtr = BasePtr;
 715   if (Opc == X86::LEA64_32r && X86::GR32RegClass.contains(BasePtr))
 716     MachineBasePtr = getX86SubSuperRegister(BasePtr, 64);
 717
 718   // This must be part of a four operand memory reference.  Replace the
 719   // FrameIndex with base register.  Add an offset to the offset.
 720   MI.getOperand(FIOperandNum).ChangeToRegister(MachineBasePtr, false);
 721
 722   if (BasePtr == StackPtr)
 723     FIOffset += SPAdj;
 724
 725   // The frame index format for stackmaps and patchpoints is different from the
 726   // X86 format. It only has a FI and an offset.
 727   if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
 728     assert(BasePtr == FramePtr && "Expected the FP as base register");
 729     int64_t Offset = MI.getOperand(FIOperandNum + 1).getImm() + FIOffset;
 730     MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
 731     return;
 732   }
 733
 734   if (MI.getOperand(FIOperandNum+3).isImm()) {
 735     // Offset is a 32-bit integer.
 736     int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
 737     int Offset = FIOffset + Imm;
 738     assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
 739            "Requesting 64-bit offset in 32-bit immediate!");
 740     if (Offset != 0 || !tryOptimizeLEAtoMOV(II))
 741       MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset);
 742   } else {
 743     // Offset is symbolic. This is extremely rare.
 744     uint64_t Offset = FIOffset +
 745       (uint64_t)MI.getOperand(FIOperandNum+3).getOffset();
 746     MI.getOperand(FIOperandNum + 3).setOffset(Offset);
 747   }
 748 }
 749
 750 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
 751   const X86FrameLowering *TFI = getFrameLowering(MF);
 752   return TFI->hasFP(MF) ? FramePtr : StackPtr;
 753 }
 754
 755 unsigned
 756 X86RegisterInfo::getPtrSizedFrameRegister(const MachineFunction &MF) const {
 757   const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
 758   unsigned FrameReg = getFrameRegister(MF);
 759   if (Subtarget.isTarget64BitILP32())
 760     FrameReg = getX86SubSuperRegister(FrameReg, 32);
 761   return FrameReg;
 762 }