lib/Target/X86/X86RegisterInfo.cpp

   1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file contains the X86 implementation of the TargetRegisterInfo class.
  10 // This file is responsible for the frame pointer elimination optimization
  11 // on X86.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "X86RegisterInfo.h"
  16 #include "X86FrameLowering.h"
  17 #include "X86MachineFunctionInfo.h"
  18 #include "X86Subtarget.h"
  19 #include "llvm/ADT/BitVector.h"
  20 #include "llvm/ADT/STLExtras.h"
  21 #include "llvm/CodeGen/MachineFrameInfo.h"
  22 #include "llvm/CodeGen/MachineFunction.h"
  23 #include "llvm/CodeGen/MachineFunctionPass.h"
  24 #include "llvm/CodeGen/MachineRegisterInfo.h"
  25 #include "llvm/CodeGen/TargetFrameLowering.h"
  26 #include "llvm/CodeGen/TargetInstrInfo.h"
  27 #include "llvm/IR/Constants.h"
  28 #include "llvm/IR/Function.h"
  29 #include "llvm/IR/Type.h"
  30 #include "llvm/Support/CommandLine.h"
  31 #include "llvm/Support/ErrorHandling.h"
  32 #include "llvm/Target/TargetMachine.h"
  33 #include "llvm/Target/TargetOptions.h"
  34
  35 using namespace llvm;
  36
  37 #define GET_REGINFO_TARGET_DESC
  38 #include "X86GenRegisterInfo.inc"
  39
  40 static cl::opt<bool>
  41 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
  42           cl::desc("Enable use of a base pointer for complex stack frames"));
  43
  44 X86RegisterInfo::X86RegisterInfo(const Triple &TT)
  45     : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP),
  46                          X86_MC::getDwarfRegFlavour(TT, false),
  47                          X86_MC::getDwarfRegFlavour(TT, true),
  48                          (TT.isArch64Bit() ? X86::RIP : X86::EIP)) {
  49   X86_MC::initLLVMToSEHAndCVRegMapping(this);
  50
  51   // Cache some information.
  52   Is64Bit = TT.isArch64Bit();
  53   IsWin64 = Is64Bit && TT.isOSWindows();
  54
  55   // Use a callee-saved register as the base pointer.  These registers must
  56   // not conflict with any ABI requirements.  For example, in 32-bit mode PIC
  57   // requires GOT in the EBX register before function calls via PLT GOT pointer.
  58   if (Is64Bit) {
  59     SlotSize = 8;
  60     // This matches the simplified 32-bit pointer code in the data layout
  61     // computation.
  62     // FIXME: Should use the data layout?
  63     bool Use64BitReg = TT.getEnvironment() != Triple::GNUX32;
  64     StackPtr = Use64BitReg ? X86::RSP : X86::ESP;
  65     FramePtr = Use64BitReg ? X86::RBP : X86::EBP;
  66     BasePtr = Use64BitReg ? X86::RBX : X86::EBX;
  67   } else {
  68     SlotSize = 4;
  69     StackPtr = X86::ESP;
  70     FramePtr = X86::EBP;
  71     BasePtr = X86::ESI;
  72   }
  73 }
  74
  75 bool
  76 X86RegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
  77   // ExecutionDomainFix, BreakFalseDeps and PostRAScheduler require liveness.
  78   return true;
  79 }
  80
  81 int
  82 X86RegisterInfo::getSEHRegNum(unsigned i) const {
  83   return getEncodingValue(i);
  84 }
  85
  86 const TargetRegisterClass *
  87 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
  88                                        unsigned Idx) const {
  89   // The sub_8bit sub-register index is more constrained in 32-bit mode.
  90   // It behaves just like the sub_8bit_hi index.
  91   if (!Is64Bit && Idx == X86::sub_8bit)
  92     Idx = X86::sub_8bit_hi;
  93
  94   // Forward to TableGen's default version.
  95   return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
  96 }
  97
  98 const TargetRegisterClass *
  99 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
 100                                           const TargetRegisterClass *B,
 101                                           unsigned SubIdx) const {
 102   // The sub_8bit sub-register index is more constrained in 32-bit mode.
 103   if (!Is64Bit && SubIdx == X86::sub_8bit) {
 104     A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
 105     if (!A)
 106       return nullptr;
 107   }
 108   return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
 109 }
 110
 111 const TargetRegisterClass *
 112 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
 113                                            const MachineFunction &MF) const {
 114   // Don't allow super-classes of GR8_NOREX.  This class is only used after
 115   // extracting sub_8bit_hi sub-registers.  The H sub-registers cannot be copied
 116   // to the full GR8 register class in 64-bit mode, so we cannot allow the
 117   // reigster class inflation.
 118   //
 119   // The GR8_NOREX class is always used in a way that won't be constrained to a
 120   // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
 121   // full GR8 class.
 122   if (RC == &X86::GR8_NOREXRegClass)
 123     return RC;
 124
 125   const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
 126
 127   const TargetRegisterClass *Super = RC;
 128   TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
 129   do {
 130     switch (Super->getID()) {
 131     case X86::FR32RegClassID:
 132     case X86::FR64RegClassID:
 133       // If AVX-512 isn't supported we should only inflate to these classes.
 134       if (!Subtarget.hasAVX512() &&
 135           getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
 136         return Super;
 137       break;
 138     case X86::VR128RegClassID:
 139     case X86::VR256RegClassID:
 140       // If VLX isn't supported we should only inflate to these classes.
 141       if (!Subtarget.hasVLX() &&
 142           getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
 143         return Super;
 144       break;
 145     case X86::VR128XRegClassID:
 146     case X86::VR256XRegClassID:
 147       // If VLX isn't support we shouldn't inflate to these classes.
 148       if (Subtarget.hasVLX() &&
 149           getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
 150         return Super;
 151       break;
 152     case X86::FR32XRegClassID:
 153     case X86::FR64XRegClassID:
 154       // If AVX-512 isn't support we shouldn't inflate to these classes.
 155       if (Subtarget.hasAVX512() &&
 156           getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
 157         return Super;
 158       break;
 159     case X86::GR8RegClassID:
 160     case X86::GR16RegClassID:
 161     case X86::GR32RegClassID:
 162     case X86::GR64RegClassID:
 163     case X86::RFP32RegClassID:
 164     case X86::RFP64RegClassID:
 165     case X86::RFP80RegClassID:
 166     case X86::VR512RegClassID:
 167       // Don't return a super-class that would shrink the spill size.
 168       // That can happen with the vector and float classes.
 169       if (getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
 170         return Super;
 171     }
 172     Super = *I++;
 173   } while (Super);
 174   return RC;
 175 }
 176
 177 const TargetRegisterClass *
 178 X86RegisterInfo::getPointerRegClass(const MachineFunction &MF,
 179                                     unsigned Kind) const {
 180   const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
 181   switch (Kind) {
 182   default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
 183   case 0: // Normal GPRs.
 184     if (Subtarget.isTarget64BitLP64())
 185       return &X86::GR64RegClass;
 186     // If the target is 64bit but we have been told to use 32bit addresses,
 187     // we can still use 64-bit register as long as we know the high bits
 188     // are zeros.
 189     // Reflect that in the returned register class.
 190     if (Is64Bit) {
 191       // When the target also allows 64-bit frame pointer and we do have a
 192       // frame, this is fine to use it for the address accesses as well.
 193       const X86FrameLowering *TFI = getFrameLowering(MF);
 194       return TFI->hasFP(MF) && TFI->Uses64BitFramePtr
 195                  ? &X86::LOW32_ADDR_ACCESS_RBPRegClass
 196                  : &X86::LOW32_ADDR_ACCESSRegClass;
 197     }
 198     return &X86::GR32RegClass;
 199   case 1: // Normal GPRs except the stack pointer (for encoding reasons).
 200     if (Subtarget.isTarget64BitLP64())
 201       return &X86::GR64_NOSPRegClass;
 202     // NOSP does not contain RIP, so no special case here.
 203     return &X86::GR32_NOSPRegClass;
 204   case 2: // NOREX GPRs.
 205     if (Subtarget.isTarget64BitLP64())
 206       return &X86::GR64_NOREXRegClass;
 207     return &X86::GR32_NOREXRegClass;
 208   case 3: // NOREX GPRs except the stack pointer (for encoding reasons).
 209     if (Subtarget.isTarget64BitLP64())
 210       return &X86::GR64_NOREX_NOSPRegClass;
 211     // NOSP does not contain RIP, so no special case here.
 212     return &X86::GR32_NOREX_NOSPRegClass;
 213   case 4: // Available for tailcall (not callee-saved GPRs).
 214     return getGPRsForTailCall(MF);
 215   }
 216 }
 217
 218 const TargetRegisterClass *
 219 X86RegisterInfo::getGPRsForTailCall(const MachineFunction &MF) const {
 220   const Function &F = MF.getFunction();
 221   if (IsWin64 || (F.getCallingConv() == CallingConv::Win64))
 222     return &X86::GR64_TCW64RegClass;
 223   else if (Is64Bit)
 224     return &X86::GR64_TCRegClass;
 225
 226   bool hasHipeCC = (F.getCallingConv() == CallingConv::HiPE);
 227   if (hasHipeCC)
 228     return &X86::GR32RegClass;
 229   return &X86::GR32_TCRegClass;
 230 }
 231
 232 const TargetRegisterClass *
 233 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
 234   if (RC == &X86::CCRRegClass) {
 235     if (Is64Bit)
 236       return &X86::GR64RegClass;
 237     else
 238       return &X86::GR32RegClass;
 239   }
 240   return RC;
 241 }
 242
 243 unsigned
 244 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
 245                                      MachineFunction &MF) const {
 246   const X86FrameLowering *TFI = getFrameLowering(MF);
 247
 248   unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
 249   switch (RC->getID()) {
 250   default:
 251     return 0;
 252   case X86::GR32RegClassID:
 253     return 4 - FPDiff;
 254   case X86::GR64RegClassID:
 255     return 12 - FPDiff;
 256   case X86::VR128RegClassID:
 257     return Is64Bit ? 10 : 4;
 258   case X86::VR64RegClassID:
 259     return 4;
 260   }
 261 }
 262
 263 const MCPhysReg *
 264 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
 265   assert(MF && "MachineFunction required");
 266
 267   const X86Subtarget &Subtarget = MF->getSubtarget<X86Subtarget>();
 268   const Function &F = MF->getFunction();
 269   bool HasSSE = Subtarget.hasSSE1();
 270   bool HasAVX = Subtarget.hasAVX();
 271   bool HasAVX512 = Subtarget.hasAVX512();
 272   bool CallsEHReturn = MF->callsEHReturn();
 273
 274   CallingConv::ID CC = F.getCallingConv();
 275
 276   // If attribute NoCallerSavedRegisters exists then we set X86_INTR calling
 277   // convention because it has the CSR list.
 278   if (MF->getFunction().hasFnAttribute("no_caller_saved_registers"))
 279     CC = CallingConv::X86_INTR;
 280
 281   switch (CC) {
 282   case CallingConv::GHC:
 283   case CallingConv::HiPE:
 284     return CSR_NoRegs_SaveList;
 285   case CallingConv::AnyReg:
 286     if (HasAVX)
 287       return CSR_64_AllRegs_AVX_SaveList;
 288     return CSR_64_AllRegs_SaveList;
 289   case CallingConv::PreserveMost:
 290     return CSR_64_RT_MostRegs_SaveList;
 291   case CallingConv::PreserveAll:
 292     if (HasAVX)
 293       return CSR_64_RT_AllRegs_AVX_SaveList;
 294     return CSR_64_RT_AllRegs_SaveList;
 295   case CallingConv::CXX_FAST_TLS:
 296     if (Is64Bit)
 297       return MF->getInfo<X86MachineFunctionInfo>()->isSplitCSR() ?
 298              CSR_64_CXX_TLS_Darwin_PE_SaveList : CSR_64_TLS_Darwin_SaveList;
 299     break;
 300   case CallingConv::Intel_OCL_BI: {
 301     if (HasAVX512 && IsWin64)
 302       return CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
 303     if (HasAVX512 && Is64Bit)
 304       return CSR_64_Intel_OCL_BI_AVX512_SaveList;
 305     if (HasAVX && IsWin64)
 306       return CSR_Win64_Intel_OCL_BI_AVX_SaveList;
 307     if (HasAVX && Is64Bit)
 308       return CSR_64_Intel_OCL_BI_AVX_SaveList;
 309     if (!HasAVX && !IsWin64 && Is64Bit)
 310       return CSR_64_Intel_OCL_BI_SaveList;
 311     break;
 312   }
 313   case CallingConv::HHVM:
 314     return CSR_64_HHVM_SaveList;
 315   case CallingConv::X86_RegCall:
 316     if (Is64Bit) {
 317       if (IsWin64) {
 318         return (HasSSE ? CSR_Win64_RegCall_SaveList :
 319                          CSR_Win64_RegCall_NoSSE_SaveList);
 320       } else {
 321         return (HasSSE ? CSR_SysV64_RegCall_SaveList :
 322                          CSR_SysV64_RegCall_NoSSE_SaveList);
 323       }
 324     } else {
 325       return (HasSSE ? CSR_32_RegCall_SaveList :
 326                        CSR_32_RegCall_NoSSE_SaveList);
 327     }
 328   case CallingConv::Cold:
 329     if (Is64Bit)
 330       return CSR_64_MostRegs_SaveList;
 331     break;
 332   case CallingConv::Win64:
 333     if (!HasSSE)
 334       return CSR_Win64_NoSSE_SaveList;
 335     return CSR_Win64_SaveList;
 336   case CallingConv::X86_64_SysV:
 337     if (CallsEHReturn)
 338       return CSR_64EHRet_SaveList;
 339     return CSR_64_SaveList;
 340   case CallingConv::X86_INTR:
 341     if (Is64Bit) {
 342       if (HasAVX512)
 343         return CSR_64_AllRegs_AVX512_SaveList;
 344       if (HasAVX)
 345         return CSR_64_AllRegs_AVX_SaveList;
 346       if (HasSSE)
 347         return CSR_64_AllRegs_SaveList;
 348       return CSR_64_AllRegs_NoSSE_SaveList;
 349     } else {
 350       if (HasAVX512)
 351         return CSR_32_AllRegs_AVX512_SaveList;
 352       if (HasAVX)
 353         return CSR_32_AllRegs_AVX_SaveList;
 354       if (HasSSE)
 355         return CSR_32_AllRegs_SSE_SaveList;
 356       return CSR_32_AllRegs_SaveList;
 357     }
 358   default:
 359     break;
 360   }
 361
 362   if (Is64Bit) {
 363     bool IsSwiftCC = Subtarget.getTargetLowering()->supportSwiftError() &&
 364                      F.getAttributes().hasAttrSomewhere(Attribute::SwiftError);
 365     if (IsSwiftCC)
 366       return IsWin64 ? CSR_Win64_SwiftError_SaveList
 367                      : CSR_64_SwiftError_SaveList;
 368
 369     if (IsWin64)
 370       return HasSSE ? CSR_Win64_SaveList : CSR_Win64_NoSSE_SaveList;
 371     if (CallsEHReturn)
 372       return CSR_64EHRet_SaveList;
 373     return CSR_64_SaveList;
 374   }
 375
 376   return CallsEHReturn ? CSR_32EHRet_SaveList : CSR_32_SaveList;
 377 }
 378
 379 const MCPhysReg *X86RegisterInfo::getCalleeSavedRegsViaCopy(
 380     const MachineFunction *MF) const {
 381   assert(MF && "Invalid MachineFunction pointer.");
 382   if (MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
 383       MF->getInfo<X86MachineFunctionInfo>()->isSplitCSR())
 384     return CSR_64_CXX_TLS_Darwin_ViaCopy_SaveList;
 385   return nullptr;
 386 }
 387
 388 const uint32_t *
 389 X86RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
 390                                       CallingConv::ID CC) const {
 391   const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
 392   bool HasSSE = Subtarget.hasSSE1();
 393   bool HasAVX = Subtarget.hasAVX();
 394   bool HasAVX512 = Subtarget.hasAVX512();
 395
 396   switch (CC) {
 397   case CallingConv::GHC:
 398   case CallingConv::HiPE:
 399     return CSR_NoRegs_RegMask;
 400   case CallingConv::AnyReg:
 401     if (HasAVX)
 402       return CSR_64_AllRegs_AVX_RegMask;
 403     return CSR_64_AllRegs_RegMask;
 404   case CallingConv::PreserveMost:
 405     return CSR_64_RT_MostRegs_RegMask;
 406   case CallingConv::PreserveAll:
 407     if (HasAVX)
 408       return CSR_64_RT_AllRegs_AVX_RegMask;
 409     return CSR_64_RT_AllRegs_RegMask;
 410   case CallingConv::CXX_FAST_TLS:
 411     if (Is64Bit)
 412       return CSR_64_TLS_Darwin_RegMask;
 413     break;
 414   case CallingConv::Intel_OCL_BI: {
 415     if (HasAVX512 && IsWin64)
 416       return CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
 417     if (HasAVX512 && Is64Bit)
 418       return CSR_64_Intel_OCL_BI_AVX512_RegMask;
 419     if (HasAVX && IsWin64)
 420       return CSR_Win64_Intel_OCL_BI_AVX_RegMask;
 421     if (HasAVX && Is64Bit)
 422       return CSR_64_Intel_OCL_BI_AVX_RegMask;
 423     if (!HasAVX && !IsWin64 && Is64Bit)
 424       return CSR_64_Intel_OCL_BI_RegMask;
 425     break;
 426   }
 427   case CallingConv::HHVM:
 428     return CSR_64_HHVM_RegMask;
 429   case CallingConv::X86_RegCall:
 430     if (Is64Bit) {
 431       if (IsWin64) {
 432         return (HasSSE ? CSR_Win64_RegCall_RegMask :
 433                          CSR_Win64_RegCall_NoSSE_RegMask);
 434       } else {
 435         return (HasSSE ? CSR_SysV64_RegCall_RegMask :
 436                          CSR_SysV64_RegCall_NoSSE_RegMask);
 437       }
 438     } else {
 439       return (HasSSE ? CSR_32_RegCall_RegMask :
 440                        CSR_32_RegCall_NoSSE_RegMask);
 441     }
 442   case CallingConv::Cold:
 443     if (Is64Bit)
 444       return CSR_64_MostRegs_RegMask;
 445     break;
 446   case CallingConv::Win64:
 447     return CSR_Win64_RegMask;
 448   case CallingConv::X86_64_SysV:
 449     return CSR_64_RegMask;
 450   case CallingConv::X86_INTR:
 451     if (Is64Bit) {
 452       if (HasAVX512)
 453         return CSR_64_AllRegs_AVX512_RegMask;
 454       if (HasAVX)
 455         return CSR_64_AllRegs_AVX_RegMask;
 456       if (HasSSE)
 457         return CSR_64_AllRegs_RegMask;
 458       return CSR_64_AllRegs_NoSSE_RegMask;
 459     } else {
 460       if (HasAVX512)
 461         return CSR_32_AllRegs_AVX512_RegMask;
 462       if (HasAVX)
 463         return CSR_32_AllRegs_AVX_RegMask;
 464       if (HasSSE)
 465         return CSR_32_AllRegs_SSE_RegMask;
 466       return CSR_32_AllRegs_RegMask;
 467     }
 468   default:
 469     break;
 470   }
 471
 472   // Unlike getCalleeSavedRegs(), we don't have MMI so we can't check
 473   // callsEHReturn().
 474   if (Is64Bit) {
 475     const Function &F = MF.getFunction();
 476     bool IsSwiftCC = Subtarget.getTargetLowering()->supportSwiftError() &&
 477                      F.getAttributes().hasAttrSomewhere(Attribute::SwiftError);
 478     if (IsSwiftCC)
 479       return IsWin64 ? CSR_Win64_SwiftError_RegMask : CSR_64_SwiftError_RegMask;
 480     return IsWin64 ? CSR_Win64_RegMask : CSR_64_RegMask;
 481   }
 482
 483   return CSR_32_RegMask;
 484 }
 485
 486 const uint32_t*
 487 X86RegisterInfo::getNoPreservedMask() const {
 488   return CSR_NoRegs_RegMask;
 489 }
 490
 491 const uint32_t *X86RegisterInfo::getDarwinTLSCallPreservedMask() const {
 492   return CSR_64_TLS_Darwin_RegMask;
 493 }
 494
 495 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
 496   BitVector Reserved(getNumRegs());
 497   const X86FrameLowering *TFI = getFrameLowering(MF);
 498
 499   // Set the floating point control register as reserved.
 500   Reserved.set(X86::FPCW);
 501
 502   // Set the stack-pointer register and its aliases as reserved.
 503   for (MCSubRegIterator I(X86::RSP, this, /*IncludeSelf=*/true); I.isValid();
 504        ++I)
 505     Reserved.set(*I);
 506
 507   // Set the Shadow Stack Pointer as reserved.
 508   Reserved.set(X86::SSP);
 509
 510   // Set the instruction pointer register and its aliases as reserved.
 511   for (MCSubRegIterator I(X86::RIP, this, /*IncludeSelf=*/true); I.isValid();
 512        ++I)
 513     Reserved.set(*I);
 514
 515   // Set the frame-pointer register and its aliases as reserved if needed.
 516   if (TFI->hasFP(MF)) {
 517     for (MCSubRegIterator I(X86::RBP, this, /*IncludeSelf=*/true); I.isValid();
 518          ++I)
 519       Reserved.set(*I);
 520   }
 521
 522   // Set the base-pointer register and its aliases as reserved if needed.
 523   if (hasBasePointer(MF)) {
 524     CallingConv::ID CC = MF.getFunction().getCallingConv();
 525     const uint32_t *RegMask = getCallPreservedMask(MF, CC);
 526     if (MachineOperand::clobbersPhysReg(RegMask, getBaseRegister()))
 527       report_fatal_error(
 528         "Stack realignment in presence of dynamic allocas is not supported with"
 529         "this calling convention.");
 530
 531     unsigned BasePtr = getX86SubSuperRegister(getBaseRegister(), 64);
 532     for (MCSubRegIterator I(BasePtr, this, /*IncludeSelf=*/true);
 533          I.isValid(); ++I)
 534       Reserved.set(*I);
 535   }
 536
 537   // Mark the segment registers as reserved.
 538   Reserved.set(X86::CS);
 539   Reserved.set(X86::SS);
 540   Reserved.set(X86::DS);
 541   Reserved.set(X86::ES);
 542   Reserved.set(X86::FS);
 543   Reserved.set(X86::GS);
 544
 545   // Mark the floating point stack registers as reserved.
 546   for (unsigned n = 0; n != 8; ++n)
 547     Reserved.set(X86::ST0 + n);
 548
 549   // Reserve the registers that only exist in 64-bit mode.
 550   if (!Is64Bit) {
 551     // These 8-bit registers are part of the x86-64 extension even though their
 552     // super-registers are old 32-bits.
 553     Reserved.set(X86::SIL);
 554     Reserved.set(X86::DIL);
 555     Reserved.set(X86::BPL);
 556     Reserved.set(X86::SPL);
 557     Reserved.set(X86::SIH);
 558     Reserved.set(X86::DIH);
 559     Reserved.set(X86::BPH);
 560     Reserved.set(X86::SPH);
 561
 562     for (unsigned n = 0; n != 8; ++n) {
 563       // R8, R9, ...
 564       for (MCRegAliasIterator AI(X86::R8 + n, this, true); AI.isValid(); ++AI)
 565         Reserved.set(*AI);
 566
 567       // XMM8, XMM9, ...
 568       for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI)
 569         Reserved.set(*AI);
 570     }
 571   }
 572   if (!Is64Bit || !MF.getSubtarget<X86Subtarget>().hasAVX512()) {
 573     for (unsigned n = 16; n != 32; ++n) {
 574       for (MCRegAliasIterator AI(X86::XMM0 + n, this, true); AI.isValid(); ++AI)
 575         Reserved.set(*AI);
 576     }
 577   }
 578
 579   assert(checkAllSuperRegsMarked(Reserved,
 580                                  {X86::SIL, X86::DIL, X86::BPL, X86::SPL,
 581                                   X86::SIH, X86::DIH, X86::BPH, X86::SPH}));
 582   return Reserved;
 583 }
 584
 585 void X86RegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const {
 586   // Check if the EFLAGS register is marked as live-out. This shouldn't happen,
 587   // because the calling convention defines the EFLAGS register as NOT
 588   // preserved.
 589   //
 590   // Unfortunatelly the EFLAGS show up as live-out after branch folding. Adding
 591   // an assert to track this and clear the register afterwards to avoid
 592   // unnecessary crashes during release builds.
 593   assert(!(Mask[X86::EFLAGS / 32] & (1U << (X86::EFLAGS % 32))) &&
 594          "EFLAGS are not live-out from a patchpoint.");
 595
 596   // Also clean other registers that don't need preserving (IP).
 597   for (auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP})
 598     Mask[Reg / 32] &= ~(1U << (Reg % 32));
 599 }
 600
 601 //===----------------------------------------------------------------------===//
 602 // Stack Frame Processing methods
 603 //===----------------------------------------------------------------------===//
 604
 605 static bool CantUseSP(const MachineFrameInfo &MFI) {
 606   return MFI.hasVarSizedObjects() || MFI.hasOpaqueSPAdjustment();
 607 }
 608
 609 bool X86RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
 610    const MachineFrameInfo &MFI = MF.getFrameInfo();
 611
 612    if (!EnableBasePointer)
 613      return false;
 614
 615    // When we need stack realignment, we can't address the stack from the frame
 616    // pointer.  When we have dynamic allocas or stack-adjusting inline asm, we
 617    // can't address variables from the stack pointer.  MS inline asm can
 618    // reference locals while also adjusting the stack pointer.  When we can't
 619    // use both the SP and the FP, we need a separate base pointer register.
 620    bool CantUseFP = needsStackRealignment(MF);
 621    return CantUseFP && CantUseSP(MFI);
 622 }
 623
 624 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
 625   if (!TargetRegisterInfo::canRealignStack(MF))
 626     return false;
 627
 628   const MachineFrameInfo &MFI = MF.getFrameInfo();
 629   const MachineRegisterInfo *MRI = &MF.getRegInfo();
 630
 631   // Stack realignment requires a frame pointer.  If we already started
 632   // register allocation with frame pointer elimination, it is too late now.
 633   if (!MRI->canReserveReg(FramePtr))
 634     return false;
 635
 636   // If a base pointer is necessary.  Check that it isn't too late to reserve
 637   // it.
 638   if (CantUseSP(MFI))
 639     return MRI->canReserveReg(BasePtr);
 640   return true;
 641 }
 642
 643 bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
 644                                            unsigned Reg, int &FrameIdx) const {
 645   // Since X86 defines assignCalleeSavedSpillSlots which always return true
 646   // this function neither used nor tested.
 647   llvm_unreachable("Unused function on X86. Otherwise need a test case.");
 648 }
 649
 650 // tryOptimizeLEAtoMOV - helper function that tries to replace a LEA instruction
 651 // of the form 'lea (%esp), %ebx' --> 'mov %esp, %ebx'.
 652 // TODO: In this case we should be really trying first to entirely eliminate
 653 // this instruction which is a plain copy.
 654 static bool tryOptimizeLEAtoMOV(MachineBasicBlock::iterator II) {
 655   MachineInstr &MI = *II;
 656   unsigned Opc = II->getOpcode();
 657   // Check if this is a LEA of the form 'lea (%esp), %ebx'
 658   if ((Opc != X86::LEA32r && Opc != X86::LEA64r && Opc != X86::LEA64_32r) ||
 659       MI.getOperand(2).getImm() != 1 ||
 660       MI.getOperand(3).getReg() != X86::NoRegister ||
 661       MI.getOperand(4).getImm() != 0 ||
 662       MI.getOperand(5).getReg() != X86::NoRegister)
 663     return false;
 664   unsigned BasePtr = MI.getOperand(1).getReg();
 665   // In X32 mode, ensure the base-pointer is a 32-bit operand, so the LEA will
 666   // be replaced with a 32-bit operand MOV which will zero extend the upper
 667   // 32-bits of the super register.
 668   if (Opc == X86::LEA64_32r)
 669     BasePtr = getX86SubSuperRegister(BasePtr, 32);
 670   unsigned NewDestReg = MI.getOperand(0).getReg();
 671   const X86InstrInfo *TII =
 672       MI.getParent()->getParent()->getSubtarget<X86Subtarget>().getInstrInfo();
 673   TII->copyPhysReg(*MI.getParent(), II, MI.getDebugLoc(), NewDestReg, BasePtr,
 674                    MI.getOperand(1).isKill());
 675   MI.eraseFromParent();
 676   return true;
 677 }
 678
 679 void
 680 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
 681                                      int SPAdj, unsigned FIOperandNum,
 682                                      RegScavenger *RS) const {
 683   MachineInstr &MI = *II;
 684   MachineFunction &MF = *MI.getParent()->getParent();
 685   const X86FrameLowering *TFI = getFrameLowering(MF);
 686   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
 687
 688   // Determine base register and offset.
 689   int FIOffset;
 690   unsigned BasePtr;
 691   if (MI.isReturn()) {
 692     assert((!needsStackRealignment(MF) ||
 693            MF.getFrameInfo().isFixedObjectIndex(FrameIndex)) &&
 694            "Return instruction can only reference SP relative frame objects");
 695     FIOffset = TFI->getFrameIndexReferenceSP(MF, FrameIndex, BasePtr, 0);
 696   } else {
 697     FIOffset = TFI->getFrameIndexReference(MF, FrameIndex, BasePtr);
 698   }
 699
 700   // LOCAL_ESCAPE uses a single offset, with no register. It only works in the
 701   // simple FP case, and doesn't work with stack realignment. On 32-bit, the
 702   // offset is from the traditional base pointer location.  On 64-bit, the
 703   // offset is from the SP at the end of the prologue, not the FP location. This
 704   // matches the behavior of llvm.frameaddress.
 705   unsigned Opc = MI.getOpcode();
 706   if (Opc == TargetOpcode::LOCAL_ESCAPE) {
 707     MachineOperand &FI = MI.getOperand(FIOperandNum);
 708     FI.ChangeToImmediate(FIOffset);
 709     return;
 710   }
 711
 712   // For LEA64_32r when BasePtr is 32-bits (X32) we can use full-size 64-bit
 713   // register as source operand, semantic is the same and destination is
 714   // 32-bits. It saves one byte per lea in code since 0x67 prefix is avoided.
 715   // Don't change BasePtr since it is used later for stack adjustment.
 716   unsigned MachineBasePtr = BasePtr;
 717   if (Opc == X86::LEA64_32r && X86::GR32RegClass.contains(BasePtr))
 718     MachineBasePtr = getX86SubSuperRegister(BasePtr, 64);
 719
 720   // This must be part of a four operand memory reference.  Replace the
 721   // FrameIndex with base register.  Add an offset to the offset.
 722   MI.getOperand(FIOperandNum).ChangeToRegister(MachineBasePtr, false);
 723
 724   if (BasePtr == StackPtr)
 725     FIOffset += SPAdj;
 726
 727   // The frame index format for stackmaps and patchpoints is different from the
 728   // X86 format. It only has a FI and an offset.
 729   if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
 730     assert(BasePtr == FramePtr && "Expected the FP as base register");
 731     int64_t Offset = MI.getOperand(FIOperandNum + 1).getImm() + FIOffset;
 732     MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
 733     return;
 734   }
 735
 736   if (MI.getOperand(FIOperandNum+3).isImm()) {
 737     // Offset is a 32-bit integer.
 738     int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
 739     int Offset = FIOffset + Imm;
 740     assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
 741            "Requesting 64-bit offset in 32-bit immediate!");
 742     if (Offset != 0 || !tryOptimizeLEAtoMOV(II))
 743       MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset);
 744   } else {
 745     // Offset is symbolic. This is extremely rare.
 746     uint64_t Offset = FIOffset +
 747       (uint64_t)MI.getOperand(FIOperandNum+3).getOffset();
 748     MI.getOperand(FIOperandNum + 3).setOffset(Offset);
 749   }
 750 }
 751
 752 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
 753   const X86FrameLowering *TFI = getFrameLowering(MF);
 754   return TFI->hasFP(MF) ? FramePtr : StackPtr;
 755 }
 756
 757 unsigned
 758 X86RegisterInfo::getPtrSizedFrameRegister(const MachineFunction &MF) const {
 759   const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
 760   unsigned FrameReg = getFrameRegister(MF);
 761   if (Subtarget.isTarget64BitILP32())
 762     FrameReg = getX86SubSuperRegister(FrameReg, 32);
 763   return FrameReg;
 764 }
 765
 766 unsigned
 767 X86RegisterInfo::getPtrSizedStackRegister(const MachineFunction &MF) const {
 768   const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
 769   unsigned StackReg = getStackRegister();
 770   if (Subtarget.isTarget64BitILP32())
 771     StackReg = getX86SubSuperRegister(StackReg, 32);
 772   return StackReg;
 773 }