[DAGCombiner] Eliminate dead stores to stack.
[llvm-complete.git] / lib / Target / SystemZ / SystemZISelLowering.h
blob8efe2204581575cc2abc5d238ceed2b7ceba9c92
1 //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that SystemZ uses to lower LLVM code into a
10 // selection DAG.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
15 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
17 #include "SystemZ.h"
18 #include "SystemZInstrInfo.h"
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/TargetLowering.h"
23 namespace llvm {
24 namespace SystemZISD {
25 enum NodeType : unsigned {
26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
28 // Return with a flag operand. Operand 0 is the chain operand.
29 RET_FLAG,
31 // Calls a function. Operand 0 is the chain operand and operand 1
32 // is the target address. The arguments start at operand 2.
33 // There is an optional glue operand at the end.
34 CALL,
35 SIBCALL,
37 // TLS calls. Like regular calls, except operand 1 is the TLS symbol.
38 // (The call target is implicitly __tls_get_offset.)
39 TLS_GDCALL,
40 TLS_LDCALL,
42 // Wraps a TargetGlobalAddress that should be loaded using PC-relative
43 // accesses (LARL). Operand 0 is the address.
44 PCREL_WRAPPER,
46 // Used in cases where an offset is applied to a TargetGlobalAddress.
47 // Operand 0 is the full TargetGlobalAddress and operand 1 is a
48 // PCREL_WRAPPER for an anchor point. This is used so that we can
49 // cheaply refer to either the full address or the anchor point
50 // as a register base.
51 PCREL_OFFSET,
53 // Integer absolute.
54 IABS,
56 // Integer comparisons. There are three operands: the two values
57 // to compare, and an integer of type SystemZICMP.
58 ICMP,
60 // Floating-point comparisons. The two operands are the values to compare.
61 FCMP,
63 // Test under mask. The first operand is ANDed with the second operand
64 // and the condition codes are set on the result. The third operand is
65 // a boolean that is true if the condition codes need to distinguish
66 // between CCMASK_TM_MIXED_MSB_0 and CCMASK_TM_MIXED_MSB_1 (which the
67 // register forms do but the memory forms don't).
68 TM,
70 // Branches if a condition is true. Operand 0 is the chain operand;
71 // operand 1 is the 4-bit condition-code mask, with bit N in
72 // big-endian order meaning "branch if CC=N"; operand 2 is the
73 // target block and operand 3 is the flag operand.
74 BR_CCMASK,
76 // Selects between operand 0 and operand 1. Operand 2 is the
77 // mask of condition-code values for which operand 0 should be
78 // chosen over operand 1; it has the same form as BR_CCMASK.
79 // Operand 3 is the flag operand.
80 SELECT_CCMASK,
82 // Evaluates to the gap between the stack pointer and the
83 // base of the dynamically-allocatable area.
84 ADJDYNALLOC,
86 // Count number of bits set in operand 0 per byte.
87 POPCNT,
89 // Wrappers around the ISD opcodes of the same name. The output is GR128.
90 // Input operands may be GR64 or GR32, depending on the instruction.
91 SMUL_LOHI,
92 UMUL_LOHI,
93 SDIVREM,
94 UDIVREM,
96 // Add/subtract with overflow/carry. These have the same operands as
97 // the corresponding standard operations, except with the carry flag
98 // replaced by a condition code value.
99 SADDO, SSUBO, UADDO, USUBO, ADDCARRY, SUBCARRY,
101 // Set the condition code from a boolean value in operand 0.
102 // Operand 1 is a mask of all condition-code values that may result of this
103 // operation, operand 2 is a mask of condition-code values that may result
104 // if the boolean is true.
105 // Note that this operation is always optimized away, we will never
106 // generate any code for it.
107 GET_CCMASK,
109 // Use a series of MVCs to copy bytes from one memory location to another.
110 // The operands are:
111 // - the target address
112 // - the source address
113 // - the constant length
115 // This isn't a memory opcode because we'd need to attach two
116 // MachineMemOperands rather than one.
117 MVC,
119 // Like MVC, but implemented as a loop that handles X*256 bytes
120 // followed by straight-line code to handle the rest (if any).
121 // The value of X is passed as an additional operand.
122 MVC_LOOP,
124 // Similar to MVC and MVC_LOOP, but for logic operations (AND, OR, XOR).
126 NC_LOOP,
128 OC_LOOP,
130 XC_LOOP,
132 // Use CLC to compare two blocks of memory, with the same comments
133 // as for MVC and MVC_LOOP.
134 CLC,
135 CLC_LOOP,
137 // Use an MVST-based sequence to implement stpcpy().
138 STPCPY,
140 // Use a CLST-based sequence to implement strcmp(). The two input operands
141 // are the addresses of the strings to compare.
142 STRCMP,
144 // Use an SRST-based sequence to search a block of memory. The first
145 // operand is the end address, the second is the start, and the third
146 // is the character to search for. CC is set to 1 on success and 2
147 // on failure.
148 SEARCH_STRING,
150 // Store the CC value in bits 29 and 28 of an integer.
151 IPM,
153 // Compiler barrier only; generate a no-op.
154 MEMBARRIER,
156 // Transaction begin. The first operand is the chain, the second
157 // the TDB pointer, and the third the immediate control field.
158 // Returns CC value and chain.
159 TBEGIN,
160 TBEGIN_NOFLOAT,
162 // Transaction end. Just the chain operand. Returns CC value and chain.
163 TEND,
165 // Create a vector constant by replicating an element-sized RISBG-style mask.
166 // The first operand specifies the starting set bit and the second operand
167 // specifies the ending set bit. Both operands count from the MSB of the
168 // element.
169 ROTATE_MASK,
171 // Replicate a GPR scalar value into all elements of a vector.
172 REPLICATE,
174 // Create a vector from two i64 GPRs.
175 JOIN_DWORDS,
177 // Replicate one element of a vector into all elements. The first operand
178 // is the vector and the second is the index of the element to replicate.
179 SPLAT,
181 // Interleave elements from the high half of operand 0 and the high half
182 // of operand 1.
183 MERGE_HIGH,
185 // Likewise for the low halves.
186 MERGE_LOW,
188 // Concatenate the vectors in the first two operands, shift them left
189 // by the third operand, and take the first half of the result.
190 SHL_DOUBLE,
192 // Take one element of the first v2i64 operand and the one element of
193 // the second v2i64 operand and concatenate them to form a v2i64 result.
194 // The third operand is a 4-bit value of the form 0A0B, where A and B
195 // are the element selectors for the first operand and second operands
196 // respectively.
197 PERMUTE_DWORDS,
199 // Perform a general vector permute on vector operands 0 and 1.
200 // Each byte of operand 2 controls the corresponding byte of the result,
201 // in the same way as a byte-level VECTOR_SHUFFLE mask.
202 PERMUTE,
204 // Pack vector operands 0 and 1 into a single vector with half-sized elements.
205 PACK,
207 // Likewise, but saturate the result and set CC. PACKS_CC does signed
208 // saturation and PACKLS_CC does unsigned saturation.
209 PACKS_CC,
210 PACKLS_CC,
212 // Unpack the first half of vector operand 0 into double-sized elements.
213 // UNPACK_HIGH sign-extends and UNPACKL_HIGH zero-extends.
214 UNPACK_HIGH,
215 UNPACKL_HIGH,
217 // Likewise for the second half.
218 UNPACK_LOW,
219 UNPACKL_LOW,
221 // Shift each element of vector operand 0 by the number of bits specified
222 // by scalar operand 1.
223 VSHL_BY_SCALAR,
224 VSRL_BY_SCALAR,
225 VSRA_BY_SCALAR,
227 // For each element of the output type, sum across all sub-elements of
228 // operand 0 belonging to the corresponding element, and add in the
229 // rightmost sub-element of the corresponding element of operand 1.
230 VSUM,
232 // Compare integer vector operands 0 and 1 to produce the usual 0/-1
233 // vector result. VICMPE is for equality, VICMPH for "signed greater than"
234 // and VICMPHL for "unsigned greater than".
235 VICMPE,
236 VICMPH,
237 VICMPHL,
239 // Likewise, but also set the condition codes on the result.
240 VICMPES,
241 VICMPHS,
242 VICMPHLS,
244 // Compare floating-point vector operands 0 and 1 to preoduce the usual 0/-1
245 // vector result. VFCMPE is for "ordered and equal", VFCMPH for "ordered and
246 // greater than" and VFCMPHE for "ordered and greater than or equal to".
247 VFCMPE,
248 VFCMPH,
249 VFCMPHE,
251 // Likewise, but also set the condition codes on the result.
252 VFCMPES,
253 VFCMPHS,
254 VFCMPHES,
256 // Test floating-point data class for vectors.
257 VFTCI,
259 // Extend the even f32 elements of vector operand 0 to produce a vector
260 // of f64 elements.
261 VEXTEND,
263 // Round the f64 elements of vector operand 0 to f32s and store them in the
264 // even elements of the result.
265 VROUND,
267 // AND the two vector operands together and set CC based on the result.
268 VTM,
270 // String operations that set CC as a side-effect.
271 VFAE_CC,
272 VFAEZ_CC,
273 VFEE_CC,
274 VFEEZ_CC,
275 VFENE_CC,
276 VFENEZ_CC,
277 VISTR_CC,
278 VSTRC_CC,
279 VSTRCZ_CC,
281 // Test Data Class.
283 // Operand 0: the value to test
284 // Operand 1: the bit mask
285 TDC,
287 // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
288 // ATOMIC_LOAD_<op>.
290 // Operand 0: the address of the containing 32-bit-aligned field
291 // Operand 1: the second operand of <op>, in the high bits of an i32
292 // for everything except ATOMIC_SWAPW
293 // Operand 2: how many bits to rotate the i32 left to bring the first
294 // operand into the high bits
295 // Operand 3: the negative of operand 2, for rotating the other way
296 // Operand 4: the width of the field in bits (8 or 16)
297 ATOMIC_SWAPW = ISD::FIRST_TARGET_MEMORY_OPCODE,
298 ATOMIC_LOADW_ADD,
299 ATOMIC_LOADW_SUB,
300 ATOMIC_LOADW_AND,
301 ATOMIC_LOADW_OR,
302 ATOMIC_LOADW_XOR,
303 ATOMIC_LOADW_NAND,
304 ATOMIC_LOADW_MIN,
305 ATOMIC_LOADW_MAX,
306 ATOMIC_LOADW_UMIN,
307 ATOMIC_LOADW_UMAX,
309 // A wrapper around the inner loop of an ATOMIC_CMP_SWAP.
311 // Operand 0: the address of the containing 32-bit-aligned field
312 // Operand 1: the compare value, in the low bits of an i32
313 // Operand 2: the swap value, in the low bits of an i32
314 // Operand 3: how many bits to rotate the i32 left to bring the first
315 // operand into the high bits
316 // Operand 4: the negative of operand 2, for rotating the other way
317 // Operand 5: the width of the field in bits (8 or 16)
318 ATOMIC_CMP_SWAPW,
320 // Atomic compare-and-swap returning CC value.
321 // Val, CC, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap)
322 ATOMIC_CMP_SWAP,
324 // 128-bit atomic load.
325 // Val, OUTCHAIN = ATOMIC_LOAD_128(INCHAIN, ptr)
326 ATOMIC_LOAD_128,
328 // 128-bit atomic store.
329 // OUTCHAIN = ATOMIC_STORE_128(INCHAIN, val, ptr)
330 ATOMIC_STORE_128,
332 // 128-bit atomic compare-and-swap.
333 // Val, CC, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap)
334 ATOMIC_CMP_SWAP_128,
336 // Byte swapping load/store. Same operands as regular load/store.
337 LRV, STRV,
339 // Prefetch from the second operand using the 4-bit control code in
340 // the first operand. The code is 1 for a load prefetch and 2 for
341 // a store prefetch.
342 PREFETCH
345 // Return true if OPCODE is some kind of PC-relative address.
346 inline bool isPCREL(unsigned Opcode) {
347 return Opcode == PCREL_WRAPPER || Opcode == PCREL_OFFSET;
349 } // end namespace SystemZISD
351 namespace SystemZICMP {
352 // Describes whether an integer comparison needs to be signed or unsigned,
353 // or whether either type is OK.
354 enum {
355 Any,
356 UnsignedOnly,
357 SignedOnly
359 } // end namespace SystemZICMP
361 class SystemZSubtarget;
362 class SystemZTargetMachine;
364 class SystemZTargetLowering : public TargetLowering {
365 public:
366 explicit SystemZTargetLowering(const TargetMachine &TM,
367 const SystemZSubtarget &STI);
369 // Override TargetLowering.
370 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
371 return MVT::i32;
373 MVT getVectorIdxTy(const DataLayout &DL) const override {
374 // Only the lower 12 bits of an element index are used, so we don't
375 // want to clobber the upper 32 bits of a GPR unnecessarily.
376 return MVT::i32;
378 TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT)
379 const override {
380 // Widen subvectors to the full width rather than promoting integer
381 // elements. This is better because:
383 // (a) it means that we can handle the ABI for passing and returning
384 // sub-128 vectors without having to handle them as legal types.
386 // (b) we don't have instructions to extend on load and truncate on store,
387 // so promoting the integers is less efficient.
389 // (c) there are no multiplication instructions for the widest integer
390 // type (v2i64).
391 if (VT.getScalarSizeInBits() % 8 == 0)
392 return TypeWidenVector;
393 return TargetLoweringBase::getPreferredVectorAction(VT);
395 bool isCheapToSpeculateCtlz() const override { return true; }
396 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &,
397 EVT) const override;
398 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
399 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
400 bool isLegalICmpImmediate(int64_t Imm) const override;
401 bool isLegalAddImmediate(int64_t Imm) const override;
402 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
403 unsigned AS,
404 Instruction *I = nullptr) const override;
405 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
406 unsigned Align,
407 bool *Fast) const override;
408 bool isTruncateFree(Type *, Type *) const override;
409 bool isTruncateFree(EVT, EVT) const override;
410 const char *getTargetNodeName(unsigned Opcode) const override;
411 std::pair<unsigned, const TargetRegisterClass *>
412 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
413 StringRef Constraint, MVT VT) const override;
414 TargetLowering::ConstraintType
415 getConstraintType(StringRef Constraint) const override;
416 TargetLowering::ConstraintWeight
417 getSingleConstraintMatchWeight(AsmOperandInfo &info,
418 const char *constraint) const override;
419 void LowerAsmOperandForConstraint(SDValue Op,
420 std::string &Constraint,
421 std::vector<SDValue> &Ops,
422 SelectionDAG &DAG) const override;
424 unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
425 if (ConstraintCode.size() == 1) {
426 switch(ConstraintCode[0]) {
427 default:
428 break;
429 case 'o':
430 return InlineAsm::Constraint_o;
431 case 'Q':
432 return InlineAsm::Constraint_Q;
433 case 'R':
434 return InlineAsm::Constraint_R;
435 case 'S':
436 return InlineAsm::Constraint_S;
437 case 'T':
438 return InlineAsm::Constraint_T;
441 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
444 /// If a physical register, this returns the register that receives the
445 /// exception address on entry to an EH pad.
446 unsigned
447 getExceptionPointerRegister(const Constant *PersonalityFn) const override {
448 return SystemZ::R6D;
451 /// If a physical register, this returns the register that receives the
452 /// exception typeid on entry to a landing pad.
453 unsigned
454 getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
455 return SystemZ::R7D;
458 /// Override to support customized stack guard loading.
459 bool useLoadStackGuardNode() const override {
460 return true;
462 void insertSSPDeclarations(Module &M) const override {
465 MachineBasicBlock *
466 EmitInstrWithCustomInserter(MachineInstr &MI,
467 MachineBasicBlock *BB) const override;
468 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
469 void LowerOperationWrapper(SDNode *N, SmallVectorImpl<SDValue> &Results,
470 SelectionDAG &DAG) const override;
471 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
472 SelectionDAG &DAG) const override;
473 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
474 bool allowTruncateForTailCall(Type *, Type *) const override;
475 bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
476 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
477 bool isVarArg,
478 const SmallVectorImpl<ISD::InputArg> &Ins,
479 const SDLoc &DL, SelectionDAG &DAG,
480 SmallVectorImpl<SDValue> &InVals) const override;
481 SDValue LowerCall(CallLoweringInfo &CLI,
482 SmallVectorImpl<SDValue> &InVals) const override;
484 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
485 bool isVarArg,
486 const SmallVectorImpl<ISD::OutputArg> &Outs,
487 LLVMContext &Context) const override;
488 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
489 const SmallVectorImpl<ISD::OutputArg> &Outs,
490 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
491 SelectionDAG &DAG) const override;
492 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
494 /// Determine which of the bits specified in Mask are known to be either
495 /// zero or one and return them in the KnownZero/KnownOne bitsets.
496 void computeKnownBitsForTargetNode(const SDValue Op,
497 KnownBits &Known,
498 const APInt &DemandedElts,
499 const SelectionDAG &DAG,
500 unsigned Depth = 0) const override;
502 /// Determine the number of bits in the operation that are sign bits.
503 unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
504 const APInt &DemandedElts,
505 const SelectionDAG &DAG,
506 unsigned Depth) const override;
508 ISD::NodeType getExtendForAtomicOps() const override {
509 return ISD::ANY_EXTEND;
512 bool supportSwiftError() const override {
513 return true;
516 static bool tryBuildVectorByteMask(BuildVectorSDNode *BVN, uint64_t &Mask);
517 static bool analyzeFPImm(const APFloat &Imm, unsigned BitWidth,
518 unsigned &Start, unsigned &End, const SystemZInstrInfo *TII);
519 private:
520 const SystemZSubtarget &Subtarget;
522 // Implement LowerOperation for individual opcodes.
523 SDValue getVectorCmp(SelectionDAG &DAG, unsigned Opcode,
524 const SDLoc &DL, EVT VT,
525 SDValue CmpOp0, SDValue CmpOp1) const;
526 SDValue lowerVectorSETCC(SelectionDAG &DAG, const SDLoc &DL,
527 EVT VT, ISD::CondCode CC,
528 SDValue CmpOp0, SDValue CmpOp1) const;
529 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
530 SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
531 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
532 SDValue lowerGlobalAddress(GlobalAddressSDNode *Node,
533 SelectionDAG &DAG) const;
534 SDValue lowerTLSGetOffset(GlobalAddressSDNode *Node,
535 SelectionDAG &DAG, unsigned Opcode,
536 SDValue GOTOffset) const;
537 SDValue lowerThreadPointer(const SDLoc &DL, SelectionDAG &DAG) const;
538 SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
539 SelectionDAG &DAG) const;
540 SDValue lowerBlockAddress(BlockAddressSDNode *Node,
541 SelectionDAG &DAG) const;
542 SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const;
543 SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;
544 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
545 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
546 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
547 SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
548 SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
549 SDValue lowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const;
550 SDValue lowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
551 SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
552 SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
553 SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
554 SDValue lowerXALUO(SDValue Op, SelectionDAG &DAG) const;
555 SDValue lowerADDSUBCARRY(SDValue Op, SelectionDAG &DAG) const;
556 SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
557 SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
558 SDValue lowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
559 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
560 SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const;
561 SDValue lowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
562 SDValue lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG,
563 unsigned Opcode) const;
564 SDValue lowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
565 SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
566 SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
567 SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
568 SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
569 SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
570 SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
571 SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
572 SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
573 SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
574 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
575 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
576 SDValue lowerExtendVectorInreg(SDValue Op, SelectionDAG &DAG,
577 unsigned UnpackHigh) const;
578 SDValue lowerShift(SDValue Op, SelectionDAG &DAG, unsigned ByScalar) const;
580 bool canTreatAsByteVector(EVT VT) const;
581 SDValue combineExtract(const SDLoc &DL, EVT ElemVT, EVT VecVT, SDValue OrigOp,
582 unsigned Index, DAGCombinerInfo &DCI,
583 bool Force) const;
584 SDValue combineTruncateExtract(const SDLoc &DL, EVT TruncVT, SDValue Op,
585 DAGCombinerInfo &DCI) const;
586 SDValue combineZERO_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
587 SDValue combineSIGN_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
588 SDValue combineSIGN_EXTEND_INREG(SDNode *N, DAGCombinerInfo &DCI) const;
589 SDValue combineMERGE(SDNode *N, DAGCombinerInfo &DCI) const;
590 SDValue combineLOAD(SDNode *N, DAGCombinerInfo &DCI) const;
591 SDValue combineSTORE(SDNode *N, DAGCombinerInfo &DCI) const;
592 SDValue combineEXTRACT_VECTOR_ELT(SDNode *N, DAGCombinerInfo &DCI) const;
593 SDValue combineJOIN_DWORDS(SDNode *N, DAGCombinerInfo &DCI) const;
594 SDValue combineFP_ROUND(SDNode *N, DAGCombinerInfo &DCI) const;
595 SDValue combineFP_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
596 SDValue combineBSWAP(SDNode *N, DAGCombinerInfo &DCI) const;
597 SDValue combineBR_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;
598 SDValue combineSELECT_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;
599 SDValue combineGET_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;
600 SDValue combineIntDIVREM(SDNode *N, DAGCombinerInfo &DCI) const;
602 SDValue unwrapAddress(SDValue N) const override;
604 // If the last instruction before MBBI in MBB was some form of COMPARE,
605 // try to replace it with a COMPARE AND BRANCH just before MBBI.
606 // CCMask and Target are the BRC-like operands for the branch.
607 // Return true if the change was made.
608 bool convertPrevCompareToBranch(MachineBasicBlock *MBB,
609 MachineBasicBlock::iterator MBBI,
610 unsigned CCMask,
611 MachineBasicBlock *Target) const;
613 // Implement EmitInstrWithCustomInserter for individual operation types.
614 MachineBasicBlock *emitSelect(MachineInstr &MI, MachineBasicBlock *BB) const;
615 MachineBasicBlock *emitCondStore(MachineInstr &MI, MachineBasicBlock *BB,
616 unsigned StoreOpcode, unsigned STOCOpcode,
617 bool Invert) const;
618 MachineBasicBlock *emitPair128(MachineInstr &MI,
619 MachineBasicBlock *MBB) const;
620 MachineBasicBlock *emitExt128(MachineInstr &MI, MachineBasicBlock *MBB,
621 bool ClearEven) const;
622 MachineBasicBlock *emitAtomicLoadBinary(MachineInstr &MI,
623 MachineBasicBlock *BB,
624 unsigned BinOpcode, unsigned BitSize,
625 bool Invert = false) const;
626 MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr &MI,
627 MachineBasicBlock *MBB,
628 unsigned CompareOpcode,
629 unsigned KeepOldMask,
630 unsigned BitSize) const;
631 MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr &MI,
632 MachineBasicBlock *BB) const;
633 MachineBasicBlock *emitMemMemWrapper(MachineInstr &MI, MachineBasicBlock *BB,
634 unsigned Opcode) const;
635 MachineBasicBlock *emitStringWrapper(MachineInstr &MI, MachineBasicBlock *BB,
636 unsigned Opcode) const;
637 MachineBasicBlock *emitTransactionBegin(MachineInstr &MI,
638 MachineBasicBlock *MBB,
639 unsigned Opcode, bool NoFloat) const;
640 MachineBasicBlock *emitLoadAndTestCmp0(MachineInstr &MI,
641 MachineBasicBlock *MBB,
642 unsigned Opcode) const;
644 const TargetRegisterClass *getRepRegClassFor(MVT VT) const override;
646 } // end namespace llvm
648 #endif