include/llvm/CodeGen/SelectionDAGISel.h

   1 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file implements the SelectionDAGISel class, which is used as the common
  10 // base class for SelectionDAG-based instruction selectors.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_CODEGEN_SELECTIONDAGISEL_H
  15 #define LLVM_CODEGEN_SELECTIONDAGISEL_H
  16
  17 #include "llvm/CodeGen/MachineFunctionPass.h"
  18 #include "llvm/CodeGen/SelectionDAG.h"
  19 #include "llvm/CodeGen/TargetSubtargetInfo.h"
  20 #include "llvm/IR/BasicBlock.h"
  21 #include "llvm/Pass.h"
  22 #include <memory>
  23
  24 namespace llvm {
  25   class FastISel;
  26   class SelectionDAGBuilder;
  27   class SDValue;
  28   class MachineRegisterInfo;
  29   class MachineBasicBlock;
  30   class MachineFunction;
  31   class MachineInstr;
  32   class OptimizationRemarkEmitter;
  33   class TargetLowering;
  34   class TargetLibraryInfo;
  35   class FunctionLoweringInfo;
  36   class ScheduleHazardRecognizer;
  37   class GCFunctionInfo;
  38   class ScheduleDAGSDNodes;
  39   class LoadInst;
  40
  41 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
  42 /// pattern-matching instruction selectors.
  43 class SelectionDAGISel : public MachineFunctionPass {
  44 public:
  45   TargetMachine &TM;
  46   const TargetLibraryInfo *LibInfo;
  47   FunctionLoweringInfo *FuncInfo;
  48   MachineFunction *MF;
  49   MachineRegisterInfo *RegInfo;
  50   SelectionDAG *CurDAG;
  51   SelectionDAGBuilder *SDB;
  52   AliasAnalysis *AA;
  53   GCFunctionInfo *GFI;
  54   CodeGenOpt::Level OptLevel;
  55   const TargetInstrInfo *TII;
  56   const TargetLowering *TLI;
  57   bool FastISelFailed;
  58   SmallPtrSet<const Instruction *, 4> ElidedArgCopyInstrs;
  59
  60   /// Current optimization remark emitter.
  61   /// Used to report things like combines and FastISel failures.
  62   std::unique_ptr<OptimizationRemarkEmitter> ORE;
  63
  64   static char ID;
  65
  66   explicit SelectionDAGISel(TargetMachine &tm,
  67                             CodeGenOpt::Level OL = CodeGenOpt::Default);
  68   ~SelectionDAGISel() override;
  69
  70   const TargetLowering *getTargetLowering() const { return TLI; }
  71
  72   void getAnalysisUsage(AnalysisUsage &AU) const override;
  73
  74   bool runOnMachineFunction(MachineFunction &MF) override;
  75
  76   virtual void EmitFunctionEntryCode() {}
  77
  78   /// PreprocessISelDAG - This hook allows targets to hack on the graph before
  79   /// instruction selection starts.
  80   virtual void PreprocessISelDAG() {}
  81
  82   /// PostprocessISelDAG() - This hook allows the target to hack on the graph
  83   /// right after selection.
  84   virtual void PostprocessISelDAG() {}
  85
  86   /// Main hook for targets to transform nodes into machine nodes.
  87   virtual void Select(SDNode *N) = 0;
  88
  89   /// SelectInlineAsmMemoryOperand - Select the specified address as a target
  90   /// addressing mode, according to the specified constraint.  If this does
  91   /// not match or is not implemented, return true.  The resultant operands
  92   /// (which will appear in the machine instruction) should be added to the
  93   /// OutOps vector.
  94   virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
  95                                             unsigned ConstraintID,
  96                                             std::vector<SDValue> &OutOps) {
  97     return true;
  98   }
  99
 100   /// IsProfitableToFold - Returns true if it's profitable to fold the specific
 101   /// operand node N of U during instruction selection that starts at Root.
 102   virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
 103
 104   /// IsLegalToFold - Returns true if the specific operand node N of
 105   /// U can be folded during instruction selection that starts at Root.
 106   /// FIXME: This is a static member function because the MSP430/X86
 107   /// targets, which uses it during isel.  This could become a proper member.
 108   static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
 109                             CodeGenOpt::Level OptLevel,
 110                             bool IgnoreChains = false);
 111
 112   static void InvalidateNodeId(SDNode *N);
 113   static int getUninvalidatedNodeId(SDNode *N);
 114
 115   static void EnforceNodeIdInvariant(SDNode *N);
 116
 117   // Opcodes used by the DAG state machine:
 118   enum BuiltinOpcodes {
 119     OPC_Scope,
 120     OPC_RecordNode,
 121     OPC_RecordChild0, OPC_RecordChild1, OPC_RecordChild2, OPC_RecordChild3,
 122     OPC_RecordChild4, OPC_RecordChild5, OPC_RecordChild6, OPC_RecordChild7,
 123     OPC_RecordMemRef,
 124     OPC_CaptureGlueInput,
 125     OPC_MoveChild,
 126     OPC_MoveChild0, OPC_MoveChild1, OPC_MoveChild2, OPC_MoveChild3,
 127     OPC_MoveChild4, OPC_MoveChild5, OPC_MoveChild6, OPC_MoveChild7,
 128     OPC_MoveParent,
 129     OPC_CheckSame,
 130     OPC_CheckChild0Same, OPC_CheckChild1Same,
 131     OPC_CheckChild2Same, OPC_CheckChild3Same,
 132     OPC_CheckPatternPredicate,
 133     OPC_CheckPredicate,
 134     OPC_CheckPredicateWithOperands,
 135     OPC_CheckOpcode,
 136     OPC_SwitchOpcode,
 137     OPC_CheckType,
 138     OPC_CheckTypeRes,
 139     OPC_SwitchType,
 140     OPC_CheckChild0Type, OPC_CheckChild1Type, OPC_CheckChild2Type,
 141     OPC_CheckChild3Type, OPC_CheckChild4Type, OPC_CheckChild5Type,
 142     OPC_CheckChild6Type, OPC_CheckChild7Type,
 143     OPC_CheckInteger,
 144     OPC_CheckChild0Integer, OPC_CheckChild1Integer, OPC_CheckChild2Integer,
 145     OPC_CheckChild3Integer, OPC_CheckChild4Integer,
 146     OPC_CheckCondCode,
 147     OPC_CheckValueType,
 148     OPC_CheckComplexPat,
 149     OPC_CheckAndImm, OPC_CheckOrImm,
 150     OPC_CheckFoldableChainNode,
 151
 152     OPC_EmitInteger,
 153     OPC_EmitRegister,
 154     OPC_EmitRegister2,
 155     OPC_EmitConvertToTarget,
 156     OPC_EmitMergeInputChains,
 157     OPC_EmitMergeInputChains1_0,
 158     OPC_EmitMergeInputChains1_1,
 159     OPC_EmitMergeInputChains1_2,
 160     OPC_EmitCopyToReg,
 161     OPC_EmitNodeXForm,
 162     OPC_EmitNode,
 163     // Space-optimized forms that implicitly encode number of result VTs.
 164     OPC_EmitNode0, OPC_EmitNode1, OPC_EmitNode2,
 165     OPC_MorphNodeTo,
 166     // Space-optimized forms that implicitly encode number of result VTs.
 167     OPC_MorphNodeTo0, OPC_MorphNodeTo1, OPC_MorphNodeTo2,
 168     OPC_CompleteMatch,
 169     // Contains offset in table for pattern being selected
 170     OPC_Coverage
 171   };
 172
 173   enum {
 174     OPFL_None       = 0,  // Node has no chain or glue input and isn't variadic.
 175     OPFL_Chain      = 1,     // Node has a chain input.
 176     OPFL_GlueInput  = 2,     // Node has a glue input.
 177     OPFL_GlueOutput = 4,     // Node has a glue output.
 178     OPFL_MemRefs    = 8,     // Node gets accumulated MemRefs.
 179     OPFL_Variadic0  = 1<<4,  // Node is variadic, root has 0 fixed inputs.
 180     OPFL_Variadic1  = 2<<4,  // Node is variadic, root has 1 fixed inputs.
 181     OPFL_Variadic2  = 3<<4,  // Node is variadic, root has 2 fixed inputs.
 182     OPFL_Variadic3  = 4<<4,  // Node is variadic, root has 3 fixed inputs.
 183     OPFL_Variadic4  = 5<<4,  // Node is variadic, root has 4 fixed inputs.
 184     OPFL_Variadic5  = 6<<4,  // Node is variadic, root has 5 fixed inputs.
 185     OPFL_Variadic6  = 7<<4,  // Node is variadic, root has 6 fixed inputs.
 186
 187     OPFL_VariadicInfo = OPFL_Variadic6
 188   };
 189
 190   /// getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the
 191   /// number of fixed arity values that should be skipped when copying from the
 192   /// root.
 193   static inline int getNumFixedFromVariadicInfo(unsigned Flags) {
 194     return ((Flags&OPFL_VariadicInfo) >> 4)-1;
 195   }
 196
 197
 198 protected:
 199   /// DAGSize - Size of DAG being instruction selected.
 200   ///
 201   unsigned DAGSize;
 202
 203   /// ReplaceUses - replace all uses of the old node F with the use
 204   /// of the new node T.
 205   void ReplaceUses(SDValue F, SDValue T) {
 206     CurDAG->ReplaceAllUsesOfValueWith(F, T);
 207     EnforceNodeIdInvariant(T.getNode());
 208   }
 209
 210   /// ReplaceUses - replace all uses of the old nodes F with the use
 211   /// of the new nodes T.
 212   void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num) {
 213     CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num);
 214     for (unsigned i = 0; i < Num; ++i)
 215       EnforceNodeIdInvariant(T[i].getNode());
 216   }
 217
 218   /// ReplaceUses - replace all uses of the old node F with the use
 219   /// of the new node T.
 220   void ReplaceUses(SDNode *F, SDNode *T) {
 221     CurDAG->ReplaceAllUsesWith(F, T);
 222     EnforceNodeIdInvariant(T);
 223   }
 224
 225   /// Replace all uses of \c F with \c T, then remove \c F from the DAG.
 226   void ReplaceNode(SDNode *F, SDNode *T) {
 227     CurDAG->ReplaceAllUsesWith(F, T);
 228     EnforceNodeIdInvariant(T);
 229     CurDAG->RemoveDeadNode(F);
 230   }
 231
 232   /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
 233   /// by tblgen.  Others should not call it.
 234   void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops,
 235                                      const SDLoc &DL);
 236
 237   /// getPatternForIndex - Patterns selected by tablegen during ISEL
 238   virtual StringRef getPatternForIndex(unsigned index) {
 239     llvm_unreachable("Tblgen should generate the implementation of this!");
 240   }
 241
 242   /// getIncludePathForIndex - get the td source location of pattern instantiation
 243   virtual StringRef getIncludePathForIndex(unsigned index) {
 244     llvm_unreachable("Tblgen should generate the implementation of this!");
 245   }
 246 public:
 247   // Calls to these predicates are generated by tblgen.
 248   bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
 249                     int64_t DesiredMaskS) const;
 250   bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
 251                     int64_t DesiredMaskS) const;
 252
 253
 254   /// CheckPatternPredicate - This function is generated by tblgen in the
 255   /// target.  It runs the specified pattern predicate and returns true if it
 256   /// succeeds or false if it fails.  The number is a private implementation
 257   /// detail to the code tblgen produces.
 258   virtual bool CheckPatternPredicate(unsigned PredNo) const {
 259     llvm_unreachable("Tblgen should generate the implementation of this!");
 260   }
 261
 262   /// CheckNodePredicate - This function is generated by tblgen in the target.
 263   /// It runs node predicate number PredNo and returns true if it succeeds or
 264   /// false if it fails.  The number is a private implementation
 265   /// detail to the code tblgen produces.
 266   virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const {
 267     llvm_unreachable("Tblgen should generate the implementation of this!");
 268   }
 269
 270   /// CheckNodePredicateWithOperands - This function is generated by tblgen in
 271   /// the target.
 272   /// It runs node predicate number PredNo and returns true if it succeeds or
 273   /// false if it fails.  The number is a private implementation detail to the
 274   /// code tblgen produces.
 275   virtual bool CheckNodePredicateWithOperands(
 276       SDNode *N, unsigned PredNo,
 277       const SmallVectorImpl<SDValue> &Operands) const {
 278     llvm_unreachable("Tblgen should generate the implementation of this!");
 279   }
 280
 281   virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N,
 282                                    unsigned PatternNo,
 283                         SmallVectorImpl<std::pair<SDValue, SDNode*> > &Result) {
 284     llvm_unreachable("Tblgen should generate the implementation of this!");
 285   }
 286
 287   virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) {
 288     llvm_unreachable("Tblgen should generate this!");
 289   }
 290
 291   void SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
 292                         unsigned TableSize);
 293
 294   /// Return true if complex patterns for this target can mutate the
 295   /// DAG.
 296   virtual bool ComplexPatternFuncMutatesDAG() const {
 297     return false;
 298   }
 299
 300   bool isOrEquivalentToAdd(const SDNode *N) const;
 301
 302 private:
 303
 304   // Calls to these functions are generated by tblgen.
 305   void Select_INLINEASM(SDNode *N, bool Branch);
 306   void Select_READ_REGISTER(SDNode *Op);
 307   void Select_WRITE_REGISTER(SDNode *Op);
 308   void Select_UNDEF(SDNode *N);
 309   void CannotYetSelect(SDNode *N);
 310
 311 private:
 312   void DoInstructionSelection();
 313   SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
 314                     ArrayRef<SDValue> Ops, unsigned EmitNodeInfo);
 315
 316   SDNode *MutateStrictFPToFP(SDNode *Node, unsigned NewOpc);
 317
 318   /// Prepares the landing pad to take incoming values or do other EH
 319   /// personality specific tasks. Returns true if the block should be
 320   /// instruction selected, false if no code should be emitted for it.
 321   bool PrepareEHLandingPad();
 322
 323   /// Perform instruction selection on all basic blocks in the function.
 324   void SelectAllBasicBlocks(const Function &Fn);
 325
 326   /// Perform instruction selection on a single basic block, for
 327   /// instructions between \p Begin and \p End.  \p HadTailCall will be set
 328   /// to true if a call in the block was translated as a tail call.
 329   void SelectBasicBlock(BasicBlock::const_iterator Begin,
 330                         BasicBlock::const_iterator End,
 331                         bool &HadTailCall);
 332   void FinishBasicBlock();
 333
 334   void CodeGenAndEmitDAG();
 335
 336   /// Generate instructions for lowering the incoming arguments of the
 337   /// given function.
 338   void LowerArguments(const Function &F);
 339
 340   void ComputeLiveOutVRegInfo();
 341
 342   /// Create the scheduler. If a specific scheduler was specified
 343   /// via the SchedulerRegistry, use it, otherwise select the
 344   /// one preferred by the target.
 345   ///
 346   ScheduleDAGSDNodes *CreateScheduler();
 347
 348   /// OpcodeOffset - This is a cache used to dispatch efficiently into isel
 349   /// state machines that start with a OPC_SwitchOpcode node.
 350   std::vector<unsigned> OpcodeOffset;
 351
 352   void UpdateChains(SDNode *NodeToMatch, SDValue InputChain,
 353                     SmallVectorImpl<SDNode *> &ChainNodesMatched,
 354                     bool isMorphNodeTo);
 355 };
 356
 357 }
 358
 359 #endif /* LLVM_CODEGEN_SELECTIONDAGISEL_H */