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Recommit [NFC] Better encapsulation of llvm::Optional Storage
[llvm-complete.git] / include / llvm / Support / X86DisassemblerDecoderCommon.h
blob83c867169f5229ba1c23e45dff7b433c2e60520c
1 //===-- X86DisassemblerDecoderCommon.h - Disassembler decoder ---*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file is part of the X86 Disassembler.
10 // It contains common definitions used by both the disassembler and the table
11 // generator.
12 // Documentation for the disassembler can be found in X86Disassembler.h.
13 //
14 //===----------------------------------------------------------------------===//
15
16 #ifndef LLVM_LIB_TARGET_X86_DISASSEMBLER_X86DISASSEMBLERDECODERCOMMON_H
17 #define LLVM_LIB_TARGET_X86_DISASSEMBLER_X86DISASSEMBLERDECODERCOMMON_H
18
19 #include "llvm/Support/DataTypes.h"
20
21 namespace llvm {
22 namespace X86Disassembler {
23
24 #define INSTRUCTIONS_SYM x86DisassemblerInstrSpecifiers
25 #define CONTEXTS_SYM x86DisassemblerContexts
26 #define ONEBYTE_SYM x86DisassemblerOneByteOpcodes
27 #define TWOBYTE_SYM x86DisassemblerTwoByteOpcodes
28 #define THREEBYTE38_SYM x86DisassemblerThreeByte38Opcodes
29 #define THREEBYTE3A_SYM x86DisassemblerThreeByte3AOpcodes
30 #define XOP8_MAP_SYM x86DisassemblerXOP8Opcodes
31 #define XOP9_MAP_SYM x86DisassemblerXOP9Opcodes
32 #define XOPA_MAP_SYM x86DisassemblerXOPAOpcodes
33 #define THREEDNOW_MAP_SYM x86Disassembler3DNowOpcodes
34
35 #define INSTRUCTIONS_STR "x86DisassemblerInstrSpecifiers"
36 #define CONTEXTS_STR "x86DisassemblerContexts"
37 #define ONEBYTE_STR "x86DisassemblerOneByteOpcodes"
38 #define TWOBYTE_STR "x86DisassemblerTwoByteOpcodes"
39 #define THREEBYTE38_STR "x86DisassemblerThreeByte38Opcodes"
40 #define THREEBYTE3A_STR "x86DisassemblerThreeByte3AOpcodes"
41 #define XOP8_MAP_STR "x86DisassemblerXOP8Opcodes"
42 #define XOP9_MAP_STR "x86DisassemblerXOP9Opcodes"
43 #define XOPA_MAP_STR "x86DisassemblerXOPAOpcodes"
44 #define THREEDNOW_MAP_STR "x86Disassembler3DNowOpcodes"
45
46 // Attributes of an instruction that must be known before the opcode can be
47 // processed correctly. Most of these indicate the presence of particular
48 // prefixes, but ATTR_64BIT is simply an attribute of the decoding context.
49 #define ATTRIBUTE_BITS \
50 ENUM_ENTRY(ATTR_NONE, 0x00) \
51 ENUM_ENTRY(ATTR_64BIT, (0x1 << 0)) \
52 ENUM_ENTRY(ATTR_XS, (0x1 << 1)) \
53 ENUM_ENTRY(ATTR_XD, (0x1 << 2)) \
54 ENUM_ENTRY(ATTR_REXW, (0x1 << 3)) \
55 ENUM_ENTRY(ATTR_OPSIZE, (0x1 << 4)) \
56 ENUM_ENTRY(ATTR_ADSIZE, (0x1 << 5)) \
57 ENUM_ENTRY(ATTR_VEX, (0x1 << 6)) \
58 ENUM_ENTRY(ATTR_VEXL, (0x1 << 7)) \
59 ENUM_ENTRY(ATTR_EVEX, (0x1 << 8)) \
60 ENUM_ENTRY(ATTR_EVEXL, (0x1 << 9)) \
61 ENUM_ENTRY(ATTR_EVEXL2, (0x1 << 10)) \
62 ENUM_ENTRY(ATTR_EVEXK, (0x1 << 11)) \
63 ENUM_ENTRY(ATTR_EVEXKZ, (0x1 << 12)) \
64 ENUM_ENTRY(ATTR_EVEXB, (0x1 << 13))
65
66 #define ENUM_ENTRY(n, v) n = v,
67 enum attributeBits {
68 ATTRIBUTE_BITS
69 ATTR_max
70 };
71 #undef ENUM_ENTRY
72
73 // Combinations of the above attributes that are relevant to instruction
74 // decode. Although other combinations are possible, they can be reduced to
75 // these without affecting the ultimately decoded instruction.
76
77 // Class name Rank Rationale for rank assignment
78 #define INSTRUCTION_CONTEXTS \
79 ENUM_ENTRY(IC, 0, "says nothing about the instruction") \
80 ENUM_ENTRY(IC_64BIT, 1, "says the instruction applies in " \
81 "64-bit mode but no more") \
82 ENUM_ENTRY(IC_OPSIZE, 3, "requires an OPSIZE prefix, so " \
83 "operands change width") \
84 ENUM_ENTRY(IC_ADSIZE, 3, "requires an ADSIZE prefix, so " \
85 "operands change width") \
86 ENUM_ENTRY(IC_OPSIZE_ADSIZE, 4, "requires ADSIZE and OPSIZE prefixes") \
87 ENUM_ENTRY(IC_XD, 2, "may say something about the opcode " \
88 "but not the operands") \
89 ENUM_ENTRY(IC_XS, 2, "may say something about the opcode " \
90 "but not the operands") \
91 ENUM_ENTRY(IC_XD_OPSIZE, 3, "requires an OPSIZE prefix, so " \
92 "operands change width") \
93 ENUM_ENTRY(IC_XS_OPSIZE, 3, "requires an OPSIZE prefix, so " \
94 "operands change width") \
95 ENUM_ENTRY(IC_XD_ADSIZE, 3, "requires an ADSIZE prefix, so " \
96 "operands change width") \
97 ENUM_ENTRY(IC_XS_ADSIZE, 3, "requires an ADSIZE prefix, so " \
98 "operands change width") \
99 ENUM_ENTRY(IC_64BIT_REXW, 5, "requires a REX.W prefix, so operands "\
100 "change width; overrides IC_OPSIZE") \
101 ENUM_ENTRY(IC_64BIT_REXW_ADSIZE, 6, "requires a REX.W prefix and 0x67 " \
102 "prefix") \
103 ENUM_ENTRY(IC_64BIT_OPSIZE, 3, "Just as meaningful as IC_OPSIZE") \
104 ENUM_ENTRY(IC_64BIT_ADSIZE, 3, "Just as meaningful as IC_ADSIZE") \
105 ENUM_ENTRY(IC_64BIT_OPSIZE_ADSIZE, 4, "Just as meaningful as IC_OPSIZE/" \
106 "IC_ADSIZE") \
107 ENUM_ENTRY(IC_64BIT_XD, 6, "XD instructions are SSE; REX.W is " \
108 "secondary") \
109 ENUM_ENTRY(IC_64BIT_XS, 6, "Just as meaningful as IC_64BIT_XD") \
110 ENUM_ENTRY(IC_64BIT_XD_OPSIZE, 3, "Just as meaningful as IC_XD_OPSIZE") \
111 ENUM_ENTRY(IC_64BIT_XS_OPSIZE, 3, "Just as meaningful as IC_XS_OPSIZE") \
112 ENUM_ENTRY(IC_64BIT_XD_ADSIZE, 3, "Just as meaningful as IC_XD_ADSIZE") \
113 ENUM_ENTRY(IC_64BIT_XS_ADSIZE, 3, "Just as meaningful as IC_XS_ADSIZE") \
114 ENUM_ENTRY(IC_64BIT_REXW_XS, 7, "OPSIZE could mean a different " \
115 "opcode") \
116 ENUM_ENTRY(IC_64BIT_REXW_XD, 7, "Just as meaningful as " \
117 "IC_64BIT_REXW_XS") \
118 ENUM_ENTRY(IC_64BIT_REXW_OPSIZE, 8, "The Dynamic Duo! Prefer over all " \
119 "else because this changes most " \
120 "operands' meaning") \
121 ENUM_ENTRY(IC_VEX, 1, "requires a VEX prefix") \
122 ENUM_ENTRY(IC_VEX_XS, 2, "requires VEX and the XS prefix") \
123 ENUM_ENTRY(IC_VEX_XD, 2, "requires VEX and the XD prefix") \
124 ENUM_ENTRY(IC_VEX_OPSIZE, 2, "requires VEX and the OpSize prefix") \
125 ENUM_ENTRY(IC_VEX_W, 3, "requires VEX and the W prefix") \
126 ENUM_ENTRY(IC_VEX_W_XS, 4, "requires VEX, W, and XS prefix") \
127 ENUM_ENTRY(IC_VEX_W_XD, 4, "requires VEX, W, and XD prefix") \
128 ENUM_ENTRY(IC_VEX_W_OPSIZE, 4, "requires VEX, W, and OpSize") \
129 ENUM_ENTRY(IC_VEX_L, 3, "requires VEX and the L prefix") \
130 ENUM_ENTRY(IC_VEX_L_XS, 4, "requires VEX and the L and XS prefix")\
131 ENUM_ENTRY(IC_VEX_L_XD, 4, "requires VEX and the L and XD prefix")\
132 ENUM_ENTRY(IC_VEX_L_OPSIZE, 4, "requires VEX, L, and OpSize") \
133 ENUM_ENTRY(IC_VEX_L_W, 4, "requires VEX, L and W") \
134 ENUM_ENTRY(IC_VEX_L_W_XS, 5, "requires VEX, L, W and XS prefix") \
135 ENUM_ENTRY(IC_VEX_L_W_XD, 5, "requires VEX, L, W and XD prefix") \
136 ENUM_ENTRY(IC_VEX_L_W_OPSIZE, 5, "requires VEX, L, W and OpSize") \
137 ENUM_ENTRY(IC_EVEX, 1, "requires an EVEX prefix") \
138 ENUM_ENTRY(IC_EVEX_XS, 2, "requires EVEX and the XS prefix") \
139 ENUM_ENTRY(IC_EVEX_XD, 2, "requires EVEX and the XD prefix") \
140 ENUM_ENTRY(IC_EVEX_OPSIZE, 2, "requires EVEX and the OpSize prefix") \
141 ENUM_ENTRY(IC_EVEX_W, 3, "requires EVEX and the W prefix") \
142 ENUM_ENTRY(IC_EVEX_W_XS, 4, "requires EVEX, W, and XS prefix") \
143 ENUM_ENTRY(IC_EVEX_W_XD, 4, "requires EVEX, W, and XD prefix") \
144 ENUM_ENTRY(IC_EVEX_W_OPSIZE, 4, "requires EVEX, W, and OpSize") \
145 ENUM_ENTRY(IC_EVEX_L, 3, "requires EVEX and the L prefix") \
146 ENUM_ENTRY(IC_EVEX_L_XS, 4, "requires EVEX and the L and XS prefix")\
147 ENUM_ENTRY(IC_EVEX_L_XD, 4, "requires EVEX and the L and XD prefix")\
148 ENUM_ENTRY(IC_EVEX_L_OPSIZE, 4, "requires EVEX, L, and OpSize") \
149 ENUM_ENTRY(IC_EVEX_L_W, 3, "requires EVEX, L and W") \
150 ENUM_ENTRY(IC_EVEX_L_W_XS, 4, "requires EVEX, L, W and XS prefix") \
151 ENUM_ENTRY(IC_EVEX_L_W_XD, 4, "requires EVEX, L, W and XD prefix") \
152 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE, 4, "requires EVEX, L, W and OpSize") \
153 ENUM_ENTRY(IC_EVEX_L2, 3, "requires EVEX and the L2 prefix") \
154 ENUM_ENTRY(IC_EVEX_L2_XS, 4, "requires EVEX and the L2 and XS prefix")\
155 ENUM_ENTRY(IC_EVEX_L2_XD, 4, "requires EVEX and the L2 and XD prefix")\
156 ENUM_ENTRY(IC_EVEX_L2_OPSIZE, 4, "requires EVEX, L2, and OpSize") \
157 ENUM_ENTRY(IC_EVEX_L2_W, 3, "requires EVEX, L2 and W") \
158 ENUM_ENTRY(IC_EVEX_L2_W_XS, 4, "requires EVEX, L2, W and XS prefix") \
159 ENUM_ENTRY(IC_EVEX_L2_W_XD, 4, "requires EVEX, L2, W and XD prefix") \
160 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE, 4, "requires EVEX, L2, W and OpSize") \
161 ENUM_ENTRY(IC_EVEX_K, 1, "requires an EVEX_K prefix") \
162 ENUM_ENTRY(IC_EVEX_XS_K, 2, "requires EVEX_K and the XS prefix") \
163 ENUM_ENTRY(IC_EVEX_XD_K, 2, "requires EVEX_K and the XD prefix") \
164 ENUM_ENTRY(IC_EVEX_OPSIZE_K, 2, "requires EVEX_K and the OpSize prefix") \
165 ENUM_ENTRY(IC_EVEX_W_K, 3, "requires EVEX_K and the W prefix") \
166 ENUM_ENTRY(IC_EVEX_W_XS_K, 4, "requires EVEX_K, W, and XS prefix") \
167 ENUM_ENTRY(IC_EVEX_W_XD_K, 4, "requires EVEX_K, W, and XD prefix") \
168 ENUM_ENTRY(IC_EVEX_W_OPSIZE_K, 4, "requires EVEX_K, W, and OpSize") \
169 ENUM_ENTRY(IC_EVEX_L_K, 3, "requires EVEX_K and the L prefix") \
170 ENUM_ENTRY(IC_EVEX_L_XS_K, 4, "requires EVEX_K and the L and XS prefix")\
171 ENUM_ENTRY(IC_EVEX_L_XD_K, 4, "requires EVEX_K and the L and XD prefix")\
172 ENUM_ENTRY(IC_EVEX_L_OPSIZE_K, 4, "requires EVEX_K, L, and OpSize") \
173 ENUM_ENTRY(IC_EVEX_L_W_K, 3, "requires EVEX_K, L and W") \
174 ENUM_ENTRY(IC_EVEX_L_W_XS_K, 4, "requires EVEX_K, L, W and XS prefix") \
175 ENUM_ENTRY(IC_EVEX_L_W_XD_K, 4, "requires EVEX_K, L, W and XD prefix") \
176 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_K, 4, "requires EVEX_K, L, W and OpSize") \
177 ENUM_ENTRY(IC_EVEX_L2_K, 3, "requires EVEX_K and the L2 prefix") \
178 ENUM_ENTRY(IC_EVEX_L2_XS_K, 4, "requires EVEX_K and the L2 and XS prefix")\
179 ENUM_ENTRY(IC_EVEX_L2_XD_K, 4, "requires EVEX_K and the L2 and XD prefix")\
180 ENUM_ENTRY(IC_EVEX_L2_OPSIZE_K, 4, "requires EVEX_K, L2, and OpSize") \
181 ENUM_ENTRY(IC_EVEX_L2_W_K, 3, "requires EVEX_K, L2 and W") \
182 ENUM_ENTRY(IC_EVEX_L2_W_XS_K, 4, "requires EVEX_K, L2, W and XS prefix") \
183 ENUM_ENTRY(IC_EVEX_L2_W_XD_K, 4, "requires EVEX_K, L2, W and XD prefix") \
184 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_K, 4, "requires EVEX_K, L2, W and OpSize") \
185 ENUM_ENTRY(IC_EVEX_B, 1, "requires an EVEX_B prefix") \
186 ENUM_ENTRY(IC_EVEX_XS_B, 2, "requires EVEX_B and the XS prefix") \
187 ENUM_ENTRY(IC_EVEX_XD_B, 2, "requires EVEX_B and the XD prefix") \
188 ENUM_ENTRY(IC_EVEX_OPSIZE_B, 2, "requires EVEX_B and the OpSize prefix") \
189 ENUM_ENTRY(IC_EVEX_W_B, 3, "requires EVEX_B and the W prefix") \
190 ENUM_ENTRY(IC_EVEX_W_XS_B, 4, "requires EVEX_B, W, and XS prefix") \
191 ENUM_ENTRY(IC_EVEX_W_XD_B, 4, "requires EVEX_B, W, and XD prefix") \
192 ENUM_ENTRY(IC_EVEX_W_OPSIZE_B, 4, "requires EVEX_B, W, and OpSize") \
193 ENUM_ENTRY(IC_EVEX_L_B, 3, "requires EVEX_B and the L prefix") \
194 ENUM_ENTRY(IC_EVEX_L_XS_B, 4, "requires EVEX_B and the L and XS prefix")\
195 ENUM_ENTRY(IC_EVEX_L_XD_B, 4, "requires EVEX_B and the L and XD prefix")\
196 ENUM_ENTRY(IC_EVEX_L_OPSIZE_B, 4, "requires EVEX_B, L, and OpSize") \
197 ENUM_ENTRY(IC_EVEX_L_W_B, 3, "requires EVEX_B, L and W") \
198 ENUM_ENTRY(IC_EVEX_L_W_XS_B, 4, "requires EVEX_B, L, W and XS prefix") \
199 ENUM_ENTRY(IC_EVEX_L_W_XD_B, 4, "requires EVEX_B, L, W and XD prefix") \
200 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_B, 4, "requires EVEX_B, L, W and OpSize") \
201 ENUM_ENTRY(IC_EVEX_L2_B, 3, "requires EVEX_B and the L2 prefix") \
202 ENUM_ENTRY(IC_EVEX_L2_XS_B, 4, "requires EVEX_B and the L2 and XS prefix")\
203 ENUM_ENTRY(IC_EVEX_L2_XD_B, 4, "requires EVEX_B and the L2 and XD prefix")\
204 ENUM_ENTRY(IC_EVEX_L2_OPSIZE_B, 4, "requires EVEX_B, L2, and OpSize") \
205 ENUM_ENTRY(IC_EVEX_L2_W_B, 3, "requires EVEX_B, L2 and W") \
206 ENUM_ENTRY(IC_EVEX_L2_W_XS_B, 4, "requires EVEX_B, L2, W and XS prefix") \
207 ENUM_ENTRY(IC_EVEX_L2_W_XD_B, 4, "requires EVEX_B, L2, W and XD prefix") \
208 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_B, 4, "requires EVEX_B, L2, W and OpSize") \
209 ENUM_ENTRY(IC_EVEX_K_B, 1, "requires EVEX_B and EVEX_K prefix") \
210 ENUM_ENTRY(IC_EVEX_XS_K_B, 2, "requires EVEX_B, EVEX_K and the XS prefix") \
211 ENUM_ENTRY(IC_EVEX_XD_K_B, 2, "requires EVEX_B, EVEX_K and the XD prefix") \
212 ENUM_ENTRY(IC_EVEX_OPSIZE_K_B, 2, "requires EVEX_B, EVEX_K and the OpSize prefix") \
213 ENUM_ENTRY(IC_EVEX_W_K_B, 3, "requires EVEX_B, EVEX_K and the W prefix") \
214 ENUM_ENTRY(IC_EVEX_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, W, and XS prefix") \
215 ENUM_ENTRY(IC_EVEX_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, W, and XD prefix") \
216 ENUM_ENTRY(IC_EVEX_W_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, W, and OpSize") \
217 ENUM_ENTRY(IC_EVEX_L_K_B, 3, "requires EVEX_B, EVEX_K and the L prefix") \
218 ENUM_ENTRY(IC_EVEX_L_XS_K_B, 4, "requires EVEX_B, EVEX_K and the L and XS prefix")\
219 ENUM_ENTRY(IC_EVEX_L_XD_K_B, 4, "requires EVEX_B, EVEX_K and the L and XD prefix")\
220 ENUM_ENTRY(IC_EVEX_L_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, L, and OpSize") \
221 ENUM_ENTRY(IC_EVEX_L_W_K_B, 3, "requires EVEX_B, EVEX_K, L and W") \
222 ENUM_ENTRY(IC_EVEX_L_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, L, W and XS prefix") \
223 ENUM_ENTRY(IC_EVEX_L_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, L, W and XD prefix") \
224 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_K_B,4, "requires EVEX_B, EVEX_K, L, W and OpSize") \
225 ENUM_ENTRY(IC_EVEX_L2_K_B, 3, "requires EVEX_B, EVEX_K and the L2 prefix") \
226 ENUM_ENTRY(IC_EVEX_L2_XS_K_B, 4, "requires EVEX_B, EVEX_K and the L2 and XS prefix")\
227 ENUM_ENTRY(IC_EVEX_L2_XD_K_B, 4, "requires EVEX_B, EVEX_K and the L2 and XD prefix")\
228 ENUM_ENTRY(IC_EVEX_L2_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, L2, and OpSize") \
229 ENUM_ENTRY(IC_EVEX_L2_W_K_B, 3, "requires EVEX_B, EVEX_K, L2 and W") \
230 ENUM_ENTRY(IC_EVEX_L2_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, L2, W and XS prefix") \
231 ENUM_ENTRY(IC_EVEX_L2_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, L2, W and XD prefix") \
232 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_K_B,4, "requires EVEX_B, EVEX_K, L2, W and OpSize") \
233 ENUM_ENTRY(IC_EVEX_KZ_B, 1, "requires EVEX_B and EVEX_KZ prefix") \
234 ENUM_ENTRY(IC_EVEX_XS_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the XS prefix") \
235 ENUM_ENTRY(IC_EVEX_XD_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the XD prefix") \
236 ENUM_ENTRY(IC_EVEX_OPSIZE_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the OpSize prefix") \
237 ENUM_ENTRY(IC_EVEX_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the W prefix") \
238 ENUM_ENTRY(IC_EVEX_W_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and XS prefix") \
239 ENUM_ENTRY(IC_EVEX_W_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and XD prefix") \
240 ENUM_ENTRY(IC_EVEX_W_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and OpSize") \
241 ENUM_ENTRY(IC_EVEX_L_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the L prefix") \
242 ENUM_ENTRY(IC_EVEX_L_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L and XS prefix")\
243 ENUM_ENTRY(IC_EVEX_L_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L and XD prefix")\
244 ENUM_ENTRY(IC_EVEX_L_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, and OpSize") \
245 ENUM_ENTRY(IC_EVEX_L_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ, L and W") \
246 ENUM_ENTRY(IC_EVEX_L_W_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, W and XS prefix") \
247 ENUM_ENTRY(IC_EVEX_L_W_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, W and XD prefix") \
248 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, W and OpSize") \
249 ENUM_ENTRY(IC_EVEX_L2_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the L2 prefix") \
250 ENUM_ENTRY(IC_EVEX_L2_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L2 and XS prefix")\
251 ENUM_ENTRY(IC_EVEX_L2_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L2 and XD prefix")\
252 ENUM_ENTRY(IC_EVEX_L2_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, and OpSize") \
253 ENUM_ENTRY(IC_EVEX_L2_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ, L2 and W") \
254 ENUM_ENTRY(IC_EVEX_L2_W_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, W and XS prefix") \
255 ENUM_ENTRY(IC_EVEX_L2_W_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, W and XD prefix") \
256 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, W and OpSize") \
257 ENUM_ENTRY(IC_EVEX_KZ, 1, "requires an EVEX_KZ prefix") \
258 ENUM_ENTRY(IC_EVEX_XS_KZ, 2, "requires EVEX_KZ and the XS prefix") \
259 ENUM_ENTRY(IC_EVEX_XD_KZ, 2, "requires EVEX_KZ and the XD prefix") \
260 ENUM_ENTRY(IC_EVEX_OPSIZE_KZ, 2, "requires EVEX_KZ and the OpSize prefix") \
261 ENUM_ENTRY(IC_EVEX_W_KZ, 3, "requires EVEX_KZ and the W prefix") \
262 ENUM_ENTRY(IC_EVEX_W_XS_KZ, 4, "requires EVEX_KZ, W, and XS prefix") \
263 ENUM_ENTRY(IC_EVEX_W_XD_KZ, 4, "requires EVEX_KZ, W, and XD prefix") \
264 ENUM_ENTRY(IC_EVEX_W_OPSIZE_KZ, 4, "requires EVEX_KZ, W, and OpSize") \
265 ENUM_ENTRY(IC_EVEX_L_KZ, 3, "requires EVEX_KZ and the L prefix") \
266 ENUM_ENTRY(IC_EVEX_L_XS_KZ, 4, "requires EVEX_KZ and the L and XS prefix")\
267 ENUM_ENTRY(IC_EVEX_L_XD_KZ, 4, "requires EVEX_KZ and the L and XD prefix")\
268 ENUM_ENTRY(IC_EVEX_L_OPSIZE_KZ, 4, "requires EVEX_KZ, L, and OpSize") \
269 ENUM_ENTRY(IC_EVEX_L_W_KZ, 3, "requires EVEX_KZ, L and W") \
270 ENUM_ENTRY(IC_EVEX_L_W_XS_KZ, 4, "requires EVEX_KZ, L, W and XS prefix") \
271 ENUM_ENTRY(IC_EVEX_L_W_XD_KZ, 4, "requires EVEX_KZ, L, W and XD prefix") \
272 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_KZ, 4, "requires EVEX_KZ, L, W and OpSize") \
273 ENUM_ENTRY(IC_EVEX_L2_KZ, 3, "requires EVEX_KZ and the L2 prefix") \
274 ENUM_ENTRY(IC_EVEX_L2_XS_KZ, 4, "requires EVEX_KZ and the L2 and XS prefix")\
275 ENUM_ENTRY(IC_EVEX_L2_XD_KZ, 4, "requires EVEX_KZ and the L2 and XD prefix")\
276 ENUM_ENTRY(IC_EVEX_L2_OPSIZE_KZ, 4, "requires EVEX_KZ, L2, and OpSize") \
277 ENUM_ENTRY(IC_EVEX_L2_W_KZ, 3, "requires EVEX_KZ, L2 and W") \
278 ENUM_ENTRY(IC_EVEX_L2_W_XS_KZ, 4, "requires EVEX_KZ, L2, W and XS prefix") \
279 ENUM_ENTRY(IC_EVEX_L2_W_XD_KZ, 4, "requires EVEX_KZ, L2, W and XD prefix") \
280 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_KZ, 4, "requires EVEX_KZ, L2, W and OpSize")
281
282 #define ENUM_ENTRY(n, r, d) n,
283 enum InstructionContext {
284 INSTRUCTION_CONTEXTS
285 IC_max
286 };
287 #undef ENUM_ENTRY
288
289 // Opcode types, which determine which decode table to use, both in the Intel
290 // manual and also for the decoder.
291 enum OpcodeType {
292 ONEBYTE = 0,
293 TWOBYTE = 1,
294 THREEBYTE_38 = 2,
295 THREEBYTE_3A = 3,
296 XOP8_MAP = 4,
297 XOP9_MAP = 5,
298 XOPA_MAP = 6,
299 THREEDNOW_MAP = 7
300 };
301
302 // The following structs are used for the hierarchical decode table. After
303 // determining the instruction's class (i.e., which IC_* constant applies to
304 // it), the decoder reads the opcode. Some instructions require specific
305 // values of the ModR/M byte, so the ModR/M byte indexes into the final table.
306 //
307 // If a ModR/M byte is not required, "required" is left unset, and the values
308 // for each instructionID are identical.
309 typedef uint16_t InstrUID;
310
311 // ModRMDecisionType - describes the type of ModR/M decision, allowing the
312 // consumer to determine the number of entries in it.
313 //
314 // MODRM_ONEENTRY - No matter what the value of the ModR/M byte is, the decoded
315 // instruction is the same.
316 // MODRM_SPLITRM - If the ModR/M byte is between 0x00 and 0xbf, the opcode
317 // corresponds to one instruction; otherwise, it corresponds to
318 // a different instruction.
319 // MODRM_SPLITMISC- If the ModR/M byte is between 0x00 and 0xbf, ModR/M byte
320 // divided by 8 is used to select instruction; otherwise, each
321 // value of the ModR/M byte could correspond to a different
322 // instruction.
323 // MODRM_SPLITREG - ModR/M byte divided by 8 is used to select instruction. This
324 // corresponds to instructions that use reg field as opcode
325 // MODRM_FULL - Potentially, each value of the ModR/M byte could correspond
326 // to a different instruction.
327 #define MODRMTYPES \
328 ENUM_ENTRY(MODRM_ONEENTRY) \
329 ENUM_ENTRY(MODRM_SPLITRM) \
330 ENUM_ENTRY(MODRM_SPLITMISC) \
331 ENUM_ENTRY(MODRM_SPLITREG) \
332 ENUM_ENTRY(MODRM_FULL)
333
334 #define ENUM_ENTRY(n) n,
335 enum ModRMDecisionType {
336 MODRMTYPES
337 MODRM_max
338 };
339 #undef ENUM_ENTRY
340
341 #define CASE_ENCODING_RM \
342 case ENCODING_RM: \
343 case ENCODING_RM_CD2: \
344 case ENCODING_RM_CD4: \
345 case ENCODING_RM_CD8: \
346 case ENCODING_RM_CD16: \
347 case ENCODING_RM_CD32: \
348 case ENCODING_RM_CD64
349
350 #define CASE_ENCODING_VSIB \
351 case ENCODING_VSIB: \
352 case ENCODING_VSIB_CD2: \
353 case ENCODING_VSIB_CD4: \
354 case ENCODING_VSIB_CD8: \
355 case ENCODING_VSIB_CD16: \
356 case ENCODING_VSIB_CD32: \
357 case ENCODING_VSIB_CD64
358
359 // Physical encodings of instruction operands.
360 #define ENCODINGS \
361 ENUM_ENTRY(ENCODING_NONE, "") \
362 ENUM_ENTRY(ENCODING_REG, "Register operand in ModR/M byte.") \
363 ENUM_ENTRY(ENCODING_RM, "R/M operand in ModR/M byte.") \
364 ENUM_ENTRY(ENCODING_RM_CD2, "R/M operand with CDisp scaling of 2") \
365 ENUM_ENTRY(ENCODING_RM_CD4, "R/M operand with CDisp scaling of 4") \
366 ENUM_ENTRY(ENCODING_RM_CD8, "R/M operand with CDisp scaling of 8") \
367 ENUM_ENTRY(ENCODING_RM_CD16,"R/M operand with CDisp scaling of 16") \
368 ENUM_ENTRY(ENCODING_RM_CD32,"R/M operand with CDisp scaling of 32") \
369 ENUM_ENTRY(ENCODING_RM_CD64,"R/M operand with CDisp scaling of 64") \
370 ENUM_ENTRY(ENCODING_VSIB, "VSIB operand in ModR/M byte.") \
371 ENUM_ENTRY(ENCODING_VSIB_CD2, "VSIB operand with CDisp scaling of 2") \
372 ENUM_ENTRY(ENCODING_VSIB_CD4, "VSIB operand with CDisp scaling of 4") \
373 ENUM_ENTRY(ENCODING_VSIB_CD8, "VSIB operand with CDisp scaling of 8") \
374 ENUM_ENTRY(ENCODING_VSIB_CD16,"VSIB operand with CDisp scaling of 16") \
375 ENUM_ENTRY(ENCODING_VSIB_CD32,"VSIB operand with CDisp scaling of 32") \
376 ENUM_ENTRY(ENCODING_VSIB_CD64,"VSIB operand with CDisp scaling of 64") \
377 ENUM_ENTRY(ENCODING_VVVV, "Register operand in VEX.vvvv byte.") \
378 ENUM_ENTRY(ENCODING_WRITEMASK, "Register operand in EVEX.aaa byte.") \
379 ENUM_ENTRY(ENCODING_IB, "1-byte immediate") \
380 ENUM_ENTRY(ENCODING_IW, "2-byte") \
381 ENUM_ENTRY(ENCODING_ID, "4-byte") \
382 ENUM_ENTRY(ENCODING_IO, "8-byte") \
383 ENUM_ENTRY(ENCODING_RB, "(AL..DIL, R8L..R15L) Register code added to " \
384 "the opcode byte") \
385 ENUM_ENTRY(ENCODING_RW, "(AX..DI, R8W..R15W)") \
386 ENUM_ENTRY(ENCODING_RD, "(EAX..EDI, R8D..R15D)") \
387 ENUM_ENTRY(ENCODING_RO, "(RAX..RDI, R8..R15)") \
388 ENUM_ENTRY(ENCODING_FP, "Position on floating-point stack in ModR/M " \
389 "byte.") \
390 \
391 ENUM_ENTRY(ENCODING_Iv, "Immediate of operand size") \
392 ENUM_ENTRY(ENCODING_Ia, "Immediate of address size") \
393 ENUM_ENTRY(ENCODING_IRC, "Immediate for static rounding control") \
394 ENUM_ENTRY(ENCODING_Rv, "Register code of operand size added to the " \
395 "opcode byte") \
396 ENUM_ENTRY(ENCODING_DUP, "Duplicate of another operand; ID is encoded " \
397 "in type") \
398 ENUM_ENTRY(ENCODING_SI, "Source index; encoded in OpSize/Adsize prefix") \
399 ENUM_ENTRY(ENCODING_DI, "Destination index; encoded in prefixes")
400
401 #define ENUM_ENTRY(n, d) n,
402 enum OperandEncoding {
403 ENCODINGS
404 ENCODING_max
405 };
406 #undef ENUM_ENTRY
407
408 // Semantic interpretations of instruction operands.
409 #define TYPES \
410 ENUM_ENTRY(TYPE_NONE, "") \
411 ENUM_ENTRY(TYPE_REL, "immediate address") \
412 ENUM_ENTRY(TYPE_R8, "1-byte register operand") \
413 ENUM_ENTRY(TYPE_R16, "2-byte") \
414 ENUM_ENTRY(TYPE_R32, "4-byte") \
415 ENUM_ENTRY(TYPE_R64, "8-byte") \
416 ENUM_ENTRY(TYPE_IMM, "immediate operand") \
417 ENUM_ENTRY(TYPE_IMM3, "1-byte immediate operand between 0 and 7") \
418 ENUM_ENTRY(TYPE_IMM5, "1-byte immediate operand between 0 and 31") \
419 ENUM_ENTRY(TYPE_AVX512ICC, "1-byte immediate operand for AVX512 icmp") \
420 ENUM_ENTRY(TYPE_UIMM8, "1-byte unsigned immediate operand") \
421 ENUM_ENTRY(TYPE_M, "Memory operand") \
422 ENUM_ENTRY(TYPE_MVSIBX, "Memory operand using XMM index") \
423 ENUM_ENTRY(TYPE_MVSIBY, "Memory operand using YMM index") \
424 ENUM_ENTRY(TYPE_MVSIBZ, "Memory operand using ZMM index") \
425 ENUM_ENTRY(TYPE_SRCIDX, "memory at source index") \
426 ENUM_ENTRY(TYPE_DSTIDX, "memory at destination index") \
427 ENUM_ENTRY(TYPE_MOFFS, "memory offset (relative to segment base)") \
428 ENUM_ENTRY(TYPE_ST, "Position on the floating-point stack") \
429 ENUM_ENTRY(TYPE_MM64, "8-byte MMX register") \
430 ENUM_ENTRY(TYPE_XMM, "16-byte") \
431 ENUM_ENTRY(TYPE_YMM, "32-byte") \
432 ENUM_ENTRY(TYPE_ZMM, "64-byte") \
433 ENUM_ENTRY(TYPE_VK, "mask register") \
434 ENUM_ENTRY(TYPE_SEGMENTREG, "Segment register operand") \
435 ENUM_ENTRY(TYPE_DEBUGREG, "Debug register operand") \
436 ENUM_ENTRY(TYPE_CONTROLREG, "Control register operand") \
437 ENUM_ENTRY(TYPE_BNDR, "MPX bounds register") \
438 \
439 ENUM_ENTRY(TYPE_Rv, "Register operand of operand size") \
440 ENUM_ENTRY(TYPE_RELv, "Immediate address of operand size") \
441 ENUM_ENTRY(TYPE_DUP0, "Duplicate of operand 0") \
442 ENUM_ENTRY(TYPE_DUP1, "operand 1") \
443 ENUM_ENTRY(TYPE_DUP2, "operand 2") \
444 ENUM_ENTRY(TYPE_DUP3, "operand 3") \
445 ENUM_ENTRY(TYPE_DUP4, "operand 4") \
446
447 #define ENUM_ENTRY(n, d) n,
448 enum OperandType {
449 TYPES
450 TYPE_max
451 };
452 #undef ENUM_ENTRY
453
454 /// The specification for how to extract and interpret one operand.
455 struct OperandSpecifier {
456 uint8_t encoding;
457 uint8_t type;
458 };
459
460 static const unsigned X86_MAX_OPERANDS = 6;
461
462 /// Decoding mode for the Intel disassembler. 16-bit, 32-bit, and 64-bit mode
463 /// are supported, and represent real mode, IA-32e, and IA-32e in 64-bit mode,
464 /// respectively.
465 enum DisassemblerMode {
466 MODE_16BIT,
467 MODE_32BIT,
468 MODE_64BIT
469 };
470
471 } // namespace X86Disassembler
472 } // namespace llvm
473
474 #endif
The low level virtual machine