lib/CodeGen/LiveStacks.cpp

   1 //===-- LiveStacks.cpp - Live Stack Slot Analysis -------------------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file implements the live stack slot analysis pass. It is analogous to
  10 // live interval analysis except it's analyzing liveness of stack slots rather
  11 // than registers.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "llvm/CodeGen/LiveStacks.h"
  16 #include "llvm/CodeGen/LiveIntervals.h"
  17 #include "llvm/CodeGen/Passes.h"
  18 #include "llvm/CodeGen/TargetRegisterInfo.h"
  19 #include "llvm/CodeGen/TargetSubtargetInfo.h"
  20 #include "llvm/Support/Debug.h"
  21 #include "llvm/Support/raw_ostream.h"
  22 using namespace llvm;
  23
  24 #define DEBUG_TYPE "livestacks"
  25
  26 char LiveStacks::ID = 0;
  27 INITIALIZE_PASS_BEGIN(LiveStacks, DEBUG_TYPE,
  28                 "Live Stack Slot Analysis", false, false)
  29 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
  30 INITIALIZE_PASS_END(LiveStacks, DEBUG_TYPE,
  31                 "Live Stack Slot Analysis", false, false)
  32
  33 char &llvm::LiveStacksID = LiveStacks::ID;
  34
  35 void LiveStacks::getAnalysisUsage(AnalysisUsage &AU) const {
  36   AU.setPreservesAll();
  37   AU.addPreserved<SlotIndexes>();
  38   AU.addRequiredTransitive<SlotIndexes>();
  39   MachineFunctionPass::getAnalysisUsage(AU);
  40 }
  41
  42 void LiveStacks::releaseMemory() {
  43   // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
  44   VNInfoAllocator.Reset();
  45   S2IMap.clear();
  46   S2RCMap.clear();
  47 }
  48
  49 bool LiveStacks::runOnMachineFunction(MachineFunction &MF) {
  50   TRI = MF.getSubtarget().getRegisterInfo();
  51   // FIXME: No analysis is being done right now. We are relying on the
  52   // register allocators to provide the information.
  53   return false;
  54 }
  55
  56 LiveInterval &
  57 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) {
  58   assert(Slot >= 0 && "Spill slot indice must be >= 0");
  59   SS2IntervalMap::iterator I = S2IMap.find(Slot);
  60   if (I == S2IMap.end()) {
  61     I = S2IMap
  62             .emplace(
  63                 std::piecewise_construct, std::forward_as_tuple(Slot),
  64                 std::forward_as_tuple(Register::index2StackSlot(Slot), 0.0F))
  65             .first;
  66     S2RCMap.insert(std::make_pair(Slot, RC));
  67   } else {
  68     // Use the largest common subclass register class.
  69     const TargetRegisterClass *OldRC = S2RCMap[Slot];
  70     S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC);
  71   }
  72   return I->second;
  73 }
  74
  75 /// print - Implement the dump method.
  76 void LiveStacks::print(raw_ostream &OS, const Module*) const {
  77
  78   OS << "********** INTERVALS **********\n";
  79   for (const_iterator I = begin(), E = end(); I != E; ++I) {
  80     I->second.print(OS);
  81     int Slot = I->first;
  82     const TargetRegisterClass *RC = getIntervalRegClass(Slot);
  83     if (RC)
  84       OS << " [" << TRI->getRegClassName(RC) << "]\n";
  85     else
  86       OS << " [Unknown]\n";
  87   }
  88 }