| commit | a78322bd37064642d88645ef1d8d6e57336f8e52 | |
| author | Petar Avramovic <Petar.Avramovic@rt-rk.com> | |
| Tue, 22 Oct 2019 14:25:37 +0000 (22 14:25 +0000) | ||
| committer | Petar Avramovic <Petar.Avramovic@rt-rk.com> | |
| Tue, 22 Oct 2019 14:25:37 +0000 (22 14:25 +0000) | ||
| tree | 21969fd96012bfba3cfbd70379a9f615d38185ca | treesnapshot (tar.gz zip) |
| parent | ceef272d87d584993012ef8e7f321664f3a7aecb | commitdiff |
[MIParser] Set RegClassOrRegBank during instruction parsing
MachineRegisterInfo::createGenericVirtualRegister sets
RegClassOrRegBank to static_cast<RegisterBank *>(nullptr).
MIParser on the other hand doesn't. When we attempt to constrain
Register Class on such VReg, additional COPY is generated.
This way we avoid COPY instructions showing in test that have MIR
input while they are not present with llvm-ir input that was used
to create given MIR for a -run-pass test.
Differential Revision: https://reviews.llvm.org/D68946
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375502 91177308-0d34-0410-b5e6-96231b3b80d8
MachineRegisterInfo::createGenericVirtualRegister sets
RegClassOrRegBank to static_cast<RegisterBank *>(nullptr).
MIParser on the other hand doesn't. When we attempt to constrain
Register Class on such VReg, additional COPY is generated.
This way we avoid COPY instructions showing in test that have MIR
input while they are not present with llvm-ir input that was used
to create given MIR for a -run-pass test.
Differential Revision: https://reviews.llvm.org/D68946
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375502 91177308-0d34-0410-b5e6-96231b3b80d8