lib/CodeGen/RegisterClassInfo.cpp

   1 //===- RegisterClassInfo.cpp - Dynamic Register Class Info ----------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file implements the RegisterClassInfo class which provides dynamic
  10 // information about target register classes. Callee-saved vs. caller-saved and
  11 // reserved registers depend on calling conventions and other dynamic
  12 // information, so some things cannot be determined statically.
  13 //
  14 //===----------------------------------------------------------------------===//
  15
  16 #include "llvm/CodeGen/RegisterClassInfo.h"
  17 #include "llvm/ADT/ArrayRef.h"
  18 #include "llvm/ADT/BitVector.h"
  19 #include "llvm/ADT/SmallVector.h"
  20 #include "llvm/CodeGen/MachineFunction.h"
  21 #include "llvm/CodeGen/MachineRegisterInfo.h"
  22 #include "llvm/CodeGen/TargetFrameLowering.h"
  23 #include "llvm/CodeGen/TargetRegisterInfo.h"
  24 #include "llvm/CodeGen/TargetSubtargetInfo.h"
  25 #include "llvm/MC/MCRegisterInfo.h"
  26 #include "llvm/Support/CommandLine.h"
  27 #include "llvm/Support/Debug.h"
  28 #include "llvm/Support/raw_ostream.h"
  29 #include <algorithm>
  30 #include <cassert>
  31 #include <cstdint>
  32
  33 using namespace llvm;
  34
  35 #define DEBUG_TYPE "regalloc"
  36
  37 static cl::opt<unsigned>
  38 StressRA("stress-regalloc", cl::Hidden, cl::init(0), cl::value_desc("N"),
  39          cl::desc("Limit all regclasses to N registers"));
  40
  41 RegisterClassInfo::RegisterClassInfo() = default;
  42
  43 void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) {
  44   bool Update = false;
  45   MF = &mf;
  46
  47   // Allocate new array the first time we see a new target.
  48   if (MF->getSubtarget().getRegisterInfo() != TRI) {
  49     TRI = MF->getSubtarget().getRegisterInfo();
  50     RegClass.reset(new RCInfo[TRI->getNumRegClasses()]);
  51     Update = true;
  52   }
  53
  54   // Does this MF have different CSRs?
  55   assert(TRI && "no register info set");
  56
  57   // Get the callee saved registers.
  58   const MCPhysReg *CSR = MF->getRegInfo().getCalleeSavedRegs();
  59   if (Update || CSR != CalleeSavedRegs) {
  60     // Build a CSRAlias map. Every CSR alias saves the last
  61     // overlapping CSR.
  62     CalleeSavedAliases.resize(TRI->getNumRegs(), 0);
  63     for (const MCPhysReg *I = CSR; *I; ++I)
  64       for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI)
  65         CalleeSavedAliases[*AI] = *I;
  66
  67     Update = true;
  68   }
  69   CalleeSavedRegs = CSR;
  70
  71   // Different reserved registers?
  72   const BitVector &RR = MF->getRegInfo().getReservedRegs();
  73   if (Reserved.size() != RR.size() || RR != Reserved) {
  74     Update = true;
  75     Reserved = RR;
  76   }
  77
  78   // Invalidate cached information from previous function.
  79   if (Update) {
  80     unsigned NumPSets = TRI->getNumRegPressureSets();
  81     PSetLimits.reset(new unsigned[NumPSets]);
  82     std::fill(&PSetLimits[0], &PSetLimits[NumPSets], 0);
  83     ++Tag;
  84   }
  85 }
  86
  87 /// compute - Compute the preferred allocation order for RC with reserved
  88 /// registers filtered out. Volatile registers come first followed by CSR
  89 /// aliases ordered according to the CSR order specified by the target.
  90 void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
  91   assert(RC && "no register class given");
  92   RCInfo &RCI = RegClass[RC->getID()];
  93   auto &STI = MF->getSubtarget();
  94
  95   // Raw register count, including all reserved regs.
  96   unsigned NumRegs = RC->getNumRegs();
  97
  98   if (!RCI.Order)
  99     RCI.Order.reset(new MCPhysReg[NumRegs]);
 100
 101   unsigned N = 0;
 102   SmallVector<MCPhysReg, 16> CSRAlias;
 103   unsigned MinCost = 0xff;
 104   unsigned LastCost = ~0u;
 105   unsigned LastCostChange = 0;
 106
 107   // FIXME: Once targets reserve registers instead of removing them from the
 108   // allocation order, we can simply use begin/end here.
 109   ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF);
 110   for (unsigned i = 0; i != RawOrder.size(); ++i) {
 111     unsigned PhysReg = RawOrder[i];
 112     // Remove reserved registers from the allocation order.
 113     if (Reserved.test(PhysReg))
 114       continue;
 115     unsigned Cost = TRI->getCostPerUse(PhysReg);
 116     MinCost = std::min(MinCost, Cost);
 117
 118     if (CalleeSavedAliases[PhysReg] &&
 119         !STI.ignoreCSRForAllocationOrder(*MF, PhysReg))
 120       // PhysReg aliases a CSR, save it for later.
 121       CSRAlias.push_back(PhysReg);
 122     else {
 123       if (Cost != LastCost)
 124         LastCostChange = N;
 125       RCI.Order[N++] = PhysReg;
 126       LastCost = Cost;
 127     }
 128   }
 129   RCI.NumRegs = N + CSRAlias.size();
 130   assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
 131
 132   // CSR aliases go after the volatile registers, preserve the target's order.
 133   for (unsigned i = 0, e = CSRAlias.size(); i != e; ++i) {
 134     unsigned PhysReg = CSRAlias[i];
 135     unsigned Cost = TRI->getCostPerUse(PhysReg);
 136     if (Cost != LastCost)
 137       LastCostChange = N;
 138     RCI.Order[N++] = PhysReg;
 139     LastCost = Cost;
 140   }
 141
 142   // Register allocator stress test.  Clip register class to N registers.
 143   if (StressRA && RCI.NumRegs > StressRA)
 144     RCI.NumRegs = StressRA;
 145
 146   // Check if RC is a proper sub-class.
 147   if (const TargetRegisterClass *Super =
 148           TRI->getLargestLegalSuperClass(RC, *MF))
 149     if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)
 150       RCI.ProperSubClass = true;
 151
 152   RCI.MinCost = uint8_t(MinCost);
 153   RCI.LastCostChange = LastCostChange;
 154
 155   LLVM_DEBUG({
 156     dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ") = [";
 157     for (unsigned I = 0; I != RCI.NumRegs; ++I)
 158       dbgs() << ' ' << printReg(RCI.Order[I], TRI);
 159     dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n" : " ]\n");
 160   });
 161
 162   // RCI is now up-to-date.
 163   RCI.Tag = Tag;
 164 }
 165
 166 /// This is not accurate because two overlapping register sets may have some
 167 /// nonoverlapping reserved registers. However, computing the allocation order
 168 /// for all register classes would be too expensive.
 169 unsigned RegisterClassInfo::computePSetLimit(unsigned Idx) const {
 170   const TargetRegisterClass *RC = nullptr;
 171   unsigned NumRCUnits = 0;
 172   for (const TargetRegisterClass *C : TRI->regclasses()) {
 173     const int *PSetID = TRI->getRegClassPressureSets(C);
 174     for (; *PSetID != -1; ++PSetID) {
 175       if ((unsigned)*PSetID == Idx)
 176         break;
 177     }
 178     if (*PSetID == -1)
 179       continue;
 180
 181     // Found a register class that counts against this pressure set.
 182     // For efficiency, only compute the set order for the largest set.
 183     unsigned NUnits = TRI->getRegClassWeight(C).WeightLimit;
 184     if (!RC || NUnits > NumRCUnits) {
 185       RC = C;
 186       NumRCUnits = NUnits;
 187     }
 188   }
 189   compute(RC);
 190   unsigned NReserved = RC->getNumRegs() - getNumAllocatableRegs(RC);
 191   return TRI->getRegPressureSetLimit(*MF, Idx) -
 192          TRI->getRegClassWeight(RC).RegWeight * NReserved;
 193 }