1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2 # RUN: llc -mtriple=aarch64-unknown-unknown -o - -verify-machineinstrs -run-pass=instruction-select %s | FileCheck %s
6 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
7 target triple = "aarch64-arm-none-eabi"
9 ; Function Attrs: noinline nounwind optnone
10 define void @fp16_to_gpr([2 x half], [2 x half]* %addr) {
14 define void @gpr_to_fp16() {
18 define void @gpr_to_fp16_physreg() {
27 tracksRegLiveness: true
29 - { id: 0, class: gpr }
30 - { id: 1, class: fpr }
31 - { id: 2, class: fpr }
32 - { id: 3, class: gpr }
33 - { id: 4, class: gpr }
34 - { id: 5, class: gpr }
35 - { id: 6, class: gpr }
36 - { id: 7, class: gpr }
37 - { id: 8, class: gpr }
38 - { id: 9, class: gpr }
39 - { id: 10, class: gpr }
40 - { id: 11, class: gpr }
41 - { id: 12, class: gpr }
44 liveins: $h0, $h1, $x0
46 ; CHECK-LABEL: name: fp16_to_gpr
47 ; CHECK: liveins: $h0, $h1, $x0
48 ; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
49 ; CHECK: [[COPY1:%[0-9]+]]:fpr16 = COPY $h1
50 ; CHECK: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
51 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[COPY]], %subreg.hsub
52 ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG]]
53 ; CHECK: [[BFMWri:%[0-9]+]]:gpr32 = BFMWri [[DEF]], [[COPY2]], 0, 15
54 ; CHECK: [[SUBREG_TO_REG1:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[COPY1]], %subreg.hsub
55 ; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG1]]
56 ; CHECK: [[BFMWri1:%[0-9]+]]:gpr32 = BFMWri [[BFMWri]], [[COPY3]], 16, 15
57 ; CHECK: [[COPY4:%[0-9]+]]:gpr64sp = COPY $x0
58 ; CHECK: STRWui [[BFMWri1]], [[COPY4]], 0 :: (store 4 into %ir.addr, align 2)
60 %1:fpr(s16) = COPY $h0
61 %2:fpr(s16) = COPY $h1
62 %3:gpr(s32) = G_IMPLICIT_DEF
63 %11:gpr(s16) = COPY %1(s16)
64 %4:gpr(s32) = G_INSERT %3, %11(s16), 0
65 %12:gpr(s16) = COPY %2(s16)
66 %5:gpr(s32) = G_INSERT %4, %12(s16), 16
67 %0:gpr(s32) = COPY %5(s32)
69 G_STORE %0(s32), %6(p0) :: (store 4 into %ir.addr, align 2)
79 tracksRegLiveness: true
81 - { id: 0, class: gpr }
82 - { id: 1, class: gpr }
83 - { id: 2, class: fpr }
88 ; CHECK-LABEL: name: gpr_to_fp16
90 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
91 ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]]
92 ; CHECK: [[COPY2:%[0-9]+]]:fpr16 = COPY [[COPY1]].hsub
93 ; CHECK: $h0 = COPY [[COPY2]]
94 ; CHECK: RET_ReallyLR implicit $h0
95 %0:gpr(s32) = COPY $w0
96 %1:gpr(s16) = G_TRUNC %0(s32)
97 %2:fpr(s16) = COPY %1(s16)
99 RET_ReallyLR implicit $h0
103 name: gpr_to_fp16_physreg
106 regBankSelected: true
107 tracksRegLiveness: true
109 - { id: 0, class: gpr }
110 - { id: 1, class: gpr }
115 ; CHECK-LABEL: name: gpr_to_fp16_physreg
116 ; CHECK: liveins: $w0
117 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
118 ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]]
119 ; CHECK: [[COPY2:%[0-9]+]]:fpr16 = COPY [[COPY1]].hsub
120 ; CHECK: $h0 = COPY [[COPY2]]
121 ; CHECK: RET_ReallyLR implicit $h0
122 %0:gpr(s32) = COPY $w0
123 %1:gpr(s16) = G_TRUNC %0(s32)
125 RET_ReallyLR implicit $h0