1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2 # RUN: llc -mtriple=aarch64-- -mattr=+lse -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
5 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
7 define void @atomicrmw_xchg_i64(i64* %addr) { ret void }
8 define void @atomicrmw_add_i64(i64* %addr) { ret void }
9 define void @atomicrmw_add_i32(i64* %addr) { ret void }
10 define void @atomicrmw_sub_i32(i64* %addr) { ret void }
11 define void @atomicrmw_and_i32(i64* %addr) { ret void }
13 define void @atomicrmw_or_i32(i64* %addr) { ret void }
14 define void @atomicrmw_xor_i32(i64* %addr) { ret void }
15 define void @atomicrmw_min_i32(i64* %addr) { ret void }
16 define void @atomicrmw_max_i32(i64* %addr) { ret void }
17 define void @atomicrmw_umin_i32(i64* %addr) { ret void }
18 define void @atomicrmw_umax_i32(i64* %addr) { ret void }
22 name: atomicrmw_xchg_i64
30 ; CHECK-LABEL: name: atomicrmw_xchg_i64
31 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
32 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
33 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
34 ; CHECK: [[SWPX:%[0-9]+]]:gpr64 = SWPX [[SUBREG_TO_REG]], [[COPY]] :: (load store monotonic 8 on %ir.addr)
35 ; CHECK: $x0 = COPY [[SWPX]]
37 %1:gpr(s64) = G_CONSTANT i64 1
38 %2:gpr(s64) = G_ATOMICRMW_XCHG %0, %1 :: (load store monotonic 8 on %ir.addr)
42 name: atomicrmw_add_i64
50 ; CHECK-LABEL: name: atomicrmw_add_i64
51 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
52 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
53 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
54 ; CHECK: [[LDADDX:%[0-9]+]]:gpr64 = LDADDX [[SUBREG_TO_REG]], [[COPY]] :: (load store monotonic 8 on %ir.addr)
55 ; CHECK: $x0 = COPY [[LDADDX]]
57 %1:gpr(s64) = G_CONSTANT i64 1
58 %2:gpr(s64) = G_ATOMICRMW_ADD %0, %1 :: (load store monotonic 8 on %ir.addr)
62 name: atomicrmw_add_i32
70 ; CHECK-LABEL: name: atomicrmw_add_i32
71 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
72 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
73 ; CHECK: [[LDADDALW:%[0-9]+]]:gpr32 = LDADDALW [[MOVi32imm]], [[COPY]] :: (load store seq_cst 4 on %ir.addr)
74 ; CHECK: $w0 = COPY [[LDADDALW]]
76 %1:gpr(s32) = G_CONSTANT i32 1
77 %2:gpr(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 4 on %ir.addr)
82 name: atomicrmw_sub_i32
90 ; CHECK-LABEL: name: atomicrmw_sub_i32
91 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
92 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
93 ; CHECK: [[LDADDALW:%[0-9]+]]:gpr32 = LDADDALW [[MOVi32imm]], [[COPY]] :: (load store seq_cst 4 on %ir.addr)
94 ; CHECK: $w0 = COPY [[LDADDALW]]
96 %1:gpr(s32) = G_CONSTANT i32 1
97 %2:gpr(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 4 on %ir.addr)
102 name: atomicrmw_and_i32
104 regBankSelected: true
110 ; CHECK-LABEL: name: atomicrmw_and_i32
111 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
112 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
113 ; CHECK: [[ORNWrr:%[0-9]+]]:gpr32 = ORNWrr $wzr, [[MOVi32imm]]
114 ; CHECK: [[LDCLRAW:%[0-9]+]]:gpr32 = LDCLRAW [[ORNWrr]], [[COPY]] :: (load store acquire 4 on %ir.addr)
115 ; CHECK: $w0 = COPY [[LDCLRAW]]
116 %0:gpr(p0) = COPY $x0
117 %1:gpr(s32) = G_CONSTANT i32 1
118 %2:gpr(s32) = G_ATOMICRMW_AND %0, %1 :: (load store acquire 4 on %ir.addr)
123 name: atomicrmw_or_i32
125 regBankSelected: true
131 ; CHECK-LABEL: name: atomicrmw_or_i32
132 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
133 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
134 ; CHECK: [[LDSETLW:%[0-9]+]]:gpr32 = LDSETLW [[MOVi32imm]], [[COPY]] :: (load store release 4 on %ir.addr)
135 ; CHECK: $w0 = COPY [[LDSETLW]]
136 %0:gpr(p0) = COPY $x0
137 %1:gpr(s32) = G_CONSTANT i32 1
138 %2:gpr(s32) = G_ATOMICRMW_OR %0, %1 :: (load store release 4 on %ir.addr)
143 name: atomicrmw_xor_i32
145 regBankSelected: true
151 ; CHECK-LABEL: name: atomicrmw_xor_i32
152 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
153 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
154 ; CHECK: [[LDEORALW:%[0-9]+]]:gpr32 = LDEORALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel 4 on %ir.addr)
155 ; CHECK: $w0 = COPY [[LDEORALW]]
156 %0:gpr(p0) = COPY $x0
157 %1:gpr(s32) = G_CONSTANT i32 1
158 %2:gpr(s32) = G_ATOMICRMW_XOR %0, %1 :: (load store acq_rel 4 on %ir.addr)
163 name: atomicrmw_min_i32
165 regBankSelected: true
171 ; CHECK-LABEL: name: atomicrmw_min_i32
172 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
173 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
174 ; CHECK: [[LDSMINALW:%[0-9]+]]:gpr32 = LDSMINALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel 4 on %ir.addr)
175 ; CHECK: $w0 = COPY [[LDSMINALW]]
176 %0:gpr(p0) = COPY $x0
177 %1:gpr(s32) = G_CONSTANT i32 1
178 %2:gpr(s32) = G_ATOMICRMW_MIN %0, %1 :: (load store acq_rel 4 on %ir.addr)
183 name: atomicrmw_max_i32
185 regBankSelected: true
191 ; CHECK-LABEL: name: atomicrmw_max_i32
192 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
193 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
194 ; CHECK: [[LDSMAXALW:%[0-9]+]]:gpr32 = LDSMAXALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel 4 on %ir.addr)
195 ; CHECK: $w0 = COPY [[LDSMAXALW]]
196 %0:gpr(p0) = COPY $x0
197 %1:gpr(s32) = G_CONSTANT i32 1
198 %2:gpr(s32) = G_ATOMICRMW_MAX %0, %1 :: (load store acq_rel 4 on %ir.addr)
203 name: atomicrmw_umin_i32
205 regBankSelected: true
211 ; CHECK-LABEL: name: atomicrmw_umin_i32
212 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
213 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
214 ; CHECK: [[LDUMINALW:%[0-9]+]]:gpr32 = LDUMINALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel 4 on %ir.addr)
215 ; CHECK: $w0 = COPY [[LDUMINALW]]
216 %0:gpr(p0) = COPY $x0
217 %1:gpr(s32) = G_CONSTANT i32 1
218 %2:gpr(s32) = G_ATOMICRMW_UMIN %0, %1 :: (load store acq_rel 4 on %ir.addr)
223 name: atomicrmw_umax_i32
225 regBankSelected: true
231 ; CHECK-LABEL: name: atomicrmw_umax_i32
232 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
233 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
234 ; CHECK: [[LDUMAXALW:%[0-9]+]]:gpr32 = LDUMAXALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel 4 on %ir.addr)
235 ; CHECK: $w0 = COPY [[LDUMAXALW]]
236 %0:gpr(p0) = COPY $x0
237 %1:gpr(s32) = G_CONSTANT i32 1
238 %2:gpr(s32) = G_ATOMICRMW_UMAX %0, %1 :: (load store acq_rel 4 on %ir.addr)