[MIParser] Set RegClassOrRegBank during instruction parsing
[llvm-complete.git] / test / CodeGen / AArch64 / aarch64-named-reg-w18.ll
blob0e6aef66eab7c4305f72f765fdf1b013d1568f21
1 ; RUN: llc -mtriple=aarch64-fuchsia -o - %s
3 define void @set_w18(i32 %x) {
4 entry:
5 ; FIXME: Include an allocatable-specific error message
6   tail call void @llvm.write_register.i32(metadata !0, i32 %x)
7   ret void
10 declare void @llvm.write_register.i32(metadata, i32) nounwind
12 !0 = !{!"w18"}