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[MIParser] Set RegClassOrRegBank during instruction parsing
[llvm-complete.git]
/
test
/
CodeGen
/
AArch64
/
legalize-bug-bogus-cpu.ll
blob
a96a3c5f48810d973616db066080937540979c59
1
; RUN: llc < %s -mtriple=aarch64-eabi -mcpu=bogus
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; Fix the bug in PR20557. Set mcpu to a bogus name, llc will crash in type
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; legalization.
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define <4 x float> @fneg4(<4 x float> %x) {
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%sub = fsub <4 x float> zeroinitializer, %x
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ret <4 x float> %sub
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}