1 ; RUN: llc -mtriple aarch64-none-linux-gnu -mattr=+dotprod < %s | FileCheck %s
2 ; RUN: llc -mtriple aarch64-none-linux-gnu -mcpu=cortex-a65 < %s | FileCheck %s
3 ; RUN: llc -mtriple aarch64-none-linux-gnu -mcpu=cortex-a65ae < %s | FileCheck %s
4 ; RUN: llc -mtriple aarch64-none-linux-gnu -mcpu=neoverse-e1 < %s | FileCheck %s
5 ; RUN: llc -mtriple aarch64-none-linux-gnu -mcpu=neoverse-n1 < %s | FileCheck %s
7 declare <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32>, <8 x i8>, <8 x i8>)
8 declare <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32>, <16 x i8>, <16 x i8>)
9 declare <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32>, <8 x i8>, <8 x i8>)
10 declare <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32>, <16 x i8>, <16 x i8>)
12 define <2 x i32> @test_vdot_u32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) #0 {
14 ; CHECK-LABEL: test_vdot_u32:
15 ; CHECK: udot v0.2s, v1.8b, v2.8b
16 %vdot1.i = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) #2
17 ret <2 x i32> %vdot1.i
20 define <4 x i32> @test_vdotq_u32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) #0 {
22 ; CHECK-LABEL: test_vdotq_u32:
23 ; CHECK: udot v0.4s, v1.16b, v2.16b
24 %vdot1.i = call <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) #2
25 ret <4 x i32> %vdot1.i
28 define <2 x i32> @test_vdot_s32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) #0 {
30 ; CHECK-LABEL: test_vdot_s32:
31 ; CHECK: sdot v0.2s, v1.8b, v2.8b
32 %vdot1.i = call <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) #2
33 ret <2 x i32> %vdot1.i
36 define <4 x i32> @test_vdotq_s32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) #0 {
38 ; CHECK-LABEL: test_vdotq_s32:
39 ; CHECK: sdot v0.4s, v1.16b, v2.16b
40 %vdot1.i = call <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) #2
41 ret <4 x i32> %vdot1.i
44 define <2 x i32> @test_vdot_lane_u32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) {
46 ; CHECK-LABEL: test_vdot_lane_u32:
47 ; CHECK: udot v0.2s, v1.8b, v2.4b[1]
48 %.cast = bitcast <8 x i8> %c to <2 x i32>
49 %shuffle = shufflevector <2 x i32> %.cast, <2 x i32> undef, <2 x i32> <i32 1, i32 1>
50 %.cast5 = bitcast <2 x i32> %shuffle to <8 x i8>
51 %vdot1.i = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %.cast5) #2
52 ret <2 x i32> %vdot1.i
55 define <4 x i32> @test_vdotq_lane_u32(<4 x i32> %a, <16 x i8> %b, <8 x i8> %c) {
57 ; CHECK-LABEL: test_vdotq_lane_u32:
58 ; CHECK: udot v0.4s, v1.16b, v2.4b[1]
59 %.cast = bitcast <8 x i8> %c to <2 x i32>
60 %shuffle = shufflevector <2 x i32> %.cast, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
61 %.cast3 = bitcast <4 x i32> %shuffle to <16 x i8>
62 %vdot1.i = call <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %.cast3) #2
63 ret <4 x i32> %vdot1.i
66 define <2 x i32> @test_vdot_laneq_u32(<2 x i32> %a, <8 x i8> %b, <16 x i8> %c) {
68 ; CHECK-LABEL: test_vdot_laneq_u32:
69 ; CHECK: udot v0.2s, v1.8b, v2.4b[1]
70 %.cast = bitcast <16 x i8> %c to <4 x i32>
71 %shuffle = shufflevector <4 x i32> %.cast, <4 x i32> undef, <2 x i32> <i32 1, i32 1>
72 %.cast5 = bitcast <2 x i32> %shuffle to <8 x i8>
73 %vdot1.i = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %.cast5) #2
74 ret <2 x i32> %vdot1.i
77 define <4 x i32> @test_vdotq_laneq_u32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) {
79 ; CHECK-LABEL: test_vdotq_laneq_u32:
80 ; CHECK: udot v0.4s, v1.16b, v2.4b[1]
81 %.cast = bitcast <16 x i8> %c to <4 x i32>
82 %shuffle = shufflevector <4 x i32> %.cast, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
83 %.cast3 = bitcast <4 x i32> %shuffle to <16 x i8>
84 %vdot1.i = call <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %.cast3) #2
85 ret <4 x i32> %vdot1.i
88 define <2 x i32> @test_vdot_lane_s32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) {
90 ; CHECK-LABEL: test_vdot_lane_s32:
91 ; CHECK: sdot v0.2s, v1.8b, v2.4b[1]
92 %.cast = bitcast <8 x i8> %c to <2 x i32>
93 %shuffle = shufflevector <2 x i32> %.cast, <2 x i32> undef, <2 x i32> <i32 1, i32 1>
94 %.cast5 = bitcast <2 x i32> %shuffle to <8 x i8>
95 %vdot1.i = call <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %.cast5) #2
96 ret <2 x i32> %vdot1.i
99 define <4 x i32> @test_vdotq_lane_s32(<4 x i32> %a, <16 x i8> %b, <8 x i8> %c) {
101 ; CHECK-LABEL: test_vdotq_lane_s32:
102 ; CHECK: sdot v0.4s, v1.16b, v2.4b[1]
103 %.cast = bitcast <8 x i8> %c to <2 x i32>
104 %shuffle = shufflevector <2 x i32> %.cast, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
105 %.cast3 = bitcast <4 x i32> %shuffle to <16 x i8>
106 %vdot1.i = call <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %.cast3) #2
107 ret <4 x i32> %vdot1.i
110 define <2 x i32> @test_vdot_laneq_s32(<2 x i32> %a, <8 x i8> %b, <16 x i8> %c) {
112 ; CHECK-LABEL: test_vdot_laneq_s32:
113 ; CHECK: sdot v0.2s, v1.8b, v2.4b[1]
114 %.cast = bitcast <16 x i8> %c to <4 x i32>
115 %shuffle = shufflevector <4 x i32> %.cast, <4 x i32> undef, <2 x i32> <i32 1, i32 1>
116 %.cast5 = bitcast <2 x i32> %shuffle to <8 x i8>
117 %vdot1.i = call <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %.cast5) #2
118 ret <2 x i32> %vdot1.i
121 define <4 x i32> @test_vdotq_laneq_s32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) {
123 ; CHECK-LABEL: test_vdotq_laneq_s32:
124 ; CHECK: sdot v0.4s, v1.16b, v2.4b[1]
125 %.cast = bitcast <16 x i8> %c to <4 x i32>
126 %shuffle = shufflevector <4 x i32> %.cast, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
127 %.cast3 = bitcast <4 x i32> %shuffle to <16 x i8>
128 %vdot1.i = call <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %.cast3) #2
129 ret <4 x i32> %vdot1.i
132 define fastcc void @test_sdot_v4i8(i8* noalias nocapture %0, i8* noalias nocapture readonly %1, i8* noalias nocapture readonly %2) {
134 ; CHECK-LABEL: test_sdot_v4i8:
135 ; CHECK: sdot {{v[0-9]+}}.2s, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
136 %3 = bitcast i8* %0 to i32*
137 %4 = load i8, i8* %1, align 1
138 %5 = sext i8 %4 to i32
139 %6 = load i8, i8* %2, align 1
140 %7 = sext i8 %6 to i32
141 %8 = mul nsw i32 %7, %5
142 %9 = getelementptr inbounds i8, i8* %1, i64 1
143 %10 = load i8, i8* %9, align 1
144 %11 = sext i8 %10 to i32
145 %12 = getelementptr inbounds i8, i8* %2, i64 1
146 %13 = load i8, i8* %12, align 1
147 %14 = sext i8 %13 to i32
148 %15 = mul nsw i32 %14, %11
149 %16 = add nsw i32 %15, %8
150 %17 = getelementptr inbounds i8, i8* %1, i64 2
151 %18 = load i8, i8* %17, align 1
152 %19 = sext i8 %18 to i32
153 %20 = getelementptr inbounds i8, i8* %2, i64 2
154 %21 = load i8, i8* %20, align 1
155 %22 = sext i8 %21 to i32
156 %23 = mul nsw i32 %22, %19
157 %24 = add nsw i32 %23, %16
158 %25 = getelementptr inbounds i8, i8* %1, i64 3
159 %26 = load i8, i8* %25, align 1
160 %27 = sext i8 %26 to i32
161 %28 = getelementptr inbounds i8, i8* %2, i64 3
162 %29 = load i8, i8* %28, align 1
163 %30 = sext i8 %29 to i32
164 %31 = mul nsw i32 %30, %27
165 %32 = add nsw i32 %31, %24
166 store i32 %32, i32* %3, align 64
170 define fastcc void @test_udot_v4i8(i8* noalias nocapture %0, i8* noalias nocapture readonly %1, i8* noalias nocapture readonly %2) {
172 ; CHECK-LABEL: test_udot_v4i8:
173 ; CHECK: udot {{v[0-9]+}}.2s, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
174 %3 = bitcast i8* %0 to i32*
175 %4 = load i8, i8* %1, align 1
176 %5 = zext i8 %4 to i32
177 %6 = load i8, i8* %2, align 1
178 %7 = zext i8 %6 to i32
179 %8 = mul nsw i32 %7, %5
180 %9 = getelementptr inbounds i8, i8* %1, i64 1
181 %10 = load i8, i8* %9, align 1
182 %11 = zext i8 %10 to i32
183 %12 = getelementptr inbounds i8, i8* %2, i64 1
184 %13 = load i8, i8* %12, align 1
185 %14 = zext i8 %13 to i32
186 %15 = mul nsw i32 %14, %11
187 %16 = add nsw i32 %15, %8
188 %17 = getelementptr inbounds i8, i8* %1, i64 2
189 %18 = load i8, i8* %17, align 1
190 %19 = zext i8 %18 to i32
191 %20 = getelementptr inbounds i8, i8* %2, i64 2
192 %21 = load i8, i8* %20, align 1
193 %22 = zext i8 %21 to i32
194 %23 = mul nsw i32 %22, %19
195 %24 = add nsw i32 %23, %16
196 %25 = getelementptr inbounds i8, i8* %1, i64 3
197 %26 = load i8, i8* %25, align 1
198 %27 = zext i8 %26 to i32
199 %28 = getelementptr inbounds i8, i8* %2, i64 3
200 %29 = load i8, i8* %28, align 1
201 %30 = zext i8 %29 to i32
202 %31 = mul nsw i32 %30, %27
203 %32 = add nsw i32 %31, %24
204 store i32 %32, i32* %3, align 64
208 declare i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32>)
210 define i32 @test_udot_v8i8(i8* nocapture readonly %a, i8* nocapture readonly %b) {
212 ; CHECK-LABEL: test_udot_v8i8:
213 ; CHECK: udot {{v[0-9]+}}.2s, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
214 %0 = bitcast i8* %a to <8 x i8>*
215 %1 = load <8 x i8>, <8 x i8>* %0
216 %2 = zext <8 x i8> %1 to <8 x i32>
217 %3 = bitcast i8* %b to <8 x i8>*
218 %4 = load <8 x i8>, <8 x i8>* %3
219 %5 = zext <8 x i8> %4 to <8 x i32>
220 %6 = mul nuw nsw <8 x i32> %5, %2
221 %7 = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> %6)
225 define i32 @test_sdot_v8i8(i8* nocapture readonly %a, i8* nocapture readonly %b) {
227 ; CHECK-LABEL: test_sdot_v8i8:
228 ; CHECK: sdot {{v[0-9]+}}.2s, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
229 %0 = bitcast i8* %a to <8 x i8>*
230 %1 = load <8 x i8>, <8 x i8>* %0
231 %2 = sext <8 x i8> %1 to <8 x i32>
232 %3 = bitcast i8* %b to <8 x i8>*
233 %4 = load <8 x i8>, <8 x i8>* %3
234 %5 = sext <8 x i8> %4 to <8 x i32>
235 %6 = mul nsw <8 x i32> %5, %2
236 %7 = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> %6)
240 declare i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32>)
242 define i32 @test_udot_v16i8(i8* nocapture readonly %a, i8* nocapture readonly %b, i32 %sum) {
244 ; CHECK-LABEL: test_udot_v16i8:
245 ; CHECK: udot {{v[0-9]+}}.4s, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
246 %0 = bitcast i8* %a to <16 x i8>*
247 %1 = load <16 x i8>, <16 x i8>* %0
248 %2 = zext <16 x i8> %1 to <16 x i32>
249 %3 = bitcast i8* %b to <16 x i8>*
250 %4 = load <16 x i8>, <16 x i8>* %3
251 %5 = zext <16 x i8> %4 to <16 x i32>
252 %6 = mul nuw nsw <16 x i32> %5, %2
253 %7 = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %6)
254 %op.extra = add i32 %7, %sum
258 define i32 @test_sdot_v16i8(i8* nocapture readonly %a, i8* nocapture readonly %b, i32 %sum) {
260 ; CHECK-LABEL: test_sdot_v16i8:
261 ; CHECK: sdot {{v[0-9]+}}.4s, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
262 %0 = bitcast i8* %a to <16 x i8>*
263 %1 = load <16 x i8>, <16 x i8>* %0
264 %2 = sext <16 x i8> %1 to <16 x i32>
265 %3 = bitcast i8* %b to <16 x i8>*
266 %4 = load <16 x i8>, <16 x i8>* %3
267 %5 = sext <16 x i8> %4 to <16 x i32>
268 %6 = mul nsw <16 x i32> %5, %2
269 %7 = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %6)
270 %op.extra = add nsw i32 %7, %sum