| blob | ab886b883afb40f3f4d6d85b941ffe1a243cee7c |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
4 declare <1 x i8> @llvm.sadd.sat.v1i8(<1 x i8>, <1 x i8>)
5 declare <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8>, <2 x i8>)
6 declare <4 x i8> @llvm.sadd.sat.v4i8(<4 x i8>, <4 x i8>)
7 declare <8 x i8> @llvm.sadd.sat.v8i8(<8 x i8>, <8 x i8>)
8 declare <12 x i8> @llvm.sadd.sat.v12i8(<12 x i8>, <12 x i8>)
9 declare <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8>, <16 x i8>)
10 declare <32 x i8> @llvm.sadd.sat.v32i8(<32 x i8>, <32 x i8>)
11 declare <64 x i8> @llvm.sadd.sat.v64i8(<64 x i8>, <64 x i8>)
13 declare <1 x i16> @llvm.sadd.sat.v1i16(<1 x i16>, <1 x i16>)
14 declare <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16>, <2 x i16>)
15 declare <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16>, <4 x i16>)
16 declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16>, <8 x i16>)
17 declare <12 x i16> @llvm.sadd.sat.v12i16(<12 x i16>, <12 x i16>)
18 declare <16 x i16> @llvm.sadd.sat.v16i16(<16 x i16>, <16 x i16>)
19 declare <32 x i16> @llvm.sadd.sat.v32i16(<32 x i16>, <32 x i16>)
21 declare <16 x i1> @llvm.sadd.sat.v16i1(<16 x i1>, <16 x i1>)
22 declare <16 x i4> @llvm.sadd.sat.v16i4(<16 x i4>, <16 x i4>)
24 declare <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32>, <2 x i32>)
25 declare <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32>, <4 x i32>)
26 declare <8 x i32> @llvm.sadd.sat.v8i32(<8 x i32>, <8 x i32>)
27 declare <16 x i32> @llvm.sadd.sat.v16i32(<16 x i32>, <16 x i32>)
28 declare <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64>, <2 x i64>)
29 declare <4 x i64> @llvm.sadd.sat.v4i64(<4 x i64>, <4 x i64>)
30 declare <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64>, <8 x i64>)
32 declare <4 x i24> @llvm.sadd.sat.v4i24(<4 x i24>, <4 x i24>)
33 declare <2 x i128> @llvm.sadd.sat.v2i128(<2 x i128>, <2 x i128>)
35 define <16 x i8> @v16i8(<16 x i8> %x, <16 x i8> %y) nounwind {
36 ; CHECK-LABEL: v16i8:
37 ; CHECK: // %bb.0:
38 ; CHECK-NEXT: add v2.16b, v0.16b, v1.16b
39 ; CHECK-NEXT: cmlt v4.16b, v2.16b, #0
40 ; CHECK-NEXT: movi v3.16b, #127
41 ; CHECK-NEXT: cmlt v1.16b, v1.16b, #0
42 ; CHECK-NEXT: cmgt v0.16b, v0.16b, v2.16b
43 ; CHECK-NEXT: mvn v5.16b, v4.16b
44 ; CHECK-NEXT: bsl v3.16b, v4.16b, v5.16b
45 ; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b
46 ; CHECK-NEXT: bsl v0.16b, v3.16b, v2.16b
47 ; CHECK-NEXT: ret
48 %z = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y)
49 ret <16 x i8> %z
50 }
52 define <32 x i8> @v32i8(<32 x i8> %x, <32 x i8> %y) nounwind {
53 ; CHECK-LABEL: v32i8:
54 ; CHECK: // %bb.0:
55 ; CHECK-NEXT: add v4.16b, v0.16b, v2.16b
56 ; CHECK-NEXT: cmlt v7.16b, v4.16b, #0
57 ; CHECK-NEXT: movi v6.16b, #127
58 ; CHECK-NEXT: mvn v16.16b, v7.16b
59 ; CHECK-NEXT: bsl v6.16b, v7.16b, v16.16b
60 ; CHECK-NEXT: add v7.16b, v1.16b, v3.16b
61 ; CHECK-NEXT: cmlt v2.16b, v2.16b, #0
62 ; CHECK-NEXT: cmgt v0.16b, v0.16b, v4.16b
63 ; CHECK-NEXT: cmlt v16.16b, v7.16b, #0
64 ; CHECK-NEXT: movi v5.16b, #127
65 ; CHECK-NEXT: cmlt v3.16b, v3.16b, #0
66 ; CHECK-NEXT: cmgt v1.16b, v1.16b, v7.16b
67 ; CHECK-NEXT: eor v0.16b, v2.16b, v0.16b
68 ; CHECK-NEXT: mvn v2.16b, v16.16b
69 ; CHECK-NEXT: eor v1.16b, v3.16b, v1.16b
70 ; CHECK-NEXT: bsl v5.16b, v16.16b, v2.16b
71 ; CHECK-NEXT: bsl v0.16b, v6.16b, v4.16b
72 ; CHECK-NEXT: bsl v1.16b, v5.16b, v7.16b
73 ; CHECK-NEXT: ret
74 %z = call <32 x i8> @llvm.sadd.sat.v32i8(<32 x i8> %x, <32 x i8> %y)
75 ret <32 x i8> %z
76 }
78 define <64 x i8> @v64i8(<64 x i8> %x, <64 x i8> %y) nounwind {
79 ; CHECK-LABEL: v64i8:
80 ; CHECK: // %bb.0:
81 ; CHECK-NEXT: add v16.16b, v0.16b, v4.16b
82 ; CHECK-NEXT: cmlt v24.16b, v16.16b, #0
83 ; CHECK-NEXT: movi v18.16b, #127
84 ; CHECK-NEXT: add v19.16b, v1.16b, v5.16b
85 ; CHECK-NEXT: mvn v25.16b, v24.16b
86 ; CHECK-NEXT: bsl v18.16b, v24.16b, v25.16b
87 ; CHECK-NEXT: cmlt v24.16b, v19.16b, #0
88 ; CHECK-NEXT: movi v20.16b, #127
89 ; CHECK-NEXT: add v21.16b, v2.16b, v6.16b
90 ; CHECK-NEXT: mvn v25.16b, v24.16b
91 ; CHECK-NEXT: bsl v20.16b, v24.16b, v25.16b
92 ; CHECK-NEXT: cmlt v24.16b, v21.16b, #0
93 ; CHECK-NEXT: cmlt v4.16b, v4.16b, #0
94 ; CHECK-NEXT: cmgt v0.16b, v0.16b, v16.16b
95 ; CHECK-NEXT: movi v22.16b, #127
96 ; CHECK-NEXT: add v23.16b, v3.16b, v7.16b
97 ; CHECK-NEXT: mvn v25.16b, v24.16b
98 ; CHECK-NEXT: eor v0.16b, v4.16b, v0.16b
99 ; CHECK-NEXT: cmlt v4.16b, v5.16b, #0
100 ; CHECK-NEXT: cmgt v1.16b, v1.16b, v19.16b
101 ; CHECK-NEXT: bsl v22.16b, v24.16b, v25.16b
102 ; CHECK-NEXT: cmlt v24.16b, v23.16b, #0
103 ; CHECK-NEXT: eor v1.16b, v4.16b, v1.16b
104 ; CHECK-NEXT: cmlt v4.16b, v6.16b, #0
105 ; CHECK-NEXT: cmgt v2.16b, v2.16b, v21.16b
106 ; CHECK-NEXT: movi v17.16b, #127
107 ; CHECK-NEXT: mvn v25.16b, v24.16b
108 ; CHECK-NEXT: eor v2.16b, v4.16b, v2.16b
109 ; CHECK-NEXT: cmlt v4.16b, v7.16b, #0
110 ; CHECK-NEXT: cmgt v3.16b, v3.16b, v23.16b
111 ; CHECK-NEXT: bsl v17.16b, v24.16b, v25.16b
112 ; CHECK-NEXT: eor v3.16b, v4.16b, v3.16b
113 ; CHECK-NEXT: bsl v0.16b, v18.16b, v16.16b
114 ; CHECK-NEXT: bsl v1.16b, v20.16b, v19.16b
115 ; CHECK-NEXT: bsl v2.16b, v22.16b, v21.16b
116 ; CHECK-NEXT: bsl v3.16b, v17.16b, v23.16b
117 ; CHECK-NEXT: ret
118 %z = call <64 x i8> @llvm.sadd.sat.v64i8(<64 x i8> %x, <64 x i8> %y)
119 ret <64 x i8> %z
120 }
122 define <8 x i16> @v8i16(<8 x i16> %x, <8 x i16> %y) nounwind {
123 ; CHECK-LABEL: v8i16:
124 ; CHECK: // %bb.0:
125 ; CHECK-NEXT: add v2.8h, v0.8h, v1.8h
126 ; CHECK-NEXT: cmlt v4.8h, v2.8h, #0
127 ; CHECK-NEXT: mvni v3.8h, #128, lsl #8
128 ; CHECK-NEXT: cmlt v1.8h, v1.8h, #0
129 ; CHECK-NEXT: cmgt v0.8h, v0.8h, v2.8h
130 ; CHECK-NEXT: mvn v5.16b, v4.16b
131 ; CHECK-NEXT: bsl v3.16b, v4.16b, v5.16b
132 ; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b
133 ; CHECK-NEXT: bsl v0.16b, v3.16b, v2.16b
134 ; CHECK-NEXT: ret
135 %z = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y)
136 ret <8 x i16> %z
137 }
139 define <16 x i16> @v16i16(<16 x i16> %x, <16 x i16> %y) nounwind {
140 ; CHECK-LABEL: v16i16:
141 ; CHECK: // %bb.0:
142 ; CHECK-NEXT: add v4.8h, v0.8h, v2.8h
143 ; CHECK-NEXT: cmlt v7.8h, v4.8h, #0
144 ; CHECK-NEXT: mvni v6.8h, #128, lsl #8
145 ; CHECK-NEXT: mvn v16.16b, v7.16b
146 ; CHECK-NEXT: bsl v6.16b, v7.16b, v16.16b
147 ; CHECK-NEXT: add v7.8h, v1.8h, v3.8h
148 ; CHECK-NEXT: cmlt v2.8h, v2.8h, #0
149 ; CHECK-NEXT: cmgt v0.8h, v0.8h, v4.8h
150 ; CHECK-NEXT: cmlt v16.8h, v7.8h, #0
151 ; CHECK-NEXT: mvni v5.8h, #128, lsl #8
152 ; CHECK-NEXT: cmlt v3.8h, v3.8h, #0
153 ; CHECK-NEXT: cmgt v1.8h, v1.8h, v7.8h
154 ; CHECK-NEXT: eor v0.16b, v2.16b, v0.16b
155 ; CHECK-NEXT: mvn v2.16b, v16.16b
156 ; CHECK-NEXT: eor v1.16b, v3.16b, v1.16b
157 ; CHECK-NEXT: bsl v5.16b, v16.16b, v2.16b
158 ; CHECK-NEXT: bsl v0.16b, v6.16b, v4.16b
159 ; CHECK-NEXT: bsl v1.16b, v5.16b, v7.16b
160 ; CHECK-NEXT: ret
161 %z = call <16 x i16> @llvm.sadd.sat.v16i16(<16 x i16> %x, <16 x i16> %y)
162 ret <16 x i16> %z
163 }
165 define <32 x i16> @v32i16(<32 x i16> %x, <32 x i16> %y) nounwind {
166 ; CHECK-LABEL: v32i16:
167 ; CHECK: // %bb.0:
168 ; CHECK-NEXT: add v16.8h, v0.8h, v4.8h
169 ; CHECK-NEXT: cmlt v24.8h, v16.8h, #0
170 ; CHECK-NEXT: mvni v18.8h, #128, lsl #8
171 ; CHECK-NEXT: add v19.8h, v1.8h, v5.8h
172 ; CHECK-NEXT: mvn v25.16b, v24.16b
173 ; CHECK-NEXT: bsl v18.16b, v24.16b, v25.16b
174 ; CHECK-NEXT: cmlt v24.8h, v19.8h, #0
175 ; CHECK-NEXT: mvni v20.8h, #128, lsl #8
176 ; CHECK-NEXT: add v21.8h, v2.8h, v6.8h
177 ; CHECK-NEXT: mvn v25.16b, v24.16b
178 ; CHECK-NEXT: bsl v20.16b, v24.16b, v25.16b
179 ; CHECK-NEXT: cmlt v24.8h, v21.8h, #0
180 ; CHECK-NEXT: cmlt v4.8h, v4.8h, #0
181 ; CHECK-NEXT: cmgt v0.8h, v0.8h, v16.8h
182 ; CHECK-NEXT: mvni v22.8h, #128, lsl #8
183 ; CHECK-NEXT: add v23.8h, v3.8h, v7.8h
184 ; CHECK-NEXT: mvn v25.16b, v24.16b
185 ; CHECK-NEXT: eor v0.16b, v4.16b, v0.16b
186 ; CHECK-NEXT: cmlt v4.8h, v5.8h, #0
187 ; CHECK-NEXT: cmgt v1.8h, v1.8h, v19.8h
188 ; CHECK-NEXT: bsl v22.16b, v24.16b, v25.16b
189 ; CHECK-NEXT: cmlt v24.8h, v23.8h, #0
190 ; CHECK-NEXT: eor v1.16b, v4.16b, v1.16b
191 ; CHECK-NEXT: cmlt v4.8h, v6.8h, #0
192 ; CHECK-NEXT: cmgt v2.8h, v2.8h, v21.8h
193 ; CHECK-NEXT: mvni v17.8h, #128, lsl #8
194 ; CHECK-NEXT: mvn v25.16b, v24.16b
195 ; CHECK-NEXT: eor v2.16b, v4.16b, v2.16b
196 ; CHECK-NEXT: cmlt v4.8h, v7.8h, #0
197 ; CHECK-NEXT: cmgt v3.8h, v3.8h, v23.8h
198 ; CHECK-NEXT: bsl v17.16b, v24.16b, v25.16b
199 ; CHECK-NEXT: eor v3.16b, v4.16b, v3.16b
200 ; CHECK-NEXT: bsl v0.16b, v18.16b, v16.16b
201 ; CHECK-NEXT: bsl v1.16b, v20.16b, v19.16b
202 ; CHECK-NEXT: bsl v2.16b, v22.16b, v21.16b
203 ; CHECK-NEXT: bsl v3.16b, v17.16b, v23.16b
204 ; CHECK-NEXT: ret
205 %z = call <32 x i16> @llvm.sadd.sat.v32i16(<32 x i16> %x, <32 x i16> %y)
206 ret <32 x i16> %z
207 }
209 define void @v8i8(<8 x i8>* %px, <8 x i8>* %py, <8 x i8>* %pz) nounwind {
210 ; CHECK-LABEL: v8i8:
211 ; CHECK: // %bb.0:
212 ; CHECK-NEXT: ldr d0, [x0]
213 ; CHECK-NEXT: ldr d1, [x1]
214 ; CHECK-NEXT: movi v2.8b, #127
215 ; CHECK-NEXT: add v3.8b, v0.8b, v1.8b
216 ; CHECK-NEXT: cmlt v4.8b, v3.8b, #0
217 ; CHECK-NEXT: cmlt v1.8b, v1.8b, #0
218 ; CHECK-NEXT: cmgt v0.8b, v0.8b, v3.8b
219 ; CHECK-NEXT: mvn v5.8b, v4.8b
220 ; CHECK-NEXT: bsl v2.8b, v4.8b, v5.8b
221 ; CHECK-NEXT: eor v0.8b, v1.8b, v0.8b
222 ; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b
223 ; CHECK-NEXT: str d0, [x2]
224 ; CHECK-NEXT: ret
225 %x = load <8 x i8>, <8 x i8>* %px
226 %y = load <8 x i8>, <8 x i8>* %py
227 %z = call <8 x i8> @llvm.sadd.sat.v8i8(<8 x i8> %x, <8 x i8> %y)
228 store <8 x i8> %z, <8 x i8>* %pz
229 ret void
230 }
232 define void @v4i8(<4 x i8>* %px, <4 x i8>* %py, <4 x i8>* %pz) nounwind {
233 ; CHECK-LABEL: v4i8:
234 ; CHECK: // %bb.0:
235 ; CHECK-NEXT: ldrsb w8, [x0]
236 ; CHECK-NEXT: ldrsb w9, [x1]
237 ; CHECK-NEXT: ldrsb w10, [x0, #1]
238 ; CHECK-NEXT: ldrsb w11, [x1, #1]
239 ; CHECK-NEXT: fmov s0, w8
240 ; CHECK-NEXT: fmov s1, w9
241 ; CHECK-NEXT: ldrsb w8, [x0, #2]
242 ; CHECK-NEXT: ldrsb w9, [x1, #2]
243 ; CHECK-NEXT: mov v0.h[1], w10
244 ; CHECK-NEXT: mov v1.h[1], w11
245 ; CHECK-NEXT: ldrsb w10, [x0, #3]
246 ; CHECK-NEXT: ldrsb w11, [x1, #3]
247 ; CHECK-NEXT: mov v0.h[2], w8
248 ; CHECK-NEXT: mov v1.h[2], w9
249 ; CHECK-NEXT: mov v0.h[3], w10
250 ; CHECK-NEXT: mov v1.h[3], w11
251 ; CHECK-NEXT: add v0.4h, v0.4h, v1.4h
252 ; CHECK-NEXT: movi v1.4h, #127
253 ; CHECK-NEXT: smin v0.4h, v0.4h, v1.4h
254 ; CHECK-NEXT: mvni v1.4h, #127
255 ; CHECK-NEXT: smax v0.4h, v0.4h, v1.4h
256 ; CHECK-NEXT: xtn v0.8b, v0.8h
257 ; CHECK-NEXT: str s0, [x2]
258 ; CHECK-NEXT: ret
259 %x = load <4 x i8>, <4 x i8>* %px
260 %y = load <4 x i8>, <4 x i8>* %py
261 %z = call <4 x i8> @llvm.sadd.sat.v4i8(<4 x i8> %x, <4 x i8> %y)
262 store <4 x i8> %z, <4 x i8>* %pz
263 ret void
264 }
266 define void @v2i8(<2 x i8>* %px, <2 x i8>* %py, <2 x i8>* %pz) nounwind {
267 ; CHECK-LABEL: v2i8:
268 ; CHECK: // %bb.0:
269 ; CHECK-NEXT: ldrsb w8, [x0]
270 ; CHECK-NEXT: ldrsb w9, [x1]
271 ; CHECK-NEXT: ldrsb w10, [x0, #1]
272 ; CHECK-NEXT: ldrsb w11, [x1, #1]
273 ; CHECK-NEXT: fmov s0, w8
274 ; CHECK-NEXT: fmov s1, w9
275 ; CHECK-NEXT: mov v0.s[1], w10
276 ; CHECK-NEXT: mov v1.s[1], w11
277 ; CHECK-NEXT: add v0.2s, v0.2s, v1.2s
278 ; CHECK-NEXT: movi v1.2s, #127
279 ; CHECK-NEXT: smin v0.2s, v0.2s, v1.2s
280 ; CHECK-NEXT: mvni v1.2s, #127
281 ; CHECK-NEXT: smax v0.2s, v0.2s, v1.2s
282 ; CHECK-NEXT: mov w8, v0.s[1]
283 ; CHECK-NEXT: fmov w9, s0
284 ; CHECK-NEXT: strb w8, [x2, #1]
285 ; CHECK-NEXT: strb w9, [x2]
286 ; CHECK-NEXT: ret
287 %x = load <2 x i8>, <2 x i8>* %px
288 %y = load <2 x i8>, <2 x i8>* %py
289 %z = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> %x, <2 x i8> %y)
290 store <2 x i8> %z, <2 x i8>* %pz
291 ret void
292 }
294 define void @v4i16(<4 x i16>* %px, <4 x i16>* %py, <4 x i16>* %pz) nounwind {
295 ; CHECK-LABEL: v4i16:
296 ; CHECK: // %bb.0:
297 ; CHECK-NEXT: ldr d0, [x0]
298 ; CHECK-NEXT: ldr d1, [x1]
299 ; CHECK-NEXT: mvni v2.4h, #128, lsl #8
300 ; CHECK-NEXT: add v3.4h, v0.4h, v1.4h
301 ; CHECK-NEXT: cmlt v4.4h, v3.4h, #0
302 ; CHECK-NEXT: cmlt v1.4h, v1.4h, #0
303 ; CHECK-NEXT: cmgt v0.4h, v0.4h, v3.4h
304 ; CHECK-NEXT: mvn v5.8b, v4.8b
305 ; CHECK-NEXT: bsl v2.8b, v4.8b, v5.8b
306 ; CHECK-NEXT: eor v0.8b, v1.8b, v0.8b
307 ; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b
308 ; CHECK-NEXT: str d0, [x2]
309 ; CHECK-NEXT: ret
310 %x = load <4 x i16>, <4 x i16>* %px
311 %y = load <4 x i16>, <4 x i16>* %py
312 %z = call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> %x, <4 x i16> %y)
313 store <4 x i16> %z, <4 x i16>* %pz
314 ret void
315 }
317 define void @v2i16(<2 x i16>* %px, <2 x i16>* %py, <2 x i16>* %pz) nounwind {
318 ; CHECK-LABEL: v2i16:
319 ; CHECK: // %bb.0:
320 ; CHECK-NEXT: ldrsh w8, [x0]
321 ; CHECK-NEXT: ldrsh w9, [x1]
322 ; CHECK-NEXT: ldrsh w10, [x0, #2]
323 ; CHECK-NEXT: ldrsh w11, [x1, #2]
324 ; CHECK-NEXT: fmov s0, w8
325 ; CHECK-NEXT: fmov s1, w9
326 ; CHECK-NEXT: mov v0.s[1], w10
327 ; CHECK-NEXT: mov v1.s[1], w11
328 ; CHECK-NEXT: add v0.2s, v0.2s, v1.2s
329 ; CHECK-NEXT: movi v1.2s, #127, msl #8
330 ; CHECK-NEXT: smin v0.2s, v0.2s, v1.2s
331 ; CHECK-NEXT: mvni v1.2s, #127, msl #8
332 ; CHECK-NEXT: smax v0.2s, v0.2s, v1.2s
333 ; CHECK-NEXT: mov w8, v0.s[1]
334 ; CHECK-NEXT: fmov w9, s0
335 ; CHECK-NEXT: strh w8, [x2, #2]
336 ; CHECK-NEXT: strh w9, [x2]
337 ; CHECK-NEXT: ret
338 %x = load <2 x i16>, <2 x i16>* %px
339 %y = load <2 x i16>, <2 x i16>* %py
340 %z = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %x, <2 x i16> %y)
341 store <2 x i16> %z, <2 x i16>* %pz
342 ret void
343 }
345 define <12 x i8> @v12i8(<12 x i8> %x, <12 x i8> %y) nounwind {
346 ; CHECK-LABEL: v12i8:
347 ; CHECK: // %bb.0:
348 ; CHECK-NEXT: add v2.16b, v0.16b, v1.16b
349 ; CHECK-NEXT: cmlt v4.16b, v2.16b, #0
350 ; CHECK-NEXT: movi v3.16b, #127
351 ; CHECK-NEXT: cmlt v1.16b, v1.16b, #0
352 ; CHECK-NEXT: cmgt v0.16b, v0.16b, v2.16b
353 ; CHECK-NEXT: mvn v5.16b, v4.16b
354 ; CHECK-NEXT: bsl v3.16b, v4.16b, v5.16b
355 ; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b
356 ; CHECK-NEXT: bsl v0.16b, v3.16b, v2.16b
357 ; CHECK-NEXT: ret
358 %z = call <12 x i8> @llvm.sadd.sat.v12i8(<12 x i8> %x, <12 x i8> %y)
359 ret <12 x i8> %z
360 }
362 define void @v12i16(<12 x i16>* %px, <12 x i16>* %py, <12 x i16>* %pz) nounwind {
363 ; CHECK-LABEL: v12i16:
364 ; CHECK: // %bb.0:
365 ; CHECK-NEXT: ldp q0, q1, [x0]
366 ; CHECK-NEXT: ldp q3, q2, [x1]
367 ; CHECK-NEXT: mvni v5.8h, #128, lsl #8
368 ; CHECK-NEXT: mvni v4.8h, #128, lsl #8
369 ; CHECK-NEXT: add v6.8h, v1.8h, v2.8h
370 ; CHECK-NEXT: cmlt v7.8h, v6.8h, #0
371 ; CHECK-NEXT: mvn v16.16b, v7.16b
372 ; CHECK-NEXT: bsl v5.16b, v7.16b, v16.16b
373 ; CHECK-NEXT: add v7.8h, v0.8h, v3.8h
374 ; CHECK-NEXT: cmlt v2.8h, v2.8h, #0
375 ; CHECK-NEXT: cmgt v1.8h, v1.8h, v6.8h
376 ; CHECK-NEXT: cmlt v16.8h, v7.8h, #0
377 ; CHECK-NEXT: cmlt v3.8h, v3.8h, #0
378 ; CHECK-NEXT: cmgt v0.8h, v0.8h, v7.8h
379 ; CHECK-NEXT: eor v1.16b, v2.16b, v1.16b
380 ; CHECK-NEXT: mvn v2.16b, v16.16b
381 ; CHECK-NEXT: eor v0.16b, v3.16b, v0.16b
382 ; CHECK-NEXT: bsl v4.16b, v16.16b, v2.16b
383 ; CHECK-NEXT: bsl v1.16b, v5.16b, v6.16b
384 ; CHECK-NEXT: bsl v0.16b, v4.16b, v7.16b
385 ; CHECK-NEXT: str q0, [x2]
386 ; CHECK-NEXT: str d1, [x2, #16]
387 ; CHECK-NEXT: ret
388 %x = load <12 x i16>, <12 x i16>* %px
389 %y = load <12 x i16>, <12 x i16>* %py
390 %z = call <12 x i16> @llvm.sadd.sat.v12i16(<12 x i16> %x, <12 x i16> %y)
391 store <12 x i16> %z, <12 x i16>* %pz
392 ret void
393 }
395 define void @v1i8(<1 x i8>* %px, <1 x i8>* %py, <1 x i8>* %pz) nounwind {
396 ; CHECK-LABEL: v1i8:
397 ; CHECK: // %bb.0:
398 ; CHECK-NEXT: ldr b0, [x0]
399 ; CHECK-NEXT: ldr b1, [x1]
400 ; CHECK-NEXT: movi v2.8b, #127
401 ; CHECK-NEXT: add v3.8b, v0.8b, v1.8b
402 ; CHECK-NEXT: cmlt v4.8b, v3.8b, #0
403 ; CHECK-NEXT: cmlt v1.8b, v1.8b, #0
404 ; CHECK-NEXT: cmgt v0.8b, v0.8b, v3.8b
405 ; CHECK-NEXT: mvn v5.8b, v4.8b
406 ; CHECK-NEXT: bsl v2.8b, v4.8b, v5.8b
407 ; CHECK-NEXT: eor v0.8b, v1.8b, v0.8b
408 ; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b
409 ; CHECK-NEXT: st1 { v0.b }[0], [x2]
410 ; CHECK-NEXT: ret
411 %x = load <1 x i8>, <1 x i8>* %px
412 %y = load <1 x i8>, <1 x i8>* %py
413 %z = call <1 x i8> @llvm.sadd.sat.v1i8(<1 x i8> %x, <1 x i8> %y)
414 store <1 x i8> %z, <1 x i8>* %pz
415 ret void
416 }
418 define void @v1i16(<1 x i16>* %px, <1 x i16>* %py, <1 x i16>* %pz) nounwind {
419 ; CHECK-LABEL: v1i16:
420 ; CHECK: // %bb.0:
421 ; CHECK-NEXT: ldr h0, [x0]
422 ; CHECK-NEXT: ldr h1, [x1]
423 ; CHECK-NEXT: mvni v2.4h, #128, lsl #8
424 ; CHECK-NEXT: add v3.4h, v0.4h, v1.4h
425 ; CHECK-NEXT: cmlt v4.4h, v3.4h, #0
426 ; CHECK-NEXT: cmlt v1.4h, v1.4h, #0
427 ; CHECK-NEXT: cmgt v0.4h, v0.4h, v3.4h
428 ; CHECK-NEXT: mvn v5.8b, v4.8b
429 ; CHECK-NEXT: bsl v2.8b, v4.8b, v5.8b
430 ; CHECK-NEXT: eor v0.8b, v1.8b, v0.8b
431 ; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b
432 ; CHECK-NEXT: str h0, [x2]
433 ; CHECK-NEXT: ret
434 %x = load <1 x i16>, <1 x i16>* %px
435 %y = load <1 x i16>, <1 x i16>* %py
436 %z = call <1 x i16> @llvm.sadd.sat.v1i16(<1 x i16> %x, <1 x i16> %y)
437 store <1 x i16> %z, <1 x i16>* %pz
438 ret void
439 }
441 define <16 x i4> @v16i4(<16 x i4> %x, <16 x i4> %y) nounwind {
442 ; CHECK-LABEL: v16i4:
443 ; CHECK: // %bb.0:
444 ; CHECK-NEXT: shl v0.16b, v0.16b, #4
445 ; CHECK-NEXT: shl v1.16b, v1.16b, #4
446 ; CHECK-NEXT: sshr v0.16b, v0.16b, #4
447 ; CHECK-NEXT: movi v2.16b, #7
448 ; CHECK-NEXT: ssra v0.16b, v1.16b, #4
449 ; CHECK-NEXT: smin v0.16b, v0.16b, v2.16b
450 ; CHECK-NEXT: movi v1.16b, #248
451 ; CHECK-NEXT: smax v0.16b, v0.16b, v1.16b
452 ; CHECK-NEXT: ret
453 %z = call <16 x i4> @llvm.sadd.sat.v16i4(<16 x i4> %x, <16 x i4> %y)
454 ret <16 x i4> %z
455 }
457 define <16 x i1> @v16i1(<16 x i1> %x, <16 x i1> %y) nounwind {
458 ; CHECK-LABEL: v16i1:
459 ; CHECK: // %bb.0:
460 ; CHECK-NEXT: shl v0.16b, v0.16b, #7
461 ; CHECK-NEXT: shl v1.16b, v1.16b, #7
462 ; CHECK-NEXT: sshr v0.16b, v0.16b, #7
463 ; CHECK-NEXT: movi v2.2d, #0000000000000000
464 ; CHECK-NEXT: ssra v0.16b, v1.16b, #7
465 ; CHECK-NEXT: smin v0.16b, v0.16b, v2.16b
466 ; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff
467 ; CHECK-NEXT: smax v0.16b, v0.16b, v1.16b
468 ; CHECK-NEXT: ret
469 %z = call <16 x i1> @llvm.sadd.sat.v16i1(<16 x i1> %x, <16 x i1> %y)
470 ret <16 x i1> %z
471 }
473 define <2 x i32> @v2i32(<2 x i32> %x, <2 x i32> %y) nounwind {
474 ; CHECK-LABEL: v2i32:
475 ; CHECK: // %bb.0:
476 ; CHECK-NEXT: add v2.2s, v0.2s, v1.2s
477 ; CHECK-NEXT: cmlt v4.2s, v2.2s, #0
478 ; CHECK-NEXT: mvni v3.2s, #128, lsl #24
479 ; CHECK-NEXT: cmlt v1.2s, v1.2s, #0
480 ; CHECK-NEXT: cmgt v0.2s, v0.2s, v2.2s
481 ; CHECK-NEXT: mvn v5.8b, v4.8b
482 ; CHECK-NEXT: bsl v3.8b, v4.8b, v5.8b
483 ; CHECK-NEXT: eor v0.8b, v1.8b, v0.8b
484 ; CHECK-NEXT: bsl v0.8b, v3.8b, v2.8b
485 ; CHECK-NEXT: ret
486 %z = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> %x, <2 x i32> %y)
487 ret <2 x i32> %z
488 }
490 define <4 x i32> @v4i32(<4 x i32> %x, <4 x i32> %y) nounwind {
491 ; CHECK-LABEL: v4i32:
492 ; CHECK: // %bb.0:
493 ; CHECK-NEXT: add v2.4s, v0.4s, v1.4s
494 ; CHECK-NEXT: cmlt v4.4s, v2.4s, #0
495 ; CHECK-NEXT: mvni v3.4s, #128, lsl #24
496 ; CHECK-NEXT: cmlt v1.4s, v1.4s, #0
497 ; CHECK-NEXT: cmgt v0.4s, v0.4s, v2.4s
498 ; CHECK-NEXT: mvn v5.16b, v4.16b
499 ; CHECK-NEXT: bsl v3.16b, v4.16b, v5.16b
500 ; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b
501 ; CHECK-NEXT: bsl v0.16b, v3.16b, v2.16b
502 ; CHECK-NEXT: ret
503 %z = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %x, <4 x i32> %y)
504 ret <4 x i32> %z
505 }
507 define <8 x i32> @v8i32(<8 x i32> %x, <8 x i32> %y) nounwind {
508 ; CHECK-LABEL: v8i32:
509 ; CHECK: // %bb.0:
510 ; CHECK-NEXT: add v4.4s, v0.4s, v2.4s
511 ; CHECK-NEXT: cmlt v7.4s, v4.4s, #0
512 ; CHECK-NEXT: mvni v6.4s, #128, lsl #24
513 ; CHECK-NEXT: mvn v16.16b, v7.16b
514 ; CHECK-NEXT: bsl v6.16b, v7.16b, v16.16b
515 ; CHECK-NEXT: add v7.4s, v1.4s, v3.4s
516 ; CHECK-NEXT: cmlt v2.4s, v2.4s, #0
517 ; CHECK-NEXT: cmgt v0.4s, v0.4s, v4.4s
518 ; CHECK-NEXT: cmlt v16.4s, v7.4s, #0
519 ; CHECK-NEXT: mvni v5.4s, #128, lsl #24
520 ; CHECK-NEXT: cmlt v3.4s, v3.4s, #0
521 ; CHECK-NEXT: cmgt v1.4s, v1.4s, v7.4s
522 ; CHECK-NEXT: eor v0.16b, v2.16b, v0.16b
523 ; CHECK-NEXT: mvn v2.16b, v16.16b
524 ; CHECK-NEXT: eor v1.16b, v3.16b, v1.16b
525 ; CHECK-NEXT: bsl v5.16b, v16.16b, v2.16b
526 ; CHECK-NEXT: bsl v0.16b, v6.16b, v4.16b
527 ; CHECK-NEXT: bsl v1.16b, v5.16b, v7.16b
528 ; CHECK-NEXT: ret
529 %z = call <8 x i32> @llvm.sadd.sat.v8i32(<8 x i32> %x, <8 x i32> %y)
530 ret <8 x i32> %z
531 }
533 define <16 x i32> @v16i32(<16 x i32> %x, <16 x i32> %y) nounwind {
534 ; CHECK-LABEL: v16i32:
535 ; CHECK: // %bb.0:
536 ; CHECK-NEXT: add v16.4s, v0.4s, v4.4s
537 ; CHECK-NEXT: cmlt v24.4s, v16.4s, #0
538 ; CHECK-NEXT: mvni v18.4s, #128, lsl #24
539 ; CHECK-NEXT: add v19.4s, v1.4s, v5.4s
540 ; CHECK-NEXT: mvn v25.16b, v24.16b
541 ; CHECK-NEXT: bsl v18.16b, v24.16b, v25.16b
542 ; CHECK-NEXT: cmlt v24.4s, v19.4s, #0
543 ; CHECK-NEXT: mvni v20.4s, #128, lsl #24
544 ; CHECK-NEXT: add v21.4s, v2.4s, v6.4s
545 ; CHECK-NEXT: mvn v25.16b, v24.16b
546 ; CHECK-NEXT: bsl v20.16b, v24.16b, v25.16b
547 ; CHECK-NEXT: cmlt v24.4s, v21.4s, #0
548 ; CHECK-NEXT: cmlt v4.4s, v4.4s, #0
549 ; CHECK-NEXT: cmgt v0.4s, v0.4s, v16.4s
550 ; CHECK-NEXT: mvni v22.4s, #128, lsl #24
551 ; CHECK-NEXT: add v23.4s, v3.4s, v7.4s
552 ; CHECK-NEXT: mvn v25.16b, v24.16b
553 ; CHECK-NEXT: eor v0.16b, v4.16b, v0.16b
554 ; CHECK-NEXT: cmlt v4.4s, v5.4s, #0
555 ; CHECK-NEXT: cmgt v1.4s, v1.4s, v19.4s
556 ; CHECK-NEXT: bsl v22.16b, v24.16b, v25.16b
557 ; CHECK-NEXT: cmlt v24.4s, v23.4s, #0
558 ; CHECK-NEXT: eor v1.16b, v4.16b, v1.16b
559 ; CHECK-NEXT: cmlt v4.4s, v6.4s, #0
560 ; CHECK-NEXT: cmgt v2.4s, v2.4s, v21.4s
561 ; CHECK-NEXT: mvni v17.4s, #128, lsl #24
562 ; CHECK-NEXT: mvn v25.16b, v24.16b
563 ; CHECK-NEXT: eor v2.16b, v4.16b, v2.16b
564 ; CHECK-NEXT: cmlt v4.4s, v7.4s, #0
565 ; CHECK-NEXT: cmgt v3.4s, v3.4s, v23.4s
566 ; CHECK-NEXT: bsl v17.16b, v24.16b, v25.16b
567 ; CHECK-NEXT: eor v3.16b, v4.16b, v3.16b
568 ; CHECK-NEXT: bsl v0.16b, v18.16b, v16.16b
569 ; CHECK-NEXT: bsl v1.16b, v20.16b, v19.16b
570 ; CHECK-NEXT: bsl v2.16b, v22.16b, v21.16b
571 ; CHECK-NEXT: bsl v3.16b, v17.16b, v23.16b
572 ; CHECK-NEXT: ret
573 %z = call <16 x i32> @llvm.sadd.sat.v16i32(<16 x i32> %x, <16 x i32> %y)
574 ret <16 x i32> %z
575 }
577 define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
578 ; CHECK-LABEL: v2i64:
579 ; CHECK: // %bb.0:
580 ; CHECK-NEXT: add v2.2d, v0.2d, v1.2d
581 ; CHECK-NEXT: mov x8, #9223372036854775807
582 ; CHECK-NEXT: cmlt v3.2d, v2.2d, #0
583 ; CHECK-NEXT: cmlt v1.2d, v1.2d, #0
584 ; CHECK-NEXT: dup v4.2d, x8
585 ; CHECK-NEXT: cmgt v0.2d, v0.2d, v2.2d
586 ; CHECK-NEXT: mvn v5.16b, v3.16b
587 ; CHECK-NEXT: bsl v4.16b, v3.16b, v5.16b
588 ; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b
589 ; CHECK-NEXT: bsl v0.16b, v4.16b, v2.16b
590 ; CHECK-NEXT: ret
591 %z = call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> %x, <2 x i64> %y)
592 ret <2 x i64> %z
593 }
595 define <4 x i64> @v4i64(<4 x i64> %x, <4 x i64> %y) nounwind {
596 ; CHECK-LABEL: v4i64:
597 ; CHECK: // %bb.0:
598 ; CHECK-NEXT: add v4.2d, v0.2d, v2.2d
599 ; CHECK-NEXT: mov x8, #9223372036854775807
600 ; CHECK-NEXT: cmlt v5.2d, v4.2d, #0
601 ; CHECK-NEXT: dup v6.2d, x8
602 ; CHECK-NEXT: mvn v7.16b, v5.16b
603 ; CHECK-NEXT: mov v16.16b, v6.16b
604 ; CHECK-NEXT: bsl v16.16b, v5.16b, v7.16b
605 ; CHECK-NEXT: add v5.2d, v1.2d, v3.2d
606 ; CHECK-NEXT: cmlt v2.2d, v2.2d, #0
607 ; CHECK-NEXT: cmgt v0.2d, v0.2d, v4.2d
608 ; CHECK-NEXT: cmlt v7.2d, v5.2d, #0
609 ; CHECK-NEXT: cmlt v3.2d, v3.2d, #0
610 ; CHECK-NEXT: cmgt v1.2d, v1.2d, v5.2d
611 ; CHECK-NEXT: eor v0.16b, v2.16b, v0.16b
612 ; CHECK-NEXT: mvn v2.16b, v7.16b
613 ; CHECK-NEXT: eor v1.16b, v3.16b, v1.16b
614 ; CHECK-NEXT: bsl v6.16b, v7.16b, v2.16b
615 ; CHECK-NEXT: bsl v0.16b, v16.16b, v4.16b
616 ; CHECK-NEXT: bsl v1.16b, v6.16b, v5.16b
617 ; CHECK-NEXT: ret
618 %z = call <4 x i64> @llvm.sadd.sat.v4i64(<4 x i64> %x, <4 x i64> %y)
619 ret <4 x i64> %z
620 }
622 define <8 x i64> @v8i64(<8 x i64> %x, <8 x i64> %y) nounwind {
623 ; CHECK-LABEL: v8i64:
624 ; CHECK: // %bb.0:
625 ; CHECK-NEXT: add v16.2d, v0.2d, v4.2d
626 ; CHECK-NEXT: mov x8, #9223372036854775807
627 ; CHECK-NEXT: add v17.2d, v1.2d, v5.2d
628 ; CHECK-NEXT: cmlt v20.2d, v16.2d, #0
629 ; CHECK-NEXT: dup v21.2d, x8
630 ; CHECK-NEXT: add v18.2d, v2.2d, v6.2d
631 ; CHECK-NEXT: cmlt v22.2d, v17.2d, #0
632 ; CHECK-NEXT: mvn v24.16b, v20.16b
633 ; CHECK-NEXT: mov v25.16b, v21.16b
634 ; CHECK-NEXT: cmlt v23.2d, v18.2d, #0
635 ; CHECK-NEXT: bsl v25.16b, v20.16b, v24.16b
636 ; CHECK-NEXT: mvn v20.16b, v22.16b
637 ; CHECK-NEXT: mov v24.16b, v21.16b
638 ; CHECK-NEXT: cmlt v4.2d, v4.2d, #0
639 ; CHECK-NEXT: cmgt v0.2d, v0.2d, v16.2d
640 ; CHECK-NEXT: add v19.2d, v3.2d, v7.2d
641 ; CHECK-NEXT: bsl v24.16b, v22.16b, v20.16b
642 ; CHECK-NEXT: mvn v20.16b, v23.16b
643 ; CHECK-NEXT: mov v22.16b, v21.16b
644 ; CHECK-NEXT: eor v0.16b, v4.16b, v0.16b
645 ; CHECK-NEXT: cmlt v4.2d, v5.2d, #0
646 ; CHECK-NEXT: cmgt v1.2d, v1.2d, v17.2d
647 ; CHECK-NEXT: bsl v22.16b, v23.16b, v20.16b
648 ; CHECK-NEXT: cmlt v20.2d, v19.2d, #0
649 ; CHECK-NEXT: eor v1.16b, v4.16b, v1.16b
650 ; CHECK-NEXT: cmlt v4.2d, v6.2d, #0
651 ; CHECK-NEXT: cmgt v2.2d, v2.2d, v18.2d
652 ; CHECK-NEXT: mvn v23.16b, v20.16b
653 ; CHECK-NEXT: eor v2.16b, v4.16b, v2.16b
654 ; CHECK-NEXT: cmlt v4.2d, v7.2d, #0
655 ; CHECK-NEXT: cmgt v3.2d, v3.2d, v19.2d
656 ; CHECK-NEXT: bsl v21.16b, v20.16b, v23.16b
657 ; CHECK-NEXT: eor v3.16b, v4.16b, v3.16b
658 ; CHECK-NEXT: bsl v0.16b, v25.16b, v16.16b
659 ; CHECK-NEXT: bsl v1.16b, v24.16b, v17.16b
660 ; CHECK-NEXT: bsl v2.16b, v22.16b, v18.16b
661 ; CHECK-NEXT: bsl v3.16b, v21.16b, v19.16b
662 ; CHECK-NEXT: ret
663 %z = call <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64> %x, <8 x i64> %y)
664 ret <8 x i64> %z
665 }
667 define <2 x i128> @v2i128(<2 x i128> %x, <2 x i128> %y) nounwind {
668 ; CHECK-LABEL: v2i128:
669 ; CHECK: // %bb.0:
670 ; CHECK-NEXT: cmp x7, #0 // =0
671 ; CHECK-NEXT: cset w9, ge
672 ; CHECK-NEXT: csinc w9, w9, wzr, ne
673 ; CHECK-NEXT: cmp x3, #0 // =0
674 ; CHECK-NEXT: cset w10, ge
675 ; CHECK-NEXT: csinc w10, w10, wzr, ne
676 ; CHECK-NEXT: cmp w10, w9
677 ; CHECK-NEXT: cset w9, eq
678 ; CHECK-NEXT: adds x11, x2, x6
679 ; CHECK-NEXT: adcs x12, x3, x7
680 ; CHECK-NEXT: cmp x12, #0 // =0
681 ; CHECK-NEXT: cset w13, ge
682 ; CHECK-NEXT: mov x8, #9223372036854775807
683 ; CHECK-NEXT: csinc w13, w13, wzr, ne
684 ; CHECK-NEXT: cinv x14, x8, ge
685 ; CHECK-NEXT: cmp w10, w13
686 ; CHECK-NEXT: cset w13, ne
687 ; CHECK-NEXT: asr x10, x12, #63
688 ; CHECK-NEXT: tst w9, w13
689 ; CHECK-NEXT: csel x3, x14, x12, ne
690 ; CHECK-NEXT: csel x2, x10, x11, ne
691 ; CHECK-NEXT: cmp x5, #0 // =0
692 ; CHECK-NEXT: cset w9, ge
693 ; CHECK-NEXT: csinc w9, w9, wzr, ne
694 ; CHECK-NEXT: cmp x1, #0 // =0
695 ; CHECK-NEXT: cset w10, ge
696 ; CHECK-NEXT: csinc w10, w10, wzr, ne
697 ; CHECK-NEXT: cmp w10, w9
698 ; CHECK-NEXT: cset w9, eq
699 ; CHECK-NEXT: adds x11, x0, x4
700 ; CHECK-NEXT: adcs x12, x1, x5
701 ; CHECK-NEXT: cmp x12, #0 // =0
702 ; CHECK-NEXT: cset w13, ge
703 ; CHECK-NEXT: csinc w13, w13, wzr, ne
704 ; CHECK-NEXT: cinv x8, x8, ge
705 ; CHECK-NEXT: cmp w10, w13
706 ; CHECK-NEXT: cset w10, ne
707 ; CHECK-NEXT: tst w9, w10
708 ; CHECK-NEXT: asr x9, x12, #63
709 ; CHECK-NEXT: csel x9, x9, x11, ne
710 ; CHECK-NEXT: csel x1, x8, x12, ne
711 ; CHECK-NEXT: fmov d0, x9
712 ; CHECK-NEXT: mov v0.d[1], x1
713 ; CHECK-NEXT: fmov x0, d0
714 ; CHECK-NEXT: ret
715 %z = call <2 x i128> @llvm.sadd.sat.v2i128(<2 x i128> %x, <2 x i128> %y)
716 ret <2 x i128> %z
717 }