1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=aarch64-unknown-unknown -O3 -verify-machineinstrs < %s | FileCheck %s
4 ; Test cases are generated from:
5 ; long long NAME(PARAM a, PARAM b) {
12 ; Please note funtion name is defined as <PARAM>_<LHS>_<RHS>. Take ll_a_op_b__1
13 ; for example. ll is PARAM, a_op_b (i.e., a << b) is LHS, _1 (i.e., -1) is RHS.
15 target datalayout = "e-m:e-i64:64-n32:64"
17 define i64 @ll_a_op_b__2(i64 %a, i64 %b) {
18 ; CHECK-LABEL: ll_a_op_b__2:
19 ; CHECK: // %bb.0: // %entry
20 ; CHECK-NEXT: lsl x8, x0, x1
21 ; CHECK-NEXT: cmn x8, #2 // =2
22 ; CHECK-NEXT: b.le .LBB0_2
23 ; CHECK-NEXT: // %bb.1: // %return
24 ; CHECK-NEXT: mov x0, x1
26 ; CHECK-NEXT: .LBB0_2: // %if.end
27 ; CHECK-NEXT: csinc x8, x1, xzr, eq
28 ; CHECK-NEXT: mul x0, x8, x0
32 %cmp = icmp sgt i64 %shl, -2
33 br i1 %cmp, label %return, label %if.end
35 if.end: ; preds = %entry
36 %cmp2 = icmp eq i64 %shl, -2
37 %mul = select i1 %cmp2, i64 %b, i64 1
38 %spec.select = mul nsw i64 %mul, %a
41 return: ; preds = %entry
45 define i64 @ll_a_op_b__1(i64 %a, i64 %b) {
46 ; CHECK-LABEL: ll_a_op_b__1:
47 ; CHECK: // %bb.0: // %entry
48 ; CHECK-NEXT: lsl x8, x0, x1
49 ; CHECK-NEXT: tbnz x8, #63, .LBB1_2
50 ; CHECK-NEXT: // %bb.1: // %return
51 ; CHECK-NEXT: mov x0, x1
53 ; CHECK-NEXT: .LBB1_2: // %if.end
54 ; CHECK-NEXT: cmn x8, #1 // =1
55 ; CHECK-NEXT: csinc x8, x1, xzr, eq
56 ; CHECK-NEXT: mul x0, x8, x0
60 %cmp = icmp sgt i64 %shl, -1
61 br i1 %cmp, label %return, label %if.end
63 if.end: ; preds = %entry
64 %cmp2 = icmp eq i64 %shl, -1
65 %mul = select i1 %cmp2, i64 %b, i64 1
66 %spec.select = mul nsw i64 %mul, %a
69 return: ; preds = %entry
73 define i64 @ll_a_op_b_0(i64 %a, i64 %b) {
74 ; CHECK-LABEL: ll_a_op_b_0:
75 ; CHECK: // %bb.0: // %entry
76 ; CHECK-NEXT: lsl x8, x0, x1
77 ; CHECK-NEXT: cmp x8, #0 // =0
78 ; CHECK-NEXT: b.le .LBB2_2
79 ; CHECK-NEXT: // %bb.1: // %return
80 ; CHECK-NEXT: mov x0, x1
82 ; CHECK-NEXT: .LBB2_2: // %if.end
83 ; CHECK-NEXT: csinc x8, x1, xzr, eq
84 ; CHECK-NEXT: mul x0, x8, x0
88 %cmp = icmp sgt i64 %shl, 0
89 br i1 %cmp, label %return, label %if.end
91 if.end: ; preds = %entry
92 %cmp2 = icmp eq i64 %shl, 0
93 %mul = select i1 %cmp2, i64 %b, i64 1
94 %spec.select = mul nsw i64 %mul, %a
97 return: ; preds = %entry
101 define i64 @ll_a_op_b_1(i64 %a, i64 %b) {
102 ; CHECK-LABEL: ll_a_op_b_1:
103 ; CHECK: // %bb.0: // %entry
104 ; CHECK-NEXT: lsl x8, x0, x1
105 ; CHECK-NEXT: cmp x8, #1 // =1
106 ; CHECK-NEXT: b.le .LBB3_2
107 ; CHECK-NEXT: // %bb.1: // %return
108 ; CHECK-NEXT: mov x0, x1
110 ; CHECK-NEXT: .LBB3_2: // %if.end
111 ; CHECK-NEXT: csinc x8, x1, xzr, eq
112 ; CHECK-NEXT: mul x0, x8, x0
115 %shl = shl i64 %a, %b
116 %cmp = icmp sgt i64 %shl, 1
117 br i1 %cmp, label %return, label %if.end
119 if.end: ; preds = %entry
120 %cmp2 = icmp eq i64 %shl, 1
121 %mul = select i1 %cmp2, i64 %b, i64 1
122 %spec.select = mul nsw i64 %mul, %a
125 return: ; preds = %entry
129 define i64 @ll_a_op_b_2(i64 %a, i64 %b) {
130 ; CHECK-LABEL: ll_a_op_b_2:
131 ; CHECK: // %bb.0: // %entry
132 ; CHECK-NEXT: lsl x8, x0, x1
133 ; CHECK-NEXT: cmp x8, #2 // =2
134 ; CHECK-NEXT: b.le .LBB4_2
135 ; CHECK-NEXT: // %bb.1: // %return
136 ; CHECK-NEXT: mov x0, x1
138 ; CHECK-NEXT: .LBB4_2: // %if.end
139 ; CHECK-NEXT: csinc x8, x1, xzr, eq
140 ; CHECK-NEXT: mul x0, x8, x0
143 %shl = shl i64 %a, %b
144 %cmp = icmp sgt i64 %shl, 2
145 br i1 %cmp, label %return, label %if.end
147 if.end: ; preds = %entry
148 %cmp2 = icmp eq i64 %shl, 2
149 %mul = select i1 %cmp2, i64 %b, i64 1
150 %spec.select = mul nsw i64 %mul, %a
153 return: ; preds = %entry
157 define i64 @ll_a__2(i64 %a, i64 %b) {
158 ; CHECK-LABEL: ll_a__2:
159 ; CHECK: // %bb.0: // %entry
160 ; CHECK-NEXT: cmn x0, #2 // =2
161 ; CHECK-NEXT: b.le .LBB5_2
162 ; CHECK-NEXT: // %bb.1: // %return
163 ; CHECK-NEXT: mov x0, x1
165 ; CHECK-NEXT: .LBB5_2: // %if.end
166 ; CHECK-NEXT: csinc x8, x1, xzr, eq
167 ; CHECK-NEXT: mul x0, x8, x0
170 %cmp = icmp sgt i64 %a, -2
171 br i1 %cmp, label %return, label %if.end
173 if.end: ; preds = %entry
174 %cmp1 = icmp eq i64 %a, -2
175 %mul = select i1 %cmp1, i64 %b, i64 1
176 %spec.select = mul nsw i64 %mul, %a
179 return: ; preds = %entry
183 define i64 @ll_a__1(i64 %a, i64 %b) {
184 ; CHECK-LABEL: ll_a__1:
185 ; CHECK: // %bb.0: // %entry
186 ; CHECK-NEXT: tbnz x0, #63, .LBB6_2
187 ; CHECK-NEXT: // %bb.1: // %return
188 ; CHECK-NEXT: mov x0, x1
190 ; CHECK-NEXT: .LBB6_2: // %if.end
191 ; CHECK-NEXT: cmn x0, #1 // =1
192 ; CHECK-NEXT: csinc x8, x1, xzr, eq
193 ; CHECK-NEXT: mul x0, x8, x0
196 %cmp = icmp sgt i64 %a, -1
197 br i1 %cmp, label %return, label %if.end
199 if.end: ; preds = %entry
200 %cmp1 = icmp eq i64 %a, -1
201 %mul = select i1 %cmp1, i64 %b, i64 1
202 %spec.select = mul nsw i64 %mul, %a
205 return: ; preds = %entry
209 define i64 @ll_a_0(i64 %a, i64 %b) {
210 ; CHECK-LABEL: ll_a_0:
211 ; CHECK: // %bb.0: // %entry
212 ; CHECK-NEXT: cmp x0, #0 // =0
213 ; CHECK-NEXT: b.le .LBB7_2
214 ; CHECK-NEXT: // %bb.1: // %return
215 ; CHECK-NEXT: mov x0, x1
217 ; CHECK-NEXT: .LBB7_2: // %if.end
218 ; CHECK-NEXT: csinc x8, x1, xzr, eq
219 ; CHECK-NEXT: mul x0, x8, x0
222 %cmp = icmp sgt i64 %a, 0
223 br i1 %cmp, label %return, label %if.end
225 if.end: ; preds = %entry
226 %cmp1 = icmp eq i64 %a, 0
227 %mul = select i1 %cmp1, i64 %b, i64 1
228 %spec.select = mul nsw i64 %mul, %a
231 return: ; preds = %entry
235 define i64 @ll_a_1(i64 %a, i64 %b) {
236 ; CHECK-LABEL: ll_a_1:
237 ; CHECK: // %bb.0: // %entry
238 ; CHECK-NEXT: cmp x0, #1 // =1
239 ; CHECK-NEXT: b.le .LBB8_2
240 ; CHECK-NEXT: // %bb.1: // %return
241 ; CHECK-NEXT: mov x0, x1
243 ; CHECK-NEXT: .LBB8_2: // %if.end
244 ; CHECK-NEXT: csinc x8, x1, xzr, eq
245 ; CHECK-NEXT: mul x0, x8, x0
248 %cmp = icmp sgt i64 %a, 1
249 br i1 %cmp, label %return, label %if.end
251 if.end: ; preds = %entry
252 %cmp1 = icmp eq i64 %a, 1
253 %mul = select i1 %cmp1, i64 %b, i64 1
254 %spec.select = mul nsw i64 %mul, %a
257 return: ; preds = %entry
261 define i64 @ll_a_2(i64 %a, i64 %b) {
262 ; CHECK-LABEL: ll_a_2:
263 ; CHECK: // %bb.0: // %entry
264 ; CHECK-NEXT: cmp x0, #2 // =2
265 ; CHECK-NEXT: b.le .LBB9_2
266 ; CHECK-NEXT: // %bb.1: // %return
267 ; CHECK-NEXT: mov x0, x1
269 ; CHECK-NEXT: .LBB9_2: // %if.end
270 ; CHECK-NEXT: csinc x8, x1, xzr, eq
271 ; CHECK-NEXT: mul x0, x8, x0
274 %cmp = icmp sgt i64 %a, 2
275 br i1 %cmp, label %return, label %if.end
277 if.end: ; preds = %entry
278 %cmp1 = icmp eq i64 %a, 2
279 %mul = select i1 %cmp1, i64 %b, i64 1
280 %spec.select = mul nsw i64 %mul, %a
283 return: ; preds = %entry
287 define i64 @i_a_op_b__2(i32 signext %a, i32 signext %b) {
288 ; CHECK-LABEL: i_a_op_b__2:
289 ; CHECK: // %bb.0: // %entry
290 ; CHECK-NEXT: lsl w8, w0, w1
291 ; CHECK-NEXT: cmn w8, #2 // =2
292 ; CHECK-NEXT: csinc w8, w1, wzr, eq
293 ; CHECK-NEXT: mul w8, w8, w0
294 ; CHECK-NEXT: csel w8, w1, w8, gt
295 ; CHECK-NEXT: sxtw x0, w8
298 %shl = shl i32 %a, %b
299 %cmp = icmp sgt i32 %shl, -2
300 br i1 %cmp, label %return, label %if.end
302 if.end: ; preds = %entry
303 %cmp2 = icmp eq i32 %shl, -2
304 %mul = select i1 %cmp2, i32 %b, i32 1
305 %spec.select = mul nsw i32 %mul, %a
308 return: ; preds = %if.end, %entry
309 %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
310 %retval.0 = sext i32 %retval.0.in to i64
314 define i64 @i_a_op_b__1(i32 signext %a, i32 signext %b) {
315 ; CHECK-LABEL: i_a_op_b__1:
316 ; CHECK: // %bb.0: // %entry
317 ; CHECK-NEXT: lsl w8, w0, w1
318 ; CHECK-NEXT: cmn w8, #1 // =1
319 ; CHECK-NEXT: csinc w9, w1, wzr, eq
320 ; CHECK-NEXT: mul w9, w9, w0
321 ; CHECK-NEXT: cmp w8, #0 // =0
322 ; CHECK-NEXT: csel w8, w1, w9, ge
323 ; CHECK-NEXT: sxtw x0, w8
326 %shl = shl i32 %a, %b
327 %cmp = icmp sgt i32 %shl, -1
328 br i1 %cmp, label %return, label %if.end
330 if.end: ; preds = %entry
331 %cmp2 = icmp eq i32 %shl, -1
332 %mul = select i1 %cmp2, i32 %b, i32 1
333 %spec.select = mul nsw i32 %mul, %a
336 return: ; preds = %if.end, %entry
337 %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
338 %retval.0 = sext i32 %retval.0.in to i64
342 define i64 @i_a_op_b_0(i32 signext %a, i32 signext %b) {
343 ; CHECK-LABEL: i_a_op_b_0:
344 ; CHECK: // %bb.0: // %entry
345 ; CHECK-NEXT: lsl w8, w0, w1
346 ; CHECK-NEXT: cmp w8, #0 // =0
347 ; CHECK-NEXT: csinc w8, w1, wzr, eq
348 ; CHECK-NEXT: mul w8, w8, w0
349 ; CHECK-NEXT: csel w8, w1, w8, gt
350 ; CHECK-NEXT: sxtw x0, w8
353 %shl = shl i32 %a, %b
354 %cmp = icmp sgt i32 %shl, 0
355 br i1 %cmp, label %return, label %if.end
357 if.end: ; preds = %entry
358 %cmp2 = icmp eq i32 %shl, 0
359 %mul = select i1 %cmp2, i32 %b, i32 1
360 %spec.select = mul nsw i32 %mul, %a
363 return: ; preds = %if.end, %entry
364 %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
365 %retval.0 = sext i32 %retval.0.in to i64
369 define i64 @i_a_op_b_1(i32 signext %a, i32 signext %b) {
370 ; CHECK-LABEL: i_a_op_b_1:
371 ; CHECK: // %bb.0: // %entry
372 ; CHECK-NEXT: lsl w8, w0, w1
373 ; CHECK-NEXT: cmp w8, #1 // =1
374 ; CHECK-NEXT: csinc w8, w1, wzr, eq
375 ; CHECK-NEXT: mul w8, w8, w0
376 ; CHECK-NEXT: csel w8, w1, w8, gt
377 ; CHECK-NEXT: sxtw x0, w8
380 %shl = shl i32 %a, %b
381 %cmp = icmp sgt i32 %shl, 1
382 br i1 %cmp, label %return, label %if.end
384 if.end: ; preds = %entry
385 %cmp2 = icmp eq i32 %shl, 1
386 %mul = select i1 %cmp2, i32 %b, i32 1
387 %spec.select = mul nsw i32 %mul, %a
390 return: ; preds = %if.end, %entry
391 %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
392 %retval.0 = sext i32 %retval.0.in to i64
396 define i64 @i_a_op_b_2(i32 signext %a, i32 signext %b) {
397 ; CHECK-LABEL: i_a_op_b_2:
398 ; CHECK: // %bb.0: // %entry
399 ; CHECK-NEXT: lsl w8, w0, w1
400 ; CHECK-NEXT: cmp w8, #2 // =2
401 ; CHECK-NEXT: csinc w8, w1, wzr, eq
402 ; CHECK-NEXT: mul w8, w8, w0
403 ; CHECK-NEXT: csel w8, w1, w8, gt
404 ; CHECK-NEXT: sxtw x0, w8
407 %shl = shl i32 %a, %b
408 %cmp = icmp sgt i32 %shl, 2
409 br i1 %cmp, label %return, label %if.end
411 if.end: ; preds = %entry
412 %cmp2 = icmp eq i32 %shl, 2
413 %mul = select i1 %cmp2, i32 %b, i32 1
414 %spec.select = mul nsw i32 %mul, %a
417 return: ; preds = %if.end, %entry
418 %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
419 %retval.0 = sext i32 %retval.0.in to i64
423 define i64 @i_a__2(i32 signext %a, i32 signext %b) {
424 ; CHECK-LABEL: i_a__2:
425 ; CHECK: // %bb.0: // %entry
426 ; CHECK-NEXT: cmn w0, #2 // =2
427 ; CHECK-NEXT: csinc w8, w1, wzr, eq
428 ; CHECK-NEXT: mul w8, w8, w0
429 ; CHECK-NEXT: csel w8, w1, w8, gt
430 ; CHECK-NEXT: sxtw x0, w8
433 %cmp = icmp sgt i32 %a, -2
434 br i1 %cmp, label %return, label %if.end
436 if.end: ; preds = %entry
437 %cmp1 = icmp eq i32 %a, -2
438 %mul = select i1 %cmp1, i32 %b, i32 1
439 %spec.select = mul nsw i32 %mul, %a
442 return: ; preds = %if.end, %entry
443 %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
444 %retval.0 = sext i32 %retval.0.in to i64
448 define i64 @i_a__1(i32 signext %a, i32 signext %b) {
449 ; CHECK-LABEL: i_a__1:
450 ; CHECK: // %bb.0: // %entry
451 ; CHECK-NEXT: cmn w0, #1 // =1
452 ; CHECK-NEXT: csinc w8, w1, wzr, eq
453 ; CHECK-NEXT: mul w8, w8, w0
454 ; CHECK-NEXT: cmp w0, #0 // =0
455 ; CHECK-NEXT: csel w8, w1, w8, ge
456 ; CHECK-NEXT: sxtw x0, w8
459 %cmp = icmp sgt i32 %a, -1
460 br i1 %cmp, label %return, label %if.end
462 if.end: ; preds = %entry
463 %cmp1 = icmp eq i32 %a, -1
464 %mul = select i1 %cmp1, i32 %b, i32 1
465 %spec.select = mul nsw i32 %mul, %a
468 return: ; preds = %if.end, %entry
469 %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
470 %retval.0 = sext i32 %retval.0.in to i64
474 define i64 @i_a_0(i32 signext %a, i32 signext %b) {
475 ; CHECK-LABEL: i_a_0:
476 ; CHECK: // %bb.0: // %entry
477 ; CHECK-NEXT: cmp w0, #0 // =0
478 ; CHECK-NEXT: csinc w8, w1, wzr, eq
479 ; CHECK-NEXT: mul w8, w8, w0
480 ; CHECK-NEXT: csel w8, w1, w8, gt
481 ; CHECK-NEXT: sxtw x0, w8
484 %cmp = icmp sgt i32 %a, 0
485 br i1 %cmp, label %return, label %if.end
487 if.end: ; preds = %entry
488 %cmp1 = icmp eq i32 %a, 0
489 %mul = select i1 %cmp1, i32 %b, i32 1
490 %spec.select = mul nsw i32 %mul, %a
493 return: ; preds = %if.end, %entry
494 %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
495 %retval.0 = sext i32 %retval.0.in to i64
499 define i64 @i_a_1(i32 signext %a, i32 signext %b) {
500 ; CHECK-LABEL: i_a_1:
501 ; CHECK: // %bb.0: // %entry
502 ; CHECK-NEXT: cmp w0, #1 // =1
503 ; CHECK-NEXT: csinc w8, w1, wzr, eq
504 ; CHECK-NEXT: mul w8, w8, w0
505 ; CHECK-NEXT: csel w8, w1, w8, gt
506 ; CHECK-NEXT: sxtw x0, w8
509 %cmp = icmp sgt i32 %a, 1
510 br i1 %cmp, label %return, label %if.end
512 if.end: ; preds = %entry
513 %cmp1 = icmp eq i32 %a, 1
514 %mul = select i1 %cmp1, i32 %b, i32 1
515 %spec.select = mul nsw i32 %mul, %a
518 return: ; preds = %if.end, %entry
519 %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
520 %retval.0 = sext i32 %retval.0.in to i64
524 define i64 @i_a_2(i32 signext %a, i32 signext %b) {
525 ; CHECK-LABEL: i_a_2:
526 ; CHECK: // %bb.0: // %entry
527 ; CHECK-NEXT: cmp w0, #2 // =2
528 ; CHECK-NEXT: csinc w8, w1, wzr, eq
529 ; CHECK-NEXT: mul w8, w8, w0
530 ; CHECK-NEXT: csel w8, w1, w8, gt
531 ; CHECK-NEXT: sxtw x0, w8
534 %cmp = icmp sgt i32 %a, 2
535 br i1 %cmp, label %return, label %if.end
537 if.end: ; preds = %entry
538 %cmp1 = icmp eq i32 %a, 2
539 %mul = select i1 %cmp1, i32 %b, i32 1
540 %spec.select = mul nsw i32 %mul, %a
543 return: ; preds = %if.end, %entry
544 %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
545 %retval.0 = sext i32 %retval.0.in to i64