| blob | cc97f2f01559f49708b9d2a989fac797037e678e |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=armv6 < %s | FileCheck %s --check-prefixes=CHECK,ARM,ARM6
3 ; RUN: llc -mtriple=armv7 < %s | FileCheck %s --check-prefixes=CHECK,ARM,ARM78,ARM7
4 ; RUN: llc -mtriple=armv8a < %s | FileCheck %s --check-prefixes=CHECK,ARM,ARM78,ARM8
5 ; RUN: llc -mtriple=thumbv6 < %s | FileCheck %s --check-prefixes=CHECK,THUMB,THUMB6
6 ; RUN: llc -mtriple=thumbv7 < %s | FileCheck %s --check-prefixes=CHECK,THUMB,THUMB78,THUMB7
7 ; RUN: llc -mtriple=thumbv8-eabi < %s | FileCheck %s --check-prefixes=CHECK,THUMB,THUMB78,THUMB8
9 ; We are looking for the following pattern here:
10 ; (X & (C l>> Y)) ==/!= 0
11 ; It may be optimal to hoist the constant:
12 ; ((X << Y) & C) ==/!= 0
14 ;------------------------------------------------------------------------------;
15 ; A few scalar test
16 ;------------------------------------------------------------------------------;
18 ; i8 scalar
20 define i1 @scalar_i8_signbit_eq(i8 %x, i8 %y) nounwind {
21 ; ARM-LABEL: scalar_i8_signbit_eq:
22 ; ARM: @ %bb.0:
23 ; ARM-NEXT: uxtb r1, r1
24 ; ARM-NEXT: lsl r0, r0, r1
25 ; ARM-NEXT: mov r1, #1
26 ; ARM-NEXT: uxtb r0, r0
27 ; ARM-NEXT: eor r0, r1, r0, lsr #7
28 ; ARM-NEXT: bx lr
29 ;
30 ; THUMB6-LABEL: scalar_i8_signbit_eq:
31 ; THUMB6: @ %bb.0:
32 ; THUMB6-NEXT: uxtb r1, r1
33 ; THUMB6-NEXT: lsls r0, r1
34 ; THUMB6-NEXT: movs r1, #128
35 ; THUMB6-NEXT: ands r1, r0
36 ; THUMB6-NEXT: rsbs r0, r1, #0
37 ; THUMB6-NEXT: adcs r0, r1
38 ; THUMB6-NEXT: bx lr
39 ;
40 ; THUMB78-LABEL: scalar_i8_signbit_eq:
41 ; THUMB78: @ %bb.0:
42 ; THUMB78-NEXT: uxtb r1, r1
43 ; THUMB78-NEXT: lsls r0, r1
44 ; THUMB78-NEXT: movs r1, #1
45 ; THUMB78-NEXT: uxtb r0, r0
46 ; THUMB78-NEXT: eor.w r0, r1, r0, lsr #7
47 ; THUMB78-NEXT: bx lr
48 %t0 = lshr i8 128, %y
49 %t1 = and i8 %t0, %x
50 %res = icmp eq i8 %t1, 0
51 ret i1 %res
52 }
54 define i1 @scalar_i8_lowestbit_eq(i8 %x, i8 %y) nounwind {
55 ; ARM-LABEL: scalar_i8_lowestbit_eq:
56 ; ARM: @ %bb.0:
57 ; ARM-NEXT: uxtb r1, r1
58 ; ARM-NEXT: mov r2, #1
59 ; ARM-NEXT: bic r0, r2, r0, lsl r1
60 ; ARM-NEXT: bx lr
61 ;
62 ; THUMB6-LABEL: scalar_i8_lowestbit_eq:
63 ; THUMB6: @ %bb.0:
64 ; THUMB6-NEXT: uxtb r1, r1
65 ; THUMB6-NEXT: lsls r0, r1
66 ; THUMB6-NEXT: movs r1, #1
67 ; THUMB6-NEXT: ands r1, r0
68 ; THUMB6-NEXT: rsbs r0, r1, #0
69 ; THUMB6-NEXT: adcs r0, r1
70 ; THUMB6-NEXT: bx lr
71 ;
72 ; THUMB78-LABEL: scalar_i8_lowestbit_eq:
73 ; THUMB78: @ %bb.0:
74 ; THUMB78-NEXT: uxtb r1, r1
75 ; THUMB78-NEXT: lsls r0, r1
76 ; THUMB78-NEXT: movs r1, #1
77 ; THUMB78-NEXT: bic.w r0, r1, r0
78 ; THUMB78-NEXT: bx lr
79 %t0 = lshr i8 1, %y
80 %t1 = and i8 %t0, %x
81 %res = icmp eq i8 %t1, 0
82 ret i1 %res
83 }
85 define i1 @scalar_i8_bitsinmiddle_eq(i8 %x, i8 %y) nounwind {
86 ; ARM-LABEL: scalar_i8_bitsinmiddle_eq:
87 ; ARM: @ %bb.0:
88 ; ARM-NEXT: uxtb r1, r1
89 ; ARM-NEXT: mov r2, #24
90 ; ARM-NEXT: and r0, r2, r0, lsl r1
91 ; ARM-NEXT: clz r0, r0
92 ; ARM-NEXT: lsr r0, r0, #5
93 ; ARM-NEXT: bx lr
94 ;
95 ; THUMB6-LABEL: scalar_i8_bitsinmiddle_eq:
96 ; THUMB6: @ %bb.0:
97 ; THUMB6-NEXT: uxtb r1, r1
98 ; THUMB6-NEXT: lsls r0, r1
99 ; THUMB6-NEXT: movs r1, #24
100 ; THUMB6-NEXT: ands r1, r0
101 ; THUMB6-NEXT: rsbs r0, r1, #0
102 ; THUMB6-NEXT: adcs r0, r1
103 ; THUMB6-NEXT: bx lr
104 ;
105 ; THUMB78-LABEL: scalar_i8_bitsinmiddle_eq:
106 ; THUMB78: @ %bb.0:
107 ; THUMB78-NEXT: uxtb r1, r1
108 ; THUMB78-NEXT: lsls r0, r1
109 ; THUMB78-NEXT: and r0, r0, #24
110 ; THUMB78-NEXT: clz r0, r0
111 ; THUMB78-NEXT: lsrs r0, r0, #5
112 ; THUMB78-NEXT: bx lr
113 %t0 = lshr i8 24, %y
114 %t1 = and i8 %t0, %x
115 %res = icmp eq i8 %t1, 0
116 ret i1 %res
117 }
119 ; i16 scalar
121 define i1 @scalar_i16_signbit_eq(i16 %x, i16 %y) nounwind {
122 ; ARM-LABEL: scalar_i16_signbit_eq:
123 ; ARM: @ %bb.0:
124 ; ARM-NEXT: uxth r1, r1
125 ; ARM-NEXT: lsl r0, r0, r1
126 ; ARM-NEXT: mov r1, #1
127 ; ARM-NEXT: uxth r0, r0
128 ; ARM-NEXT: eor r0, r1, r0, lsr #15
129 ; ARM-NEXT: bx lr
130 ;
131 ; THUMB6-LABEL: scalar_i16_signbit_eq:
132 ; THUMB6: @ %bb.0:
133 ; THUMB6-NEXT: uxth r1, r1
134 ; THUMB6-NEXT: lsls r0, r1
135 ; THUMB6-NEXT: movs r1, #1
136 ; THUMB6-NEXT: lsls r1, r1, #15
137 ; THUMB6-NEXT: ands r1, r0
138 ; THUMB6-NEXT: rsbs r0, r1, #0
139 ; THUMB6-NEXT: adcs r0, r1
140 ; THUMB6-NEXT: bx lr
141 ;
142 ; THUMB78-LABEL: scalar_i16_signbit_eq:
143 ; THUMB78: @ %bb.0:
144 ; THUMB78-NEXT: uxth r1, r1
145 ; THUMB78-NEXT: lsls r0, r1
146 ; THUMB78-NEXT: movs r1, #1
147 ; THUMB78-NEXT: uxth r0, r0
148 ; THUMB78-NEXT: eor.w r0, r1, r0, lsr #15
149 ; THUMB78-NEXT: bx lr
150 %t0 = lshr i16 32768, %y
151 %t1 = and i16 %t0, %x
152 %res = icmp eq i16 %t1, 0
153 ret i1 %res
154 }
156 define i1 @scalar_i16_lowestbit_eq(i16 %x, i16 %y) nounwind {
157 ; ARM-LABEL: scalar_i16_lowestbit_eq:
158 ; ARM: @ %bb.0:
159 ; ARM-NEXT: uxth r1, r1
160 ; ARM-NEXT: mov r2, #1
161 ; ARM-NEXT: bic r0, r2, r0, lsl r1
162 ; ARM-NEXT: bx lr
163 ;
164 ; THUMB6-LABEL: scalar_i16_lowestbit_eq:
165 ; THUMB6: @ %bb.0:
166 ; THUMB6-NEXT: uxth r1, r1
167 ; THUMB6-NEXT: lsls r0, r1
168 ; THUMB6-NEXT: movs r1, #1
169 ; THUMB6-NEXT: ands r1, r0
170 ; THUMB6-NEXT: rsbs r0, r1, #0
171 ; THUMB6-NEXT: adcs r0, r1
172 ; THUMB6-NEXT: bx lr
173 ;
174 ; THUMB78-LABEL: scalar_i16_lowestbit_eq:
175 ; THUMB78: @ %bb.0:
176 ; THUMB78-NEXT: uxth r1, r1
177 ; THUMB78-NEXT: lsls r0, r1
178 ; THUMB78-NEXT: movs r1, #1
179 ; THUMB78-NEXT: bic.w r0, r1, r0
180 ; THUMB78-NEXT: bx lr
181 %t0 = lshr i16 1, %y
182 %t1 = and i16 %t0, %x
183 %res = icmp eq i16 %t1, 0
184 ret i1 %res
185 }
187 define i1 @scalar_i16_bitsinmiddle_eq(i16 %x, i16 %y) nounwind {
188 ; ARM-LABEL: scalar_i16_bitsinmiddle_eq:
189 ; ARM: @ %bb.0:
190 ; ARM-NEXT: uxth r1, r1
191 ; ARM-NEXT: mov r2, #4080
192 ; ARM-NEXT: and r0, r2, r0, lsl r1
193 ; ARM-NEXT: clz r0, r0
194 ; ARM-NEXT: lsr r0, r0, #5
195 ; ARM-NEXT: bx lr
196 ;
197 ; THUMB6-LABEL: scalar_i16_bitsinmiddle_eq:
198 ; THUMB6: @ %bb.0:
199 ; THUMB6-NEXT: uxth r1, r1
200 ; THUMB6-NEXT: lsls r0, r1
201 ; THUMB6-NEXT: movs r1, #255
202 ; THUMB6-NEXT: lsls r1, r1, #4
203 ; THUMB6-NEXT: ands r1, r0
204 ; THUMB6-NEXT: rsbs r0, r1, #0
205 ; THUMB6-NEXT: adcs r0, r1
206 ; THUMB6-NEXT: bx lr
207 ;
208 ; THUMB78-LABEL: scalar_i16_bitsinmiddle_eq:
209 ; THUMB78: @ %bb.0:
210 ; THUMB78-NEXT: uxth r1, r1
211 ; THUMB78-NEXT: lsls r0, r1
212 ; THUMB78-NEXT: and r0, r0, #4080
213 ; THUMB78-NEXT: clz r0, r0
214 ; THUMB78-NEXT: lsrs r0, r0, #5
215 ; THUMB78-NEXT: bx lr
216 %t0 = lshr i16 4080, %y
217 %t1 = and i16 %t0, %x
218 %res = icmp eq i16 %t1, 0
219 ret i1 %res
220 }
222 ; i32 scalar
224 define i1 @scalar_i32_signbit_eq(i32 %x, i32 %y) nounwind {
225 ; ARM-LABEL: scalar_i32_signbit_eq:
226 ; ARM: @ %bb.0:
227 ; ARM-NEXT: mvn r0, r0, lsl r1
228 ; ARM-NEXT: lsr r0, r0, #31
229 ; ARM-NEXT: bx lr
230 ;
231 ; THUMB6-LABEL: scalar_i32_signbit_eq:
232 ; THUMB6: @ %bb.0:
233 ; THUMB6-NEXT: lsls r0, r1
234 ; THUMB6-NEXT: movs r1, #1
235 ; THUMB6-NEXT: lsls r1, r1, #31
236 ; THUMB6-NEXT: ands r1, r0
237 ; THUMB6-NEXT: rsbs r0, r1, #0
238 ; THUMB6-NEXT: adcs r0, r1
239 ; THUMB6-NEXT: bx lr
240 ;
241 ; THUMB78-LABEL: scalar_i32_signbit_eq:
242 ; THUMB78: @ %bb.0:
243 ; THUMB78-NEXT: lsls r0, r1
244 ; THUMB78-NEXT: mvns r0, r0
245 ; THUMB78-NEXT: lsrs r0, r0, #31
246 ; THUMB78-NEXT: bx lr
247 %t0 = lshr i32 2147483648, %y
248 %t1 = and i32 %t0, %x
249 %res = icmp eq i32 %t1, 0
250 ret i1 %res
251 }
253 define i1 @scalar_i32_lowestbit_eq(i32 %x, i32 %y) nounwind {
254 ; ARM-LABEL: scalar_i32_lowestbit_eq:
255 ; ARM: @ %bb.0:
256 ; ARM-NEXT: mov r2, #1
257 ; ARM-NEXT: bic r0, r2, r0, lsl r1
258 ; ARM-NEXT: bx lr
259 ;
260 ; THUMB6-LABEL: scalar_i32_lowestbit_eq:
261 ; THUMB6: @ %bb.0:
262 ; THUMB6-NEXT: lsls r0, r1
263 ; THUMB6-NEXT: movs r1, #1
264 ; THUMB6-NEXT: ands r1, r0
265 ; THUMB6-NEXT: rsbs r0, r1, #0
266 ; THUMB6-NEXT: adcs r0, r1
267 ; THUMB6-NEXT: bx lr
268 ;
269 ; THUMB78-LABEL: scalar_i32_lowestbit_eq:
270 ; THUMB78: @ %bb.0:
271 ; THUMB78-NEXT: lsls r0, r1
272 ; THUMB78-NEXT: movs r1, #1
273 ; THUMB78-NEXT: bic.w r0, r1, r0
274 ; THUMB78-NEXT: bx lr
275 %t0 = lshr i32 1, %y
276 %t1 = and i32 %t0, %x
277 %res = icmp eq i32 %t1, 0
278 ret i1 %res
279 }
281 define i1 @scalar_i32_bitsinmiddle_eq(i32 %x, i32 %y) nounwind {
282 ; ARM6-LABEL: scalar_i32_bitsinmiddle_eq:
283 ; ARM6: @ %bb.0:
284 ; ARM6-NEXT: mov r2, #65280
285 ; ARM6-NEXT: orr r2, r2, #16711680
286 ; ARM6-NEXT: and r0, r2, r0, lsl r1
287 ; ARM6-NEXT: clz r0, r0
288 ; ARM6-NEXT: lsr r0, r0, #5
289 ; ARM6-NEXT: bx lr
290 ;
291 ; ARM78-LABEL: scalar_i32_bitsinmiddle_eq:
292 ; ARM78: @ %bb.0:
293 ; ARM78-NEXT: movw r2, #65280
294 ; ARM78-NEXT: movt r2, #255
295 ; ARM78-NEXT: and r0, r2, r0, lsl r1
296 ; ARM78-NEXT: clz r0, r0
297 ; ARM78-NEXT: lsr r0, r0, #5
298 ; ARM78-NEXT: bx lr
299 ;
300 ; THUMB6-LABEL: scalar_i32_bitsinmiddle_eq:
301 ; THUMB6: @ %bb.0:
302 ; THUMB6-NEXT: lsls r0, r1
303 ; THUMB6-NEXT: ldr r1, .LCPI8_0
304 ; THUMB6-NEXT: ands r1, r0
305 ; THUMB6-NEXT: rsbs r0, r1, #0
306 ; THUMB6-NEXT: adcs r0, r1
307 ; THUMB6-NEXT: bx lr
308 ; THUMB6-NEXT: .p2align 2
309 ; THUMB6-NEXT: @ %bb.1:
310 ; THUMB6-NEXT: .LCPI8_0:
311 ; THUMB6-NEXT: .long 16776960 @ 0xffff00
312 ;
313 ; THUMB78-LABEL: scalar_i32_bitsinmiddle_eq:
314 ; THUMB78: @ %bb.0:
315 ; THUMB78-NEXT: lsls r0, r1
316 ; THUMB78-NEXT: movw r1, #65280
317 ; THUMB78-NEXT: movt r1, #255
318 ; THUMB78-NEXT: ands r0, r1
319 ; THUMB78-NEXT: clz r0, r0
320 ; THUMB78-NEXT: lsrs r0, r0, #5
321 ; THUMB78-NEXT: bx lr
322 %t0 = lshr i32 16776960, %y
323 %t1 = and i32 %t0, %x
324 %res = icmp eq i32 %t1, 0
325 ret i1 %res
326 }
328 ; i64 scalar
330 define i1 @scalar_i64_signbit_eq(i64 %x, i64 %y) nounwind {
331 ; ARM-LABEL: scalar_i64_signbit_eq:
332 ; ARM: @ %bb.0:
333 ; ARM-NEXT: rsb r3, r2, #32
334 ; ARM-NEXT: lsr r3, r0, r3
335 ; ARM-NEXT: orr r1, r3, r1, lsl r2
336 ; ARM-NEXT: subs r2, r2, #32
337 ; ARM-NEXT: lslpl r1, r0, r2
338 ; ARM-NEXT: mvn r0, r1
339 ; ARM-NEXT: lsr r0, r0, #31
340 ; ARM-NEXT: bx lr
341 ;
342 ; THUMB6-LABEL: scalar_i64_signbit_eq:
343 ; THUMB6: @ %bb.0:
344 ; THUMB6-NEXT: push {r7, lr}
345 ; THUMB6-NEXT: bl __ashldi3
346 ; THUMB6-NEXT: movs r0, #1
347 ; THUMB6-NEXT: lsls r2, r0, #31
348 ; THUMB6-NEXT: ands r2, r1
349 ; THUMB6-NEXT: rsbs r0, r2, #0
350 ; THUMB6-NEXT: adcs r0, r2
351 ; THUMB6-NEXT: pop {r7, pc}
352 ;
353 ; THUMB7-LABEL: scalar_i64_signbit_eq:
354 ; THUMB7: @ %bb.0:
355 ; THUMB7-NEXT: rsb.w r3, r2, #32
356 ; THUMB7-NEXT: lsls r1, r2
357 ; THUMB7-NEXT: subs r2, #32
358 ; THUMB7-NEXT: lsr.w r3, r0, r3
359 ; THUMB7-NEXT: orr.w r1, r1, r3
360 ; THUMB7-NEXT: it pl
361 ; THUMB7-NEXT: lslpl.w r1, r0, r2
362 ; THUMB7-NEXT: mvns r0, r1
363 ; THUMB7-NEXT: lsrs r0, r0, #31
364 ; THUMB7-NEXT: bx lr
365 ;
366 ; THUMB8-LABEL: scalar_i64_signbit_eq:
367 ; THUMB8: @ %bb.0:
368 ; THUMB8-NEXT: rsb.w r3, r2, #32
369 ; THUMB8-NEXT: lsls r1, r2
370 ; THUMB8-NEXT: lsr.w r3, r0, r3
371 ; THUMB8-NEXT: orrs r1, r3
372 ; THUMB8-NEXT: subs r2, #32
373 ; THUMB8-NEXT: lsl.w r0, r0, r2
374 ; THUMB8-NEXT: it mi
375 ; THUMB8-NEXT: movmi r0, r1
376 ; THUMB8-NEXT: mvns r0, r0
377 ; THUMB8-NEXT: lsrs r0, r0, #31
378 ; THUMB8-NEXT: bx lr
379 %t0 = lshr i64 9223372036854775808, %y
380 %t1 = and i64 %t0, %x
381 %res = icmp eq i64 %t1, 0
382 ret i1 %res
383 }
385 define i1 @scalar_i64_lowestbit_eq(i64 %x, i64 %y) nounwind {
386 ; ARM6-LABEL: scalar_i64_lowestbit_eq:
387 ; ARM6: @ %bb.0:
388 ; ARM6-NEXT: subs r1, r2, #32
389 ; ARM6-NEXT: lsl r0, r0, r2
390 ; ARM6-NEXT: movpl r0, #0
391 ; ARM6-NEXT: mov r1, #1
392 ; ARM6-NEXT: bic r0, r1, r0
393 ; ARM6-NEXT: bx lr
394 ;
395 ; ARM78-LABEL: scalar_i64_lowestbit_eq:
396 ; ARM78: @ %bb.0:
397 ; ARM78-NEXT: subs r1, r2, #32
398 ; ARM78-NEXT: lsl r0, r0, r2
399 ; ARM78-NEXT: movwpl r0, #0
400 ; ARM78-NEXT: mov r1, #1
401 ; ARM78-NEXT: bic r0, r1, r0
402 ; ARM78-NEXT: bx lr
403 ;
404 ; THUMB6-LABEL: scalar_i64_lowestbit_eq:
405 ; THUMB6: @ %bb.0:
406 ; THUMB6-NEXT: push {r7, lr}
407 ; THUMB6-NEXT: bl __ashldi3
408 ; THUMB6-NEXT: movs r1, #1
409 ; THUMB6-NEXT: ands r1, r0
410 ; THUMB6-NEXT: rsbs r0, r1, #0
411 ; THUMB6-NEXT: adcs r0, r1
412 ; THUMB6-NEXT: pop {r7, pc}
413 ;
414 ; THUMB78-LABEL: scalar_i64_lowestbit_eq:
415 ; THUMB78: @ %bb.0:
416 ; THUMB78-NEXT: lsls r0, r2
417 ; THUMB78-NEXT: subs.w r1, r2, #32
418 ; THUMB78-NEXT: it pl
419 ; THUMB78-NEXT: movpl r0, #0
420 ; THUMB78-NEXT: movs r1, #1
421 ; THUMB78-NEXT: bic.w r0, r1, r0
422 ; THUMB78-NEXT: bx lr
423 %t0 = lshr i64 1, %y
424 %t1 = and i64 %t0, %x
425 %res = icmp eq i64 %t1, 0
426 ret i1 %res
427 }
429 define i1 @scalar_i64_bitsinmiddle_eq(i64 %x, i64 %y) nounwind {
430 ; ARM6-LABEL: scalar_i64_bitsinmiddle_eq:
431 ; ARM6: @ %bb.0:
432 ; ARM6-NEXT: rsb r3, r2, #32
433 ; ARM6-NEXT: lsr r3, r0, r3
434 ; ARM6-NEXT: orr r1, r3, r1, lsl r2
435 ; ARM6-NEXT: subs r3, r2, #32
436 ; ARM6-NEXT: lslpl r1, r0, r3
437 ; ARM6-NEXT: lsl r0, r0, r2
438 ; ARM6-NEXT: movpl r0, #0
439 ; ARM6-NEXT: pkhbt r0, r1, r0
440 ; ARM6-NEXT: clz r0, r0
441 ; ARM6-NEXT: lsr r0, r0, #5
442 ; ARM6-NEXT: bx lr
443 ;
444 ; ARM78-LABEL: scalar_i64_bitsinmiddle_eq:
445 ; ARM78: @ %bb.0:
446 ; ARM78-NEXT: rsb r3, r2, #32
447 ; ARM78-NEXT: lsr r3, r0, r3
448 ; ARM78-NEXT: orr r1, r3, r1, lsl r2
449 ; ARM78-NEXT: subs r3, r2, #32
450 ; ARM78-NEXT: lslpl r1, r0, r3
451 ; ARM78-NEXT: lsl r0, r0, r2
452 ; ARM78-NEXT: movwpl r0, #0
453 ; ARM78-NEXT: pkhbt r0, r1, r0
454 ; ARM78-NEXT: clz r0, r0
455 ; ARM78-NEXT: lsr r0, r0, #5
456 ; ARM78-NEXT: bx lr
457 ;
458 ; THUMB6-LABEL: scalar_i64_bitsinmiddle_eq:
459 ; THUMB6: @ %bb.0:
460 ; THUMB6-NEXT: push {r7, lr}
461 ; THUMB6-NEXT: bl __ashldi3
462 ; THUMB6-NEXT: ldr r2, .LCPI11_0
463 ; THUMB6-NEXT: ands r2, r0
464 ; THUMB6-NEXT: uxth r0, r1
465 ; THUMB6-NEXT: adds r1, r2, r0
466 ; THUMB6-NEXT: rsbs r0, r1, #0
467 ; THUMB6-NEXT: adcs r0, r1
468 ; THUMB6-NEXT: pop {r7, pc}
469 ; THUMB6-NEXT: .p2align 2
470 ; THUMB6-NEXT: @ %bb.1:
471 ; THUMB6-NEXT: .LCPI11_0:
472 ; THUMB6-NEXT: .long 4294901760 @ 0xffff0000
473 ;
474 ; THUMB7-LABEL: scalar_i64_bitsinmiddle_eq:
475 ; THUMB7: @ %bb.0:
476 ; THUMB7-NEXT: rsb.w r3, r2, #32
477 ; THUMB7-NEXT: lsls r1, r2
478 ; THUMB7-NEXT: lsr.w r3, r0, r3
479 ; THUMB7-NEXT: orrs r1, r3
480 ; THUMB7-NEXT: subs.w r3, r2, #32
481 ; THUMB7-NEXT: it pl
482 ; THUMB7-NEXT: lslpl.w r1, r0, r3
483 ; THUMB7-NEXT: lsl.w r0, r0, r2
484 ; THUMB7-NEXT: it pl
485 ; THUMB7-NEXT: movpl r0, #0
486 ; THUMB7-NEXT: pkhbt r0, r1, r0
487 ; THUMB7-NEXT: clz r0, r0
488 ; THUMB7-NEXT: lsrs r0, r0, #5
489 ; THUMB7-NEXT: bx lr
490 ;
491 ; THUMB8-LABEL: scalar_i64_bitsinmiddle_eq:
492 ; THUMB8: @ %bb.0:
493 ; THUMB8-NEXT: rsb.w r3, r2, #32
494 ; THUMB8-NEXT: lsls r1, r2
495 ; THUMB8-NEXT: lsr.w r3, r0, r3
496 ; THUMB8-NEXT: orrs r1, r3
497 ; THUMB8-NEXT: subs.w r3, r2, #32
498 ; THUMB8-NEXT: lsl.w r3, r0, r3
499 ; THUMB8-NEXT: lsl.w r0, r0, r2
500 ; THUMB8-NEXT: it mi
501 ; THUMB8-NEXT: movmi r3, r1
502 ; THUMB8-NEXT: it pl
503 ; THUMB8-NEXT: movpl r0, #0
504 ; THUMB8-NEXT: pkhbt r0, r3, r0
505 ; THUMB8-NEXT: clz r0, r0
506 ; THUMB8-NEXT: lsrs r0, r0, #5
507 ; THUMB8-NEXT: bx lr
508 %t0 = lshr i64 281474976645120, %y
509 %t1 = and i64 %t0, %x
510 %res = icmp eq i64 %t1, 0
511 ret i1 %res
512 }
514 ;------------------------------------------------------------------------------;
515 ; A few trivial vector tests
516 ;------------------------------------------------------------------------------;
518 define <4 x i1> @vec_4xi32_splat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
519 ; ARM6-LABEL: vec_4xi32_splat_eq:
520 ; ARM6: @ %bb.0:
521 ; ARM6-NEXT: push {r11, lr}
522 ; ARM6-NEXT: ldr r12, [sp, #8]
523 ; ARM6-NEXT: mov lr, #1
524 ; ARM6-NEXT: bic r0, lr, r0, lsl r12
525 ; ARM6-NEXT: ldr r12, [sp, #12]
526 ; ARM6-NEXT: bic r1, lr, r1, lsl r12
527 ; ARM6-NEXT: ldr r12, [sp, #16]
528 ; ARM6-NEXT: bic r2, lr, r2, lsl r12
529 ; ARM6-NEXT: ldr r12, [sp, #20]
530 ; ARM6-NEXT: bic r3, lr, r3, lsl r12
531 ; ARM6-NEXT: pop {r11, pc}
532 ;
533 ; ARM78-LABEL: vec_4xi32_splat_eq:
534 ; ARM78: @ %bb.0:
535 ; ARM78-NEXT: vmov d17, r2, r3
536 ; ARM78-NEXT: mov r12, sp
537 ; ARM78-NEXT: vld1.64 {d18, d19}, [r12]
538 ; ARM78-NEXT: vmov d16, r0, r1
539 ; ARM78-NEXT: vmov.i32 q10, #0x1
540 ; ARM78-NEXT: vshl.u32 q8, q8, q9
541 ; ARM78-NEXT: vtst.32 q8, q8, q10
542 ; ARM78-NEXT: vmvn q8, q8
543 ; ARM78-NEXT: vmovn.i32 d16, q8
544 ; ARM78-NEXT: vmov r0, r1, d16
545 ; ARM78-NEXT: bx lr
546 ;
547 ; THUMB6-LABEL: vec_4xi32_splat_eq:
548 ; THUMB6: @ %bb.0:
549 ; THUMB6-NEXT: push {r4, r5, r7, lr}
550 ; THUMB6-NEXT: ldr r4, [sp, #16]
551 ; THUMB6-NEXT: lsls r0, r4
552 ; THUMB6-NEXT: movs r4, #1
553 ; THUMB6-NEXT: ands r0, r4
554 ; THUMB6-NEXT: rsbs r5, r0, #0
555 ; THUMB6-NEXT: adcs r0, r5
556 ; THUMB6-NEXT: ldr r5, [sp, #20]
557 ; THUMB6-NEXT: lsls r1, r5
558 ; THUMB6-NEXT: ands r1, r4
559 ; THUMB6-NEXT: rsbs r5, r1, #0
560 ; THUMB6-NEXT: adcs r1, r5
561 ; THUMB6-NEXT: ldr r5, [sp, #24]
562 ; THUMB6-NEXT: lsls r2, r5
563 ; THUMB6-NEXT: ands r2, r4
564 ; THUMB6-NEXT: rsbs r5, r2, #0
565 ; THUMB6-NEXT: adcs r2, r5
566 ; THUMB6-NEXT: ldr r5, [sp, #28]
567 ; THUMB6-NEXT: lsls r3, r5
568 ; THUMB6-NEXT: ands r3, r4
569 ; THUMB6-NEXT: rsbs r4, r3, #0
570 ; THUMB6-NEXT: adcs r3, r4
571 ; THUMB6-NEXT: pop {r4, r5, r7, pc}
572 ;
573 ; THUMB78-LABEL: vec_4xi32_splat_eq:
574 ; THUMB78: @ %bb.0:
575 ; THUMB78-NEXT: vmov d17, r2, r3
576 ; THUMB78-NEXT: mov r12, sp
577 ; THUMB78-NEXT: vld1.64 {d18, d19}, [r12]
578 ; THUMB78-NEXT: vmov d16, r0, r1
579 ; THUMB78-NEXT: vmov.i32 q10, #0x1
580 ; THUMB78-NEXT: vshl.u32 q8, q8, q9
581 ; THUMB78-NEXT: vtst.32 q8, q8, q10
582 ; THUMB78-NEXT: vmvn q8, q8
583 ; THUMB78-NEXT: vmovn.i32 d16, q8
584 ; THUMB78-NEXT: vmov r0, r1, d16
585 ; THUMB78-NEXT: bx lr
586 %t0 = lshr <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %y
587 %t1 = and <4 x i32> %t0, %x
588 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0>
589 ret <4 x i1> %res
590 }
592 define <4 x i1> @vec_4xi32_nonsplat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
593 ; ARM6-LABEL: vec_4xi32_nonsplat_eq:
594 ; ARM6: @ %bb.0:
595 ; ARM6-NEXT: ldr r12, [sp, #4]
596 ; ARM6-NEXT: mov r0, #1
597 ; ARM6-NEXT: bic r1, r0, r1, lsl r12
598 ; ARM6-NEXT: ldr r12, [sp, #8]
599 ; ARM6-NEXT: mov r0, #65280
600 ; ARM6-NEXT: orr r0, r0, #16711680
601 ; ARM6-NEXT: and r0, r0, r2, lsl r12
602 ; ARM6-NEXT: clz r0, r0
603 ; ARM6-NEXT: lsr r2, r0, #5
604 ; ARM6-NEXT: ldr r0, [sp, #12]
605 ; ARM6-NEXT: mvn r0, r3, lsl r0
606 ; ARM6-NEXT: lsr r3, r0, #31
607 ; ARM6-NEXT: mov r0, #1
608 ; ARM6-NEXT: bx lr
609 ;
610 ; ARM78-LABEL: vec_4xi32_nonsplat_eq:
611 ; ARM78: @ %bb.0:
612 ; ARM78-NEXT: mov r12, sp
613 ; ARM78-NEXT: vld1.64 {d16, d17}, [r12]
614 ; ARM78-NEXT: adr r12, .LCPI13_0
615 ; ARM78-NEXT: vneg.s32 q8, q8
616 ; ARM78-NEXT: vld1.64 {d18, d19}, [r12:128]
617 ; ARM78-NEXT: vshl.u32 q8, q9, q8
618 ; ARM78-NEXT: vmov d19, r2, r3
619 ; ARM78-NEXT: vmov d18, r0, r1
620 ; ARM78-NEXT: vtst.32 q8, q8, q9
621 ; ARM78-NEXT: vmvn q8, q8
622 ; ARM78-NEXT: vmovn.i32 d16, q8
623 ; ARM78-NEXT: vmov r0, r1, d16
624 ; ARM78-NEXT: bx lr
625 ; ARM78-NEXT: .p2align 4
626 ; ARM78-NEXT: @ %bb.1:
627 ; ARM78-NEXT: .LCPI13_0:
628 ; ARM78-NEXT: .long 0 @ 0x0
629 ; ARM78-NEXT: .long 1 @ 0x1
630 ; ARM78-NEXT: .long 16776960 @ 0xffff00
631 ; ARM78-NEXT: .long 2147483648 @ 0x80000000
632 ;
633 ; THUMB6-LABEL: vec_4xi32_nonsplat_eq:
634 ; THUMB6: @ %bb.0:
635 ; THUMB6-NEXT: push {r4, lr}
636 ; THUMB6-NEXT: ldr r0, [sp, #12]
637 ; THUMB6-NEXT: lsls r1, r0
638 ; THUMB6-NEXT: movs r0, #1
639 ; THUMB6-NEXT: ands r1, r0
640 ; THUMB6-NEXT: rsbs r4, r1, #0
641 ; THUMB6-NEXT: adcs r1, r4
642 ; THUMB6-NEXT: ldr r4, [sp, #16]
643 ; THUMB6-NEXT: lsls r2, r4
644 ; THUMB6-NEXT: ldr r4, .LCPI13_0
645 ; THUMB6-NEXT: ands r4, r2
646 ; THUMB6-NEXT: rsbs r2, r4, #0
647 ; THUMB6-NEXT: adcs r2, r4
648 ; THUMB6-NEXT: ldr r4, [sp, #20]
649 ; THUMB6-NEXT: lsls r3, r4
650 ; THUMB6-NEXT: lsls r4, r0, #31
651 ; THUMB6-NEXT: ands r4, r3
652 ; THUMB6-NEXT: rsbs r3, r4, #0
653 ; THUMB6-NEXT: adcs r3, r4
654 ; THUMB6-NEXT: pop {r4, pc}
655 ; THUMB6-NEXT: .p2align 2
656 ; THUMB6-NEXT: @ %bb.1:
657 ; THUMB6-NEXT: .LCPI13_0:
658 ; THUMB6-NEXT: .long 16776960 @ 0xffff00
659 ;
660 ; THUMB78-LABEL: vec_4xi32_nonsplat_eq:
661 ; THUMB78: @ %bb.0:
662 ; THUMB78-NEXT: mov r12, sp
663 ; THUMB78-NEXT: vld1.64 {d16, d17}, [r12]
664 ; THUMB78-NEXT: adr.w r12, .LCPI13_0
665 ; THUMB78-NEXT: vneg.s32 q8, q8
666 ; THUMB78-NEXT: vld1.64 {d18, d19}, [r12:128]
667 ; THUMB78-NEXT: vshl.u32 q8, q9, q8
668 ; THUMB78-NEXT: vmov d19, r2, r3
669 ; THUMB78-NEXT: vmov d18, r0, r1
670 ; THUMB78-NEXT: vtst.32 q8, q8, q9
671 ; THUMB78-NEXT: vmvn q8, q8
672 ; THUMB78-NEXT: vmovn.i32 d16, q8
673 ; THUMB78-NEXT: vmov r0, r1, d16
674 ; THUMB78-NEXT: bx lr
675 ; THUMB78-NEXT: .p2align 4
676 ; THUMB78-NEXT: @ %bb.1:
677 ; THUMB78-NEXT: .LCPI13_0:
678 ; THUMB78-NEXT: .long 0 @ 0x0
679 ; THUMB78-NEXT: .long 1 @ 0x1
680 ; THUMB78-NEXT: .long 16776960 @ 0xffff00
681 ; THUMB78-NEXT: .long 2147483648 @ 0x80000000
682 %t0 = lshr <4 x i32> <i32 0, i32 1, i32 16776960, i32 2147483648>, %y
683 %t1 = and <4 x i32> %t0, %x
684 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0>
685 ret <4 x i1> %res
686 }
688 define <4 x i1> @vec_4xi32_nonsplat_undef0_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
689 ; ARM6-LABEL: vec_4xi32_nonsplat_undef0_eq:
690 ; ARM6: @ %bb.0:
691 ; ARM6-NEXT: push {r11, lr}
692 ; ARM6-NEXT: ldr r2, [sp, #12]
693 ; ARM6-NEXT: mov lr, #1
694 ; ARM6-NEXT: ldr r12, [sp, #8]
695 ; ARM6-NEXT: bic r1, lr, r1, lsl r2
696 ; ARM6-NEXT: ldr r2, [sp, #20]
697 ; ARM6-NEXT: bic r0, lr, r0, lsl r12
698 ; ARM6-NEXT: bic r3, lr, r3, lsl r2
699 ; ARM6-NEXT: mov r2, #1
700 ; ARM6-NEXT: pop {r11, pc}
701 ;
702 ; ARM78-LABEL: vec_4xi32_nonsplat_undef0_eq:
703 ; ARM78: @ %bb.0:
704 ; ARM78-NEXT: vmov d17, r2, r3
705 ; ARM78-NEXT: mov r12, sp
706 ; ARM78-NEXT: vld1.64 {d18, d19}, [r12]
707 ; ARM78-NEXT: vmov d16, r0, r1
708 ; ARM78-NEXT: vmov.i32 q10, #0x1
709 ; ARM78-NEXT: vshl.u32 q8, q8, q9
710 ; ARM78-NEXT: vtst.32 q8, q8, q10
711 ; ARM78-NEXT: vmvn q8, q8
712 ; ARM78-NEXT: vmovn.i32 d16, q8
713 ; ARM78-NEXT: vmov r0, r1, d16
714 ; ARM78-NEXT: bx lr
715 ;
716 ; THUMB6-LABEL: vec_4xi32_nonsplat_undef0_eq:
717 ; THUMB6: @ %bb.0:
718 ; THUMB6-NEXT: push {r4, lr}
719 ; THUMB6-NEXT: ldr r2, [sp, #8]
720 ; THUMB6-NEXT: lsls r0, r2
721 ; THUMB6-NEXT: movs r2, #1
722 ; THUMB6-NEXT: ands r0, r2
723 ; THUMB6-NEXT: rsbs r4, r0, #0
724 ; THUMB6-NEXT: adcs r0, r4
725 ; THUMB6-NEXT: ldr r4, [sp, #12]
726 ; THUMB6-NEXT: lsls r1, r4
727 ; THUMB6-NEXT: ands r1, r2
728 ; THUMB6-NEXT: rsbs r4, r1, #0
729 ; THUMB6-NEXT: adcs r1, r4
730 ; THUMB6-NEXT: ldr r4, [sp, #20]
731 ; THUMB6-NEXT: lsls r3, r4
732 ; THUMB6-NEXT: ands r3, r2
733 ; THUMB6-NEXT: rsbs r4, r3, #0
734 ; THUMB6-NEXT: adcs r3, r4
735 ; THUMB6-NEXT: pop {r4, pc}
736 ;
737 ; THUMB78-LABEL: vec_4xi32_nonsplat_undef0_eq:
738 ; THUMB78: @ %bb.0:
739 ; THUMB78-NEXT: vmov d17, r2, r3
740 ; THUMB78-NEXT: mov r12, sp
741 ; THUMB78-NEXT: vld1.64 {d18, d19}, [r12]
742 ; THUMB78-NEXT: vmov d16, r0, r1
743 ; THUMB78-NEXT: vmov.i32 q10, #0x1
744 ; THUMB78-NEXT: vshl.u32 q8, q8, q9
745 ; THUMB78-NEXT: vtst.32 q8, q8, q10
746 ; THUMB78-NEXT: vmvn q8, q8
747 ; THUMB78-NEXT: vmovn.i32 d16, q8
748 ; THUMB78-NEXT: vmov r0, r1, d16
749 ; THUMB78-NEXT: bx lr
750 %t0 = lshr <4 x i32> <i32 1, i32 1, i32 undef, i32 1>, %y
751 %t1 = and <4 x i32> %t0, %x
752 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0>
753 ret <4 x i1> %res
754 }
755 define <4 x i1> @vec_4xi32_nonsplat_undef1_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
756 ; ARM6-LABEL: vec_4xi32_nonsplat_undef1_eq:
757 ; ARM6: @ %bb.0:
758 ; ARM6-NEXT: push {r11, lr}
759 ; ARM6-NEXT: ldr r2, [sp, #12]
760 ; ARM6-NEXT: mov lr, #1
761 ; ARM6-NEXT: ldr r12, [sp, #8]
762 ; ARM6-NEXT: bic r1, lr, r1, lsl r2
763 ; ARM6-NEXT: ldr r2, [sp, #20]
764 ; ARM6-NEXT: bic r0, lr, r0, lsl r12
765 ; ARM6-NEXT: bic r3, lr, r3, lsl r2
766 ; ARM6-NEXT: pop {r11, pc}
767 ;
768 ; ARM78-LABEL: vec_4xi32_nonsplat_undef1_eq:
769 ; ARM78: @ %bb.0:
770 ; ARM78-NEXT: mov r12, sp
771 ; ARM78-NEXT: vld1.64 {d16, d17}, [r12]
772 ; ARM78-NEXT: vmov.i32 q9, #0x1
773 ; ARM78-NEXT: vneg.s32 q8, q8
774 ; ARM78-NEXT: vshl.u32 q8, q9, q8
775 ; ARM78-NEXT: vmov d19, r2, r3
776 ; ARM78-NEXT: vmov d18, r0, r1
777 ; ARM78-NEXT: vtst.32 q8, q8, q9
778 ; ARM78-NEXT: vmvn q8, q8
779 ; ARM78-NEXT: vmovn.i32 d16, q8
780 ; ARM78-NEXT: vmov r0, r1, d16
781 ; ARM78-NEXT: bx lr
782 ;
783 ; THUMB6-LABEL: vec_4xi32_nonsplat_undef1_eq:
784 ; THUMB6: @ %bb.0:
785 ; THUMB6-NEXT: push {r4, lr}
786 ; THUMB6-NEXT: ldr r2, [sp, #8]
787 ; THUMB6-NEXT: lsls r0, r2
788 ; THUMB6-NEXT: movs r2, #1
789 ; THUMB6-NEXT: ands r0, r2
790 ; THUMB6-NEXT: rsbs r4, r0, #0
791 ; THUMB6-NEXT: adcs r0, r4
792 ; THUMB6-NEXT: ldr r4, [sp, #12]
793 ; THUMB6-NEXT: lsls r1, r4
794 ; THUMB6-NEXT: ands r1, r2
795 ; THUMB6-NEXT: rsbs r4, r1, #0
796 ; THUMB6-NEXT: adcs r1, r4
797 ; THUMB6-NEXT: ldr r4, [sp, #20]
798 ; THUMB6-NEXT: lsls r3, r4
799 ; THUMB6-NEXT: ands r3, r2
800 ; THUMB6-NEXT: rsbs r2, r3, #0
801 ; THUMB6-NEXT: adcs r3, r2
802 ; THUMB6-NEXT: pop {r4, pc}
803 ;
804 ; THUMB78-LABEL: vec_4xi32_nonsplat_undef1_eq:
805 ; THUMB78: @ %bb.0:
806 ; THUMB78-NEXT: mov r12, sp
807 ; THUMB78-NEXT: vld1.64 {d16, d17}, [r12]
808 ; THUMB78-NEXT: vmov.i32 q9, #0x1
809 ; THUMB78-NEXT: vneg.s32 q8, q8
810 ; THUMB78-NEXT: vshl.u32 q8, q9, q8
811 ; THUMB78-NEXT: vmov d19, r2, r3
812 ; THUMB78-NEXT: vmov d18, r0, r1
813 ; THUMB78-NEXT: vtst.32 q8, q8, q9
814 ; THUMB78-NEXT: vmvn q8, q8
815 ; THUMB78-NEXT: vmovn.i32 d16, q8
816 ; THUMB78-NEXT: vmov r0, r1, d16
817 ; THUMB78-NEXT: bx lr
818 %t0 = lshr <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %y
819 %t1 = and <4 x i32> %t0, %x
820 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 undef, i32 0>
821 ret <4 x i1> %res
822 }
823 define <4 x i1> @vec_4xi32_nonsplat_undef2_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
824 ; ARM6-LABEL: vec_4xi32_nonsplat_undef2_eq:
825 ; ARM6: @ %bb.0:
826 ; ARM6-NEXT: push {r11, lr}
827 ; ARM6-NEXT: ldr r2, [sp, #12]
828 ; ARM6-NEXT: mov lr, #1
829 ; ARM6-NEXT: ldr r12, [sp, #8]
830 ; ARM6-NEXT: bic r1, lr, r1, lsl r2
831 ; ARM6-NEXT: ldr r2, [sp, #20]
832 ; ARM6-NEXT: bic r0, lr, r0, lsl r12
833 ; ARM6-NEXT: bic r3, lr, r3, lsl r2
834 ; ARM6-NEXT: pop {r11, pc}
835 ;
836 ; ARM78-LABEL: vec_4xi32_nonsplat_undef2_eq:
837 ; ARM78: @ %bb.0:
838 ; ARM78-NEXT: mov r12, sp
839 ; ARM78-NEXT: vld1.64 {d16, d17}, [r12]
840 ; ARM78-NEXT: vmov.i32 q9, #0x1
841 ; ARM78-NEXT: vneg.s32 q8, q8
842 ; ARM78-NEXT: vshl.u32 q8, q9, q8
843 ; ARM78-NEXT: vmov d19, r2, r3
844 ; ARM78-NEXT: vmov d18, r0, r1
845 ; ARM78-NEXT: vtst.32 q8, q8, q9
846 ; ARM78-NEXT: vmvn q8, q8
847 ; ARM78-NEXT: vmovn.i32 d16, q8
848 ; ARM78-NEXT: vmov r0, r1, d16
849 ; ARM78-NEXT: bx lr
850 ;
851 ; THUMB6-LABEL: vec_4xi32_nonsplat_undef2_eq:
852 ; THUMB6: @ %bb.0:
853 ; THUMB6-NEXT: push {r4, lr}
854 ; THUMB6-NEXT: ldr r2, [sp, #8]
855 ; THUMB6-NEXT: lsls r0, r2
856 ; THUMB6-NEXT: movs r2, #1
857 ; THUMB6-NEXT: ands r0, r2
858 ; THUMB6-NEXT: rsbs r4, r0, #0
859 ; THUMB6-NEXT: adcs r0, r4
860 ; THUMB6-NEXT: ldr r4, [sp, #12]
861 ; THUMB6-NEXT: lsls r1, r4
862 ; THUMB6-NEXT: ands r1, r2
863 ; THUMB6-NEXT: rsbs r4, r1, #0
864 ; THUMB6-NEXT: adcs r1, r4
865 ; THUMB6-NEXT: ldr r4, [sp, #20]
866 ; THUMB6-NEXT: lsls r3, r4
867 ; THUMB6-NEXT: ands r3, r2
868 ; THUMB6-NEXT: rsbs r2, r3, #0
869 ; THUMB6-NEXT: adcs r3, r2
870 ; THUMB6-NEXT: pop {r4, pc}
871 ;
872 ; THUMB78-LABEL: vec_4xi32_nonsplat_undef2_eq:
873 ; THUMB78: @ %bb.0:
874 ; THUMB78-NEXT: mov r12, sp
875 ; THUMB78-NEXT: vld1.64 {d16, d17}, [r12]
876 ; THUMB78-NEXT: vmov.i32 q9, #0x1
877 ; THUMB78-NEXT: vneg.s32 q8, q8
878 ; THUMB78-NEXT: vshl.u32 q8, q9, q8
879 ; THUMB78-NEXT: vmov d19, r2, r3
880 ; THUMB78-NEXT: vmov d18, r0, r1
881 ; THUMB78-NEXT: vtst.32 q8, q8, q9
882 ; THUMB78-NEXT: vmvn q8, q8
883 ; THUMB78-NEXT: vmovn.i32 d16, q8
884 ; THUMB78-NEXT: vmov r0, r1, d16
885 ; THUMB78-NEXT: bx lr
886 %t0 = lshr <4 x i32> <i32 1, i32 1, i32 undef, i32 1>, %y
887 %t1 = and <4 x i32> %t0, %x
888 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 undef, i32 0>
889 ret <4 x i1> %res
890 }
892 ;------------------------------------------------------------------------------;
893 ; A special tests
894 ;------------------------------------------------------------------------------;
896 define i1 @scalar_i8_signbit_ne(i8 %x, i8 %y) nounwind {
897 ; ARM-LABEL: scalar_i8_signbit_ne:
898 ; ARM: @ %bb.0:
899 ; ARM-NEXT: uxtb r1, r1
900 ; ARM-NEXT: lsl r0, r0, r1
901 ; ARM-NEXT: uxtb r0, r0
902 ; ARM-NEXT: lsr r0, r0, #7
903 ; ARM-NEXT: bx lr
904 ;
905 ; THUMB-LABEL: scalar_i8_signbit_ne:
906 ; THUMB: @ %bb.0:
907 ; THUMB-NEXT: uxtb r1, r1
908 ; THUMB-NEXT: lsls r0, r1
909 ; THUMB-NEXT: uxtb r0, r0
910 ; THUMB-NEXT: lsrs r0, r0, #7
911 ; THUMB-NEXT: bx lr
912 %t0 = lshr i8 128, %y
913 %t1 = and i8 %t0, %x
914 %res = icmp ne i8 %t1, 0 ; we are perfectly happy with 'ne' predicate
915 ret i1 %res
916 }
918 ;------------------------------------------------------------------------------;
919 ; What if X is a constant too?
920 ;------------------------------------------------------------------------------;
922 define i1 @scalar_i32_x_is_const_eq(i32 %y) nounwind {
923 ; ARM6-LABEL: scalar_i32_x_is_const_eq:
924 ; ARM6: @ %bb.0:
925 ; ARM6-NEXT: ldr r1, .LCPI18_0
926 ; ARM6-NEXT: mov r2, #1
927 ; ARM6-NEXT: bic r0, r2, r1, lsr r0
928 ; ARM6-NEXT: bx lr
929 ; ARM6-NEXT: .p2align 2
930 ; ARM6-NEXT: @ %bb.1:
931 ; ARM6-NEXT: .LCPI18_0:
932 ; ARM6-NEXT: .long 2857740885 @ 0xaa55aa55
933 ;
934 ; ARM78-LABEL: scalar_i32_x_is_const_eq:
935 ; ARM78: @ %bb.0:
936 ; ARM78-NEXT: movw r1, #43605
937 ; ARM78-NEXT: mov r2, #1
938 ; ARM78-NEXT: movt r1, #43605
939 ; ARM78-NEXT: bic r0, r2, r1, lsr r0
940 ; ARM78-NEXT: bx lr
941 ;
942 ; THUMB6-LABEL: scalar_i32_x_is_const_eq:
943 ; THUMB6: @ %bb.0:
944 ; THUMB6-NEXT: ldr r1, .LCPI18_0
945 ; THUMB6-NEXT: lsrs r1, r0
946 ; THUMB6-NEXT: movs r2, #1
947 ; THUMB6-NEXT: ands r2, r1
948 ; THUMB6-NEXT: rsbs r0, r2, #0
949 ; THUMB6-NEXT: adcs r0, r2
950 ; THUMB6-NEXT: bx lr
951 ; THUMB6-NEXT: .p2align 2
952 ; THUMB6-NEXT: @ %bb.1:
953 ; THUMB6-NEXT: .LCPI18_0:
954 ; THUMB6-NEXT: .long 2857740885 @ 0xaa55aa55
955 ;
956 ; THUMB78-LABEL: scalar_i32_x_is_const_eq:
957 ; THUMB78: @ %bb.0:
958 ; THUMB78-NEXT: movw r1, #43605
959 ; THUMB78-NEXT: movt r1, #43605
960 ; THUMB78-NEXT: lsr.w r0, r1, r0
961 ; THUMB78-NEXT: movs r1, #1
962 ; THUMB78-NEXT: bic.w r0, r1, r0
963 ; THUMB78-NEXT: bx lr
964 %t0 = lshr i32 2857740885, %y
965 %t1 = and i32 %t0, 1
966 %res = icmp eq i32 %t1, 0
967 ret i1 %res
968 }
969 define i1 @scalar_i32_x_is_const2_eq(i32 %y) nounwind {
970 ; ARM6-LABEL: scalar_i32_x_is_const2_eq:
971 ; ARM6: @ %bb.0:
972 ; ARM6-NEXT: ldr r2, .LCPI19_0
973 ; ARM6-NEXT: mov r1, #1
974 ; ARM6-NEXT: and r0, r2, r1, lsr r0
975 ; ARM6-NEXT: clz r0, r0
976 ; ARM6-NEXT: lsr r0, r0, #5
977 ; ARM6-NEXT: bx lr
978 ; ARM6-NEXT: .p2align 2
979 ; ARM6-NEXT: @ %bb.1:
980 ; ARM6-NEXT: .LCPI19_0:
981 ; ARM6-NEXT: .long 2857740885 @ 0xaa55aa55
982 ;
983 ; ARM78-LABEL: scalar_i32_x_is_const2_eq:
984 ; ARM78: @ %bb.0:
985 ; ARM78-NEXT: movw r1, #43605
986 ; ARM78-NEXT: mov r2, #1
987 ; ARM78-NEXT: movt r1, #43605
988 ; ARM78-NEXT: and r0, r1, r2, lsr r0
989 ; ARM78-NEXT: clz r0, r0
990 ; ARM78-NEXT: lsr r0, r0, #5
991 ; ARM78-NEXT: bx lr
992 ;
993 ; THUMB6-LABEL: scalar_i32_x_is_const2_eq:
994 ; THUMB6: @ %bb.0:
995 ; THUMB6-NEXT: movs r1, #1
996 ; THUMB6-NEXT: lsrs r1, r0
997 ; THUMB6-NEXT: ldr r2, .LCPI19_0
998 ; THUMB6-NEXT: ands r2, r1
999 ; THUMB6-NEXT: rsbs r0, r2, #0
1000 ; THUMB6-NEXT: adcs r0, r2
1001 ; THUMB6-NEXT: bx lr
1002 ; THUMB6-NEXT: .p2align 2
1003 ; THUMB6-NEXT: @ %bb.1:
1004 ; THUMB6-NEXT: .LCPI19_0:
1005 ; THUMB6-NEXT: .long 2857740885 @ 0xaa55aa55
1006 ;
1007 ; THUMB78-LABEL: scalar_i32_x_is_const2_eq:
1008 ; THUMB78: @ %bb.0:
1009 ; THUMB78-NEXT: movs r1, #1
1010 ; THUMB78-NEXT: lsr.w r0, r1, r0
1011 ; THUMB78-NEXT: movw r1, #43605
1012 ; THUMB78-NEXT: movt r1, #43605
1013 ; THUMB78-NEXT: ands r0, r1
1014 ; THUMB78-NEXT: clz r0, r0
1015 ; THUMB78-NEXT: lsrs r0, r0, #5
1016 ; THUMB78-NEXT: bx lr
1017 %t0 = lshr i32 1, %y
1018 %t1 = and i32 %t0, 2857740885
1019 %res = icmp eq i32 %t1, 0
1020 ret i1 %res
1021 }
1023 ;------------------------------------------------------------------------------;
1024 ; A few negative tests
1025 ;------------------------------------------------------------------------------;
1027 define i1 @negative_scalar_i8_bitsinmiddle_slt(i8 %x, i8 %y) nounwind {
1028 ; ARM6-LABEL: negative_scalar_i8_bitsinmiddle_slt:
1029 ; ARM6: @ %bb.0:
1030 ; ARM6-NEXT: uxtb r1, r1
1031 ; ARM6-NEXT: mov r2, #24
1032 ; ARM6-NEXT: and r0, r0, r2, lsr r1
1033 ; ARM6-NEXT: sxtb r1, r0
1034 ; ARM6-NEXT: mov r0, #0
1035 ; ARM6-NEXT: cmp r1, #0
1036 ; ARM6-NEXT: movmi r0, #1
1037 ; ARM6-NEXT: bx lr
1038 ;
1039 ; ARM78-LABEL: negative_scalar_i8_bitsinmiddle_slt:
1040 ; ARM78: @ %bb.0:
1041 ; ARM78-NEXT: uxtb r1, r1
1042 ; ARM78-NEXT: mov r2, #24
1043 ; ARM78-NEXT: and r0, r0, r2, lsr r1
1044 ; ARM78-NEXT: sxtb r1, r0
1045 ; ARM78-NEXT: mov r0, #0
1046 ; ARM78-NEXT: cmp r1, #0
1047 ; ARM78-NEXT: movwmi r0, #1
1048 ; ARM78-NEXT: bx lr
1049 ;
1050 ; THUMB6-LABEL: negative_scalar_i8_bitsinmiddle_slt:
1051 ; THUMB6: @ %bb.0:
1052 ; THUMB6-NEXT: uxtb r1, r1
1053 ; THUMB6-NEXT: movs r2, #24
1054 ; THUMB6-NEXT: lsrs r2, r1
1055 ; THUMB6-NEXT: ands r2, r0
1056 ; THUMB6-NEXT: sxtb r0, r2
1057 ; THUMB6-NEXT: cmp r0, #0
1058 ; THUMB6-NEXT: bmi .LBB20_2
1059 ; THUMB6-NEXT: @ %bb.1:
1060 ; THUMB6-NEXT: movs r0, #0
1061 ; THUMB6-NEXT: bx lr
1062 ; THUMB6-NEXT: .LBB20_2:
1063 ; THUMB6-NEXT: movs r0, #1
1064 ; THUMB6-NEXT: bx lr
1065 ;
1066 ; THUMB78-LABEL: negative_scalar_i8_bitsinmiddle_slt:
1067 ; THUMB78: @ %bb.0:
1068 ; THUMB78-NEXT: uxtb r1, r1
1069 ; THUMB78-NEXT: movs r2, #24
1070 ; THUMB78-NEXT: lsr.w r1, r2, r1
1071 ; THUMB78-NEXT: ands r0, r1
1072 ; THUMB78-NEXT: sxtb r1, r0
1073 ; THUMB78-NEXT: movs r0, #0
1074 ; THUMB78-NEXT: cmp r1, #0
1075 ; THUMB78-NEXT: it mi
1076 ; THUMB78-NEXT: movmi r0, #1
1077 ; THUMB78-NEXT: bx lr
1078 %t0 = lshr i8 24, %y
1079 %t1 = and i8 %t0, %x
1080 %res = icmp slt i8 %t1, 0
1081 ret i1 %res
1082 }
1084 define i1 @scalar_i8_signbit_eq_with_nonzero(i8 %x, i8 %y) nounwind {
1085 ; ARM-LABEL: scalar_i8_signbit_eq_with_nonzero:
1086 ; ARM: @ %bb.0:
1087 ; ARM-NEXT: uxtb r1, r1
1088 ; ARM-NEXT: mov r2, #128
1089 ; ARM-NEXT: and r0, r0, r2, lsr r1
1090 ; ARM-NEXT: mvn r1, #0
1091 ; ARM-NEXT: uxtab r0, r1, r0
1092 ; ARM-NEXT: clz r0, r0
1093 ; ARM-NEXT: lsr r0, r0, #5
1094 ; ARM-NEXT: bx lr
1095 ;
1096 ; THUMB6-LABEL: scalar_i8_signbit_eq_with_nonzero:
1097 ; THUMB6: @ %bb.0:
1098 ; THUMB6-NEXT: uxtb r1, r1
1099 ; THUMB6-NEXT: movs r2, #128
1100 ; THUMB6-NEXT: lsrs r2, r1
1101 ; THUMB6-NEXT: ands r2, r0
1102 ; THUMB6-NEXT: uxtb r0, r2
1103 ; THUMB6-NEXT: subs r1, r0, #1
1104 ; THUMB6-NEXT: rsbs r0, r1, #0
1105 ; THUMB6-NEXT: adcs r0, r1
1106 ; THUMB6-NEXT: bx lr
1107 ;
1108 ; THUMB78-LABEL: scalar_i8_signbit_eq_with_nonzero:
1109 ; THUMB78: @ %bb.0:
1110 ; THUMB78-NEXT: uxtb r1, r1
1111 ; THUMB78-NEXT: movs r2, #128
1112 ; THUMB78-NEXT: lsr.w r1, r2, r1
1113 ; THUMB78-NEXT: ands r0, r1
1114 ; THUMB78-NEXT: mov.w r1, #-1
1115 ; THUMB78-NEXT: uxtab r0, r1, r0
1116 ; THUMB78-NEXT: clz r0, r0
1117 ; THUMB78-NEXT: lsrs r0, r0, #5
1118 ; THUMB78-NEXT: bx lr
1119 %t0 = lshr i8 128, %y
1120 %t1 = and i8 %t0, %x
1121 %res = icmp eq i8 %t1, 1 ; should be comparing with 0
1122 ret i1 %res
1123 }