1 ; RUN: llc < %s -mtriple=arm-none-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s --check-prefix=ACORE
2 ; RUN: not llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m4 2>&1 | FileCheck %s --check-prefix=MCORE
4 ; MCORE: LLVM ERROR: Invalid register name "cpsr".
6 define i32 @read_cpsr() nounwind {
7 ; ACORE-LABEL: read_cpsr:
9 %reg = call i32 @llvm.read_register.i32(metadata !1)
13 define i32 @read_aclass_registers() nounwind {
15 ; ACORE-LABEL: read_aclass_registers:
19 %0 = call i32 @llvm.read_register.i32(metadata !0)
20 %1 = call i32 @llvm.read_register.i32(metadata !1)
21 %add1 = add i32 %1, %0
22 %2 = call i32 @llvm.read_register.i32(metadata !2)
23 %add2 = add i32 %add1, %2
27 define void @write_aclass_registers(i32 %x) nounwind {
29 ; ACORE-LABEL: write_aclass_registers:
30 ; ACORE: msr APSR_nzcvq, r0
31 ; ACORE: msr APSR_g, r0
32 ; ACORE: msr APSR_nzcvqg, r0
33 ; ACORE: msr CPSR_c, r0
34 ; ACORE: msr CPSR_x, r0
35 ; ACORE: msr APSR_g, r0
36 ; ACORE: msr APSR_nzcvq, r0
37 ; ACORE: msr CPSR_fsxc, r0
38 ; ACORE: msr SPSR_c, r0
39 ; ACORE: msr SPSR_x, r0
40 ; ACORE: msr SPSR_s, r0
41 ; ACORE: msr SPSR_f, r0
42 ; ACORE: msr SPSR_fsxc, r0
44 call void @llvm.write_register.i32(metadata !3, i32 %x)
45 call void @llvm.write_register.i32(metadata !4, i32 %x)
46 call void @llvm.write_register.i32(metadata !5, i32 %x)
47 call void @llvm.write_register.i32(metadata !6, i32 %x)
48 call void @llvm.write_register.i32(metadata !7, i32 %x)
49 call void @llvm.write_register.i32(metadata !8, i32 %x)
50 call void @llvm.write_register.i32(metadata !9, i32 %x)
51 call void @llvm.write_register.i32(metadata !10, i32 %x)
52 call void @llvm.write_register.i32(metadata !11, i32 %x)
53 call void @llvm.write_register.i32(metadata !12, i32 %x)
54 call void @llvm.write_register.i32(metadata !13, i32 %x)
55 call void @llvm.write_register.i32(metadata !14, i32 %x)
56 call void @llvm.write_register.i32(metadata !15, i32 %x)
60 declare i32 @llvm.read_register.i32(metadata) nounwind
61 declare void @llvm.write_register.i32(metadata, i32) nounwind
68 !5 = !{!"apsr_nzcvqg"}