[MIParser] Set RegClassOrRegBank during instruction parsing
[llvm-complete.git] / test / CodeGen / ARM / v6m-umul-with-overflow.ll
blob4e3146d711024d30b42fcba88194f2ec44f2a849
1 ; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s
3 define i1 @unsigned_multiplication_did_overflow(i32, i32) {
4 ; CHECK-LABEL: unsigned_multiplication_did_overflow:
5 entry-block:
6   %2 = tail call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %0, i32 %1)
7   %3 = extractvalue { i32, i1 } %2, 1
8   ret i1 %3
10 ; CHECK: mov{{s?}}    r2, r1
11 ; CHECK: mov{{s?}}    r1, #0
12 ; CHECK: mov{{s?}}    r3, {{#0|r1}}
13 ; CHECK: bl     __aeabi_lmul
16 declare { i32, i1 } @llvm.umul.with.overflow.i32(i32, i32)