1 ; RUN: llc -march=hexagon -hexagon-bit=0 < %s | FileCheck %s
2 ; Optimized bitwise operations.
4 define i32 @my_clrbit(i32 %x) nounwind {
6 ; CHECK-LABEL: my_clrbit
7 ; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}},#31)
8 %x.addr = alloca i32, align 4
9 store i32 %x, i32* %x.addr, align 4
10 %0 = load i32, i32* %x.addr, align 4
11 %and = and i32 %0, 2147483647
15 define i64 @my_clrbit2(i64 %x) nounwind {
17 ; CHECK-LABEL: my_clrbit2
18 ; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}},#31)
19 %x.addr = alloca i64, align 8
20 store i64 %x, i64* %x.addr, align 8
21 %0 = load i64, i64* %x.addr, align 8
22 %and = and i64 %0, -2147483649
26 define i64 @my_clrbit3(i64 %x) nounwind {
28 ; CHECK-LABEL: my_clrbit3
29 ; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}},#31)
30 %x.addr = alloca i64, align 8
31 store i64 %x, i64* %x.addr, align 8
32 %0 = load i64, i64* %x.addr, align 8
33 %and = and i64 %0, 9223372036854775807
37 define i32 @my_clrbit4(i32 %x) nounwind {
39 ; CHECK-LABEL: my_clrbit4
40 ; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}},#13)
41 %x.addr = alloca i32, align 4
42 store i32 %x, i32* %x.addr, align 4
43 %0 = load i32, i32* %x.addr, align 4
44 %and = and i32 %0, -8193
48 define i64 @my_clrbit5(i64 %x) nounwind {
50 ; CHECK-LABEL: my_clrbit5
51 ; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}},#13)
52 %x.addr = alloca i64, align 8
53 store i64 %x, i64* %x.addr, align 8
54 %0 = load i64, i64* %x.addr, align 8
55 %and = and i64 %0, -8193
59 define i64 @my_clrbit6(i64 %x) nounwind {
61 ; CHECK-LABEL: my_clrbit6
62 ; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}},#27)
63 %x.addr = alloca i64, align 8
64 store i64 %x, i64* %x.addr, align 8
65 %0 = load i64, i64* %x.addr, align 8
66 %and = and i64 %0, -576460752303423489
70 define zeroext i16 @my_setbit(i16 zeroext %crc) nounwind {
72 ; CHECK-LABEL: my_setbit
73 ; CHECK: r{{[0-9]+}} = setbit(r{{[0-9]+}},#15)
74 %crc.addr = alloca i16, align 2
75 store i16 %crc, i16* %crc.addr, align 2
76 %0 = load i16, i16* %crc.addr, align 2
77 %conv = zext i16 %0 to i32
78 %or = or i32 %conv, 32768
79 %conv1 = trunc i32 %or to i16
80 store i16 %conv1, i16* %crc.addr, align 2
81 %1 = load i16, i16* %crc.addr, align 2
85 define i32 @my_setbit2(i32 %x) nounwind {
87 ; CHECK-LABEL: my_setbit2
88 ; CHECK: r{{[0-9]+}} = setbit(r{{[0-9]+}},#15)
89 %x.addr = alloca i32, align 4
90 store i32 %x, i32* %x.addr, align 4
91 %0 = load i32, i32* %x.addr, align 4
92 %or = or i32 %0, 32768
96 define i64 @my_setbit3(i64 %x) nounwind {
98 ; CHECK-LABEL: my_setbit3
99 ; CHECK: r{{[0-9]+}} = setbit(r{{[0-9]+}},#15)
100 %x.addr = alloca i64, align 8
101 store i64 %x, i64* %x.addr, align 8
102 %0 = load i64, i64* %x.addr, align 8
103 %or = or i64 %0, 32768
107 define i32 @my_setbit4(i32 %x) nounwind {
109 ; CHECK-LABEL: my_setbit4
110 ; CHECK: r{{[0-9]+}} = setbit(r{{[0-9]+}},#31)
111 %x.addr = alloca i32, align 4
112 store i32 %x, i32* %x.addr, align 4
113 %0 = load i32, i32* %x.addr, align 4
114 %or = or i32 %0, -2147483648
118 define i64 @my_setbit5(i64 %x) nounwind {
120 ; CHECK-LABEL: my_setbit5
121 ; CHECK: r{{[0-9]+}} = setbit(r{{[0-9]+}},#13)
122 %x.addr = alloca i64, align 8
123 store i64 %x, i64* %x.addr, align 8
124 %0 = load i64, i64* %x.addr, align 8
125 %or = or i64 %0, 35184372088832
129 define zeroext i16 @my_togglebit(i16 zeroext %crc) nounwind {
131 ; CHECK-LABEL: my_togglebit
132 ; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}},#15)
133 %crc.addr = alloca i16, align 2
134 store i16 %crc, i16* %crc.addr, align 2
135 %0 = load i16, i16* %crc.addr, align 2
136 %conv = zext i16 %0 to i32
137 %xor = xor i32 %conv, 32768
138 %conv1 = trunc i32 %xor to i16
139 store i16 %conv1, i16* %crc.addr, align 2
140 %1 = load i16, i16* %crc.addr, align 2
144 define i32 @my_togglebit2(i32 %x) nounwind {
146 ; CHECK-LABEL: my_togglebit2
147 ; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}},#15)
148 %x.addr = alloca i32, align 4
149 store i32 %x, i32* %x.addr, align 4
150 %0 = load i32, i32* %x.addr, align 4
151 %xor = xor i32 %0, 32768
155 define i64 @my_togglebit3(i64 %x) nounwind {
157 ; CHECK-LABEL: my_togglebit3
158 ; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}},#15)
159 %x.addr = alloca i64, align 8
160 store i64 %x, i64* %x.addr, align 8
161 %0 = load i64, i64* %x.addr, align 8
162 %xor = xor i64 %0, 32768
166 define i64 @my_togglebit4(i64 %x) nounwind {
168 ; CHECK-LABEL: my_togglebit4
169 ; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}},#20)
170 %x.addr = alloca i64, align 8
171 store i64 %x, i64* %x.addr, align 8
172 %0 = load i64, i64* %x.addr, align 8
173 %xor = xor i64 %0, 4503599627370496