1 ; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
2 ; Check that we generate conversion from single precision floating point
3 ; to 64-bit int value in IEEE complaint mode in V5.
5 ; CHECK: r{{[0-9]+}}:{{[0-9]+}} = convert_sf2d(r{{[0-9]+}})
7 define i32 @main() nounwind {
9 %retval = alloca i32, align 4
10 %i = alloca i64, align 8
11 %a = alloca float, align 4
12 %b = alloca float, align 4
13 %c = alloca float, align 4
14 store i32 0, i32* %retval
15 store float 0x402ECCCCC0000000, float* %a, align 4
16 store float 0x4022333340000000, float* %b, align 4
17 %0 = load float, float* %a, align 4
18 %1 = load float, float* %b, align 4
19 %add = fadd float %0, %1
20 store volatile float %add, float* %c, align 4
21 %2 = load volatile float, float* %c, align 4
22 %conv = fptosi float %2 to i64
23 store i64 %conv, i64* %i, align 8
24 %3 = load i64, i64* %i, align 8
25 %conv1 = trunc i64 %3 to i32