1 ; RUN: llc -march=hexagon < %s | FileCheck %s
3 target triple = "hexagon"
7 define void @dc00(i8* nocapture readonly %p) local_unnamed_addr #0 {
8 tail call void @llvm.hexagon.prefetch(i8* %p)
14 define void @dc01(i8* nocapture readonly %p) local_unnamed_addr #0 {
16 tail call void @llvm.hexagon.Y2.dccleana(i8* %p)
22 define void @dc02(i8* nocapture readonly %p) local_unnamed_addr #0 {
24 tail call void @llvm.hexagon.Y2.dccleaninva(i8* %p)
30 define void @dc03(i8* nocapture readonly %p) local_unnamed_addr #0 {
32 tail call void @llvm.hexagon.Y2.dcinva(i8* %p)
38 define void @dc04(i8* nocapture %p) local_unnamed_addr #0 {
40 tail call void @llvm.hexagon.Y2.dczeroa(i8* %p)
45 ; CHECK: l2fetch(r{{[0-9]+}},r{{[0-9]+}})
46 define void @dc05(i8* nocapture readonly %p, i32 %q) local_unnamed_addr #0 {
48 tail call void @llvm.hexagon.Y4.l2fetch(i8* %p, i32 %q)
53 ; CHECK: l2fetch(r{{[0-9]+}},r{{[0-9]+}}:{{[0-9]+}})
54 define void @dc06(i8* nocapture readonly %p, i64 %q) local_unnamed_addr #0 {
56 tail call void @llvm.hexagon.Y5.l2fetch(i8* %p, i64 %q)
60 declare void @llvm.hexagon.prefetch(i8* nocapture) #1
61 declare void @llvm.hexagon.Y2.dccleana(i8* nocapture readonly) #2
62 declare void @llvm.hexagon.Y2.dccleaninva(i8* nocapture readonly) #2
63 declare void @llvm.hexagon.Y2.dcinva(i8* nocapture readonly) #2
64 declare void @llvm.hexagon.Y2.dczeroa(i8* nocapture) #3
65 declare void @llvm.hexagon.Y4.l2fetch(i8* nocapture readonly, i32) #2
66 declare void @llvm.hexagon.Y5.l2fetch(i8* nocapture readonly, i64) #2
68 attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" }
69 attributes #1 = { inaccessiblemem_or_argmemonly nounwind }
70 attributes #2 = { nounwind }
71 attributes #3 = { argmemonly nounwind writeonly }