1 ; RUN: llc -enable-aa-sched-mi -march=hexagon -mcpu=hexagonv5 -rdf-opt=0 \
2 ; RUN: < %s | FileCheck %s
5 ; CHECK: = memd([[REG0:(r[0-9]+)]]++#8)
6 ; CHECK-NOT: memw([[REG0]]+#0) =
10 define void @f0(i32* %a0) #0 {
12 store i32 -1, i32* %a0, align 8, !tbaa !0
22 %v0 = extractelement <2 x i32> %v6, i32 1
23 br i1 undef, label %b2, label %b1
25 b4: ; preds = %b4, %b0
26 %v1 = phi <2 x i32> [ %v6, %b4 ], [ zeroinitializer, %b0 ]
27 %v2 = phi i32* [ %v9, %b4 ], [ %a0, %b0 ]
28 %v3 = phi i32 [ %v7, %b4 ], [ 0, %b0 ]
29 %v4 = bitcast i32* %v2 to <2 x i32>*
30 %v5 = load <2 x i32>, <2 x i32>* %v4, align 8
31 %v6 = add <2 x i32> %v5, %v1
32 %v7 = add nsw i32 %v3, 2
33 %v8 = icmp slt i32 %v3, 4
34 %v9 = getelementptr i32, i32* %v2, i32 2
35 br i1 %v8, label %b4, label %b3
38 attributes #0 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
42 !2 = !{!"omnipotent char", !3}
43 !3 = !{!"Simple C/C++ TBAA"}