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[MIParser] Set RegClassOrRegBank during instruction parsing
[llvm-complete.git]
/
test
/
CodeGen
/
Hexagon
/
predicate-copy.ll
blob
1b58ec9e790871bc955a3218559d48f6f02e278f
1
; RUN: llc -march=hexagon -O3 < %s | FileCheck %s
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; CHECK: r{{[0-9]+}} = p{{[0-9]+}}
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define i1 @f0() #0 {
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b0:
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ret i1 false
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv5" }