1 ; RUN: llc -O3 -march=hexagon < %s | FileCheck %s
2 ; CHECK: v{{[0-9]+}} = vmem(r{{[0-9]+}}+#0)
4 target triple = "hexagon"
6 ; Function Attrs: nounwind
7 define void @f0(i16* nocapture %a0) #0 {
9 br i1 undef, label %b1, label %b5
12 %v0 = bitcast i16* %a0 to <16 x i32>*
15 b2: ; preds = %b4, %b1
16 %v1 = phi i32 [ 0, %b1 ], [ %v50, %b4 ]
17 %v2 = phi <16 x i32>* [ %v0, %b1 ], [ undef, %b4 ]
20 b3: ; preds = %b3, %b2
21 %v3 = phi i32 [ -4, %b2 ], [ %v40, %b3 ]
23 %v5 = getelementptr inbounds i8, i8* null, i32 %v4
24 %v6 = bitcast i8* %v5 to <16 x i32>*
25 %v7 = load <16 x i32>, <16 x i32>* %v6, align 64, !tbaa !0
26 %v8 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> undef, <16 x i32> %v7, i32 4)
27 %v9 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32> %v8, <16 x i32> zeroinitializer)
28 %v10 = tail call <512 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> %v9, <16 x i32> undef)
29 %v11 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<512 x i1> %v10, <16 x i32> undef, <16 x i32> undef)
30 %v12 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<512 x i1> zeroinitializer, <16 x i32> %v11, <16 x i32> undef)
31 %v13 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<512 x i1> undef, <16 x i32> %v12, <16 x i32> undef)
32 %v14 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> undef, <16 x i32> undef, i32 1)
33 %v15 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32> %v14, <16 x i32> zeroinitializer)
34 %v16 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32> zeroinitializer, <16 x i32> zeroinitializer)
35 %v17 = tail call <512 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> zeroinitializer, <16 x i32> undef)
36 %v18 = tail call <512 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> %v15, <16 x i32> undef)
37 %v19 = tail call <512 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> zeroinitializer, <16 x i32> undef)
38 %v20 = tail call <512 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> %v16, <16 x i32> undef)
39 %v21 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<512 x i1> %v19, <16 x i32> undef, <16 x i32> zeroinitializer)
40 %v22 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<512 x i1> %v20, <16 x i32> undef, <16 x i32> zeroinitializer)
41 %v23 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v22, <16 x i32> %v21)
42 %v24 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> zeroinitializer, <32 x i32> %v23, i32 16843009)
43 %v25 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<512 x i1> %v17, <16 x i32> %v13, <16 x i32> undef)
44 %v26 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<512 x i1> %v18, <16 x i32> %v25, <16 x i32> undef)
45 %v27 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<512 x i1> %v19, <16 x i32> %v26, <16 x i32> undef)
46 %v28 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<512 x i1> %v20, <16 x i32> %v27, <16 x i32> undef)
47 %v29 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32> undef, <16 x i32> zeroinitializer)
48 %v30 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32> zeroinitializer, <16 x i32> zeroinitializer)
49 %v31 = tail call <512 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> undef, <16 x i32> undef)
50 %v32 = tail call <512 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> %v29, <16 x i32> undef)
51 %v33 = tail call <512 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> %v30, <16 x i32> undef)
52 %v34 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> %v24, <32 x i32> zeroinitializer, i32 16843009)
53 %v35 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> %v34, <32 x i32> undef, i32 16843009)
54 %v36 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<512 x i1> zeroinitializer, <16 x i32> %v28, <16 x i32> undef)
55 %v37 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<512 x i1> %v31, <16 x i32> %v36, <16 x i32> undef)
56 %v38 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<512 x i1> %v32, <16 x i32> %v37, <16 x i32> undef)
57 %v39 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<512 x i1> %v33, <16 x i32> %v38, <16 x i32> undef)
58 %v40 = add nsw i32 %v3, 3
59 %v41 = icmp eq i32 %v40, 5
60 br i1 %v41, label %b4, label %b3
63 %v42 = phi <16 x i32> [ %v39, %b3 ]
64 %v43 = phi <32 x i32> [ %v35, %b3 ]
65 %v44 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v43)
66 %v45 = tail call <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32> zeroinitializer, <16 x i32> %v44, i32 -2)
67 %v46 = tail call <32 x i32> @llvm.hexagon.V6.vunpackub(<16 x i32> %v42)
68 %v47 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v45)
69 store <16 x i32> %v47, <16 x i32>* %v2, align 64, !tbaa !0
70 %v48 = getelementptr inbounds <16 x i32>, <16 x i32>* null, i32 1
71 %v49 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v46)
72 store <16 x i32> %v49, <16 x i32>* %v48, align 64, !tbaa !0
73 %v50 = add nsw i32 %v1, 1
74 %v51 = icmp slt i32 %v50, 0
75 br i1 %v51, label %b2, label %b5
77 b5: ; preds = %b4, %b0
81 ; Function Attrs: nounwind readnone
82 declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #1
84 ; Function Attrs: nounwind readnone
85 declare <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32>, <16 x i32>) #1
87 ; Function Attrs: nounwind readnone
88 declare <512 x i1> @llvm.hexagon.V6.vgtub(<16 x i32>, <16 x i32>) #1
90 ; Function Attrs: nounwind readnone
91 declare <16 x i32> @llvm.hexagon.V6.vmux(<512 x i1>, <16 x i32>, <16 x i32>) #1
93 ; Function Attrs: nounwind readnone
94 declare <16 x i32> @llvm.hexagon.V6.vaddbnq(<512 x i1>, <16 x i32>, <16 x i32>) #1
96 ; Function Attrs: nounwind readnone
97 declare <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32>, <16 x i32>, i32) #1
99 ; Function Attrs: nounwind readnone
100 declare <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32>, <16 x i32>, i32) #1
102 ; Function Attrs: nounwind readnone
103 declare <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32>, <32 x i32>, i32) #1
105 ; Function Attrs: nounwind readnone
106 declare <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32>, <16 x i32>, i32) #1
108 ; Function Attrs: nounwind readnone
109 declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
111 ; Function Attrs: nounwind readnone
112 declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1
114 ; Function Attrs: nounwind readnone
115 declare <32 x i32> @llvm.hexagon.V6.vunpackub(<16 x i32>) #1
117 attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
118 attributes #1 = { nounwind readnone }
120 !0 = !{!1, !1, i64 0}
121 !1 = !{!"omnipotent char", !2, i64 0}
122 !2 = !{!"Simple C/C++ TBAA"}