[MIParser] Set RegClassOrRegBank during instruction parsing
[llvm-complete.git] / test / CodeGen / Hexagon / switch-lut-function-section.ll
blob542bfbb6d667891d40f94e186edae980275cb331
1 ;RUN: llc -O2 -hexagon-emit-lut-text=true -function-sections < %s | FileCheck --check-prefix=FUNCTEXT %s
3 ;This test checks the placement of lookup table in function's text section.
4 target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
5 target triple = "hexagon-unknown--elf"
7 ;FUNCTEXT: .text
8 ;FUNCTEXT: .section{{.*}}text.foo,
9 ;FUNCTEXT-NOT: .section{{.*}}.rodata
10 ;FUNCTEXT: .Lswitch.table:
11 ;FUNCTEXT-NEXT: .word
13 @switch.table = private unnamed_addr constant [9 x i32] [i32 9, i32 20, i32 14, i32 22, i32 12, i32 5, i32 98, i32 8, i32 11] #0
15 ; Function Attrs: norecurse nounwind readnone
16 define i32 @foo(i32 %x) local_unnamed_addr #0 {
17 entry:
18   %0 = icmp ult i32 %x, 9
19   br i1 %0, label %switch.lookup, label %return
21 switch.lookup:                                    ; preds = %entry
22   %switch.gep = getelementptr inbounds [9 x i32], [9 x i32]* @switch.table, i32 0, i32 %x
23   %switch.load = load i32, i32* %switch.gep, align 4
24   ret i32 %switch.load
26 return:                                           ; preds = %entry
27   ret i32 19
30 attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" }