1 ; RUN: llc -march=hexagon < %s -pipeliner-experimental-cg=true | FileCheck %s
3 ; Test that the pipeliner cause an assert and correctly pipelines the
6 ; CHECK: loop0(.LBB0_[[LOOP:.]],
7 ; CHECK: .LBB0_[[LOOP]]:
8 ; CHECK: [[REG0:r([0-9]+)]] = sath([[REG1:r([0-9]+)]])
9 ; CHECK: memh(r{{[0-9]+}}++#2) = [[REG0]].new
13 define void @f0(i16* nocapture %a0, float* nocapture readonly %a1, float %a2, i32 %a3) {
15 %v0 = icmp sgt i32 %a3, 0
16 br i1 %v0, label %b1, label %b2
18 b1: ; preds = %b1, %b0
19 %v1 = phi i32 [ %v11, %b1 ], [ 0, %b0 ]
20 %v2 = phi i16* [ %v10, %b1 ], [ %a0, %b0 ]
21 %v3 = phi float* [ %v4, %b1 ], [ %a1, %b0 ]
22 %v4 = getelementptr inbounds float, float* %v3, i32 1
23 %v5 = load float, float* %v3, align 4, !tbaa !0
24 %v6 = fmul float %v5, %a2
25 %v7 = tail call i32 @llvm.hexagon.F2.conv.sf2w(float %v6)
26 %v8 = tail call i32 @llvm.hexagon.A2.sath(i32 %v7)
27 %v9 = trunc i32 %v8 to i16
28 %v10 = getelementptr inbounds i16, i16* %v2, i32 1
29 store i16 %v9, i16* %v2, align 2, !tbaa !4
30 %v11 = add nuw nsw i32 %v1, 1
31 %v12 = icmp eq i32 %v11, %a3
32 br i1 %v12, label %b2, label %b1
34 b2: ; preds = %b1, %b0
38 ; Function Attrs: nounwind readnone
39 declare i32 @llvm.hexagon.A2.sath(i32) #0
41 ; Function Attrs: nounwind readnone
42 declare i32 @llvm.hexagon.F2.conv.sf2w(float) #0
44 attributes #0 = { nounwind readnone }
47 !1 = !{!"float", !2, i64 0}
48 !2 = !{!"omnipotent char", !3, i64 0}
49 !3 = !{!"Simple C/C++ TBAA"}
51 !5 = !{!"short", !2, i64 0}