1 ; RUN: llc -march=hexagon -enable-pipeliner < %s
4 ; Function Attrs: nounwind
7 br i1 undef, label %b1, label %b3
12 b2: ; preds = %b2, %b1
13 %v0 = phi i32 [ 0, %b1 ], [ %v9, %b2 ]
14 %v1 = phi <16 x i32> [ undef, %b1 ], [ %v2, %b2 ]
15 %v2 = phi <16 x i32> [ undef, %b1 ], [ %v4, %b2 ]
16 %v3 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v2, <16 x i32> %v1, i32 62)
17 %v4 = tail call <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32> undef, <16 x i32> zeroinitializer)
18 %v5 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v4, <16 x i32> %v2, i32 2)
19 %v6 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> undef, <16 x i32> %v3)
20 %v7 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v6, <16 x i32> %v5)
21 %v8 = tail call <16 x i32> @llvm.hexagon.V6.vabsh(<16 x i32> %v7)
22 store <16 x i32> %v8, <16 x i32>* undef, align 64
23 %v9 = add nsw i32 %v0, 1
24 %v10 = icmp slt i32 %v9, undef
25 br i1 %v10, label %b2, label %b3
27 b3: ; preds = %b2, %b0
31 ; Function Attrs: nounwind readnone
32 declare <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32>, <16 x i32>) #1
34 ; Function Attrs: nounwind readnone
35 declare <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32>, <16 x i32>) #1
37 ; Function Attrs: nounwind readnone
38 declare <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32>, <16 x i32>, i32) #1
40 ; Function Attrs: nounwind readnone
41 declare <16 x i32> @llvm.hexagon.V6.vabsh(<16 x i32>) #1
43 attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
44 attributes #1 = { nounwind readnone }