1 ; RUN: llc -march=hexagon -disable-hexagon-peephole < %s | FileCheck %s
3 ; Test that we're generating a 32-bit multiply high instead of a 64-bit version,
4 ; when using the high 32-bits only.
7 ; CHECK-NOT: r{{[0-9]+}}:{{[0-9]+}} = mpy(
8 define void @f0(i32* nocapture readonly %a0, i32* nocapture %a1) #0 {
10 %v0 = getelementptr i32, i32* %a1, i32 448
13 b1: ; preds = %b1, %b0
14 br i1 undef, label %b2, label %b1
17 %v1 = getelementptr inbounds i32, i32* %a0, i32 64
18 %v2 = load i32, i32* %a0, align 4
19 %v3 = getelementptr inbounds i32, i32* %a0, i32 2
20 %v4 = load i32, i32* %v1, align 4
21 %v5 = sext i32 %v2 to i64
22 %v6 = sext i32 %v4 to i64
23 %v7 = mul nsw i64 %v6, %v5
24 %v8 = lshr i64 %v7, 32
25 %v9 = trunc i64 %v8 to i32
26 %v10 = sub nsw i32 0, %v9
27 %v11 = getelementptr inbounds i32, i32* %v0, i32 1
28 store i32 %v10, i32* %v1, align 4
32 ; Similar to above, but using the operands of the multiply are expressions.
35 ; CHECK: r{{[0-9]+}} = mpy(
36 define void @f1(i32 %a0, i32 %a1, i32* nocapture readonly %a2, i32* nocapture %a3) #0 {
38 %v0 = getelementptr i32, i32* %a3, i32 448
41 b1: ; preds = %b1, %b0
42 br i1 undef, label %b2, label %b1
45 %v1 = getelementptr inbounds i32, i32* %a2, i32 64
46 %v2 = sext i32 %a0 to i64
47 %v3 = sext i32 %a1 to i64
48 %v4 = mul nsw i64 %v3, %v2
49 %v5 = lshr i64 %v4, 32
50 %v6 = trunc i64 %v5 to i32
51 %v7 = sub nsw i32 0, %v6
52 %v8 = getelementptr inbounds i32, i32* %v0, i32 1
53 store i32 %v7, i32* %v1, align 4
57 ; Check that the transform occurs when the loads can be post-incremented.
60 ; CHECK: r{{[0-9]+}} = mpy(
61 define void @f2(i32* nocapture readonly %a0, i32* nocapture %a1) #0 {
63 %v0 = getelementptr i32, i32* %a1, i32 448
67 %v1 = getelementptr inbounds i32, i32* %a0, i32 64
70 b2: ; preds = %b2, %b1
71 %v2 = phi i32* [ %v0, %b1 ], [ %v14, %b2 ]
72 %v3 = phi i32* [ %v1, %b1 ], [ undef, %b2 ]
73 %v4 = phi i32* [ null, %b1 ], [ %v6, %b2 ]
74 %v5 = load i32, i32* %v4, align 4
75 %v6 = getelementptr inbounds i32, i32* %v4, i32 2
76 %v7 = load i32, i32* %v3, align 4
77 %v8 = sext i32 %v5 to i64
78 %v9 = sext i32 %v7 to i64
79 %v10 = mul nsw i64 %v9, %v8
80 %v11 = lshr i64 %v10, 32
81 %v12 = trunc i64 %v11 to i32
82 %v13 = sub nsw i32 0, %v12
83 %v14 = getelementptr inbounds i32, i32* %v2, i32 1
84 store i32 %v13, i32* %v2, align 4
88 attributes #0 = { nounwind "target-cpu"="hexagonv55" }