1 ; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
3 ; CHECK: r{{[0-9]*}} += rol(r{{[0-9]*}},#31)
4 ; CHECK: r{{[0-9]*}} &= rol(r{{[0-9]*}},#31)
5 ; CHECK: r{{[0-9]*}} -= rol(r{{[0-9]*}},#31)
6 ; CHECK: r{{[0-9]*}} |= rol(r{{[0-9]*}},#31)
7 ; CHECK: r{{[0-9]*}} ^= rol(r{{[0-9]*}},#31)
9 target triple = "hexagon"
11 @g0 = common global i32 0, align 4
12 @g1 = common global i32 0, align 4
13 @g2 = common global i32 0, align 4
14 @g3 = common global i32 0, align 4
15 @g4 = common global i32 0, align 4
17 ; Function Attrs: nounwind
20 %v0 = alloca i32, align 4
21 %v1 = alloca i32, align 4
23 store i32 0, i32* %v1, align 4
24 %v2 = call i32 @llvm.hexagon.S6.rol.i.r.acc(i32 0, i32 1, i32 31)
25 store i32 %v2, i32* @g0, align 4
26 %v3 = call i32 @llvm.hexagon.S6.rol.i.r.and(i32 0, i32 1, i32 31)
27 store i32 %v3, i32* @g1, align 4
28 %v4 = call i32 @llvm.hexagon.S6.rol.i.r.nac(i32 0, i32 1, i32 31)
29 store i32 %v4, i32* @g2, align 4
30 %v5 = call i32 @llvm.hexagon.S6.rol.i.r.or(i32 0, i32 1, i32 31)
31 store i32 %v5, i32* @g3, align 4
32 %v6 = call i32 @llvm.hexagon.S6.rol.i.r.xacc(i32 0, i32 1, i32 31)
33 store i32 %v6, i32* @g4, align 4
37 ; Function Attrs: nounwind readnone
38 declare i32 @llvm.hexagon.S6.rol.i.r.acc(i32, i32, i32) #1
40 ; Function Attrs: nounwind readnone
41 declare i32 @llvm.hexagon.S6.rol.i.r.and(i32, i32, i32) #1
43 ; Function Attrs: nounwind readnone
44 declare i32 @llvm.hexagon.S6.rol.i.r.nac(i32, i32, i32) #1
46 ; Function Attrs: nounwind readnone
47 declare i32 @llvm.hexagon.S6.rol.i.r.or(i32, i32, i32) #1
49 ; Function Attrs: nounwind readnone
50 declare i32 @llvm.hexagon.S6.rol.i.r.xacc(i32, i32, i32) #1
52 attributes #0 = { nounwind "target-cpu"="hexagonv60" }
53 attributes #1 = { nounwind readnone }