1 ; RUN: llc -march=hexagon < %s | FileCheck %s
3 ; Test that we generate a post-increment when using double hvx (128B)
4 ; post-increment operations.
6 ; CHECK: = vmem(r{{[0-9]+}}++#1)
7 ; CHECK: vmem(r{{[0-9]+}}++#1)
9 ; Function Attrs: nounwind
10 define void @f0(i8* noalias nocapture readonly %a0, i8* noalias nocapture %a1, i32 %a2) #0 {
12 %v0 = icmp sgt i32 %a2, 0
13 br i1 %v0, label %b1, label %b3
16 %v1 = bitcast i8* %a0 to <32 x i32>*
17 %v2 = bitcast i8* %a1 to <32 x i32>*
20 b2: ; preds = %b2, %b1
21 %v3 = phi <32 x i32>* [ %v9, %b2 ], [ %v1, %b1 ]
22 %v4 = phi <32 x i32>* [ %v10, %b2 ], [ %v2, %b1 ]
23 %v5 = phi i32 [ %v7, %b2 ], [ 0, %b1 ]
24 %v6 = load <32 x i32>, <32 x i32>* %v3, align 128, !tbaa !0
25 store <32 x i32> %v6, <32 x i32>* %v4, align 128, !tbaa !0
26 %v7 = add nsw i32 %v5, 1
27 %v8 = icmp eq i32 %v7, %a2
28 %v9 = getelementptr <32 x i32>, <32 x i32>* %v3, i32 1
29 %v10 = getelementptr <32 x i32>, <32 x i32>* %v4, i32 1
30 br i1 %v8, label %b3, label %b2
32 b3: ; preds = %b2, %b0
36 attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }
39 !1 = !{!"omnipotent char", !2, i64 0}
40 !2 = !{!"Simple C/C++ TBAA"}