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[MIParser] Set RegClassOrRegBank during instruction parsing
[llvm-complete.git]
/
test
/
CodeGen
/
Hexagon
/
vect
/
vect-vaddh-1.ll
blob
1b43d4fb6cc8615f6940a633b2641b91135c6982
1
; RUN: llc -march=hexagon < %s | FileCheck %s
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; CHECK: vaddh
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define <4 x i16> @t_i4x16(<4 x i16> %a, <4 x i16> %b) nounwind {
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entry:
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%0 = add <4 x i16> %a, %b
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ret <4 x i16> %0
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}