1 ; RUN: llc -march=hexagon -enable-pipeliner -verify-machineinstrs < %s
4 ; This test fails in the machine verifier because the verifier thinks the
5 ; return register is undefined, and because there is a basic block that
6 ; ends with an unconditional branch that is not marked as a barrier.
8 ; Enabling SWP exposes these bugs because the live variable analysis is
9 ; performed earlier than the process implicit def pass. This ordering
10 ; causes the JMPR machine instruction to contain two R0 operands, one
11 ; with an undef and one with a kill flag.
13 @g0 = common global i32 0, align 4
15 ; Function Attrs: nounwind
16 define i32 @f0(i32 %a0) #0 {
18 %v0 = icmp eq i32 %a0, 0
19 br i1 %v0, label %b2, label %b1
22 %v1 = tail call i32 bitcast (i32 (...)* @f1 to i32 (i32)*)(i32 %a0) #0
26 store i32 0, i32* @g0, align 4
29 b3: ; preds = %b2, %b1
35 attributes #0 = { nounwind }