| blob | 3aa384e53084d3515b711bb6cc4d47742e918dc7 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips2 -relocation-model=pic | FileCheck %s \
3 ; RUN: -check-prefix=MIPS
4 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32 -relocation-model=pic | FileCheck %s \
5 ; RUN: -check-prefix=MIPS32
6 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \
7 ; RUN: -check-prefix=32R2
8 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \
9 ; RUN: -check-prefix=32R2
10 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \
11 ; RUN: -check-prefix=32R2
12 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \
13 ; RUN: -check-prefix=32R6
14 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips3 -relocation-model=pic | FileCheck %s \
15 ; RUN: -check-prefix=MIPS3
16 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips4 -relocation-model=pic | FileCheck %s \
17 ; RUN: -check-prefix=MIPS64
18 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64 -relocation-model=pic | FileCheck %s \
19 ; RUN: -check-prefix=MIPS64
20 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \
21 ; RUN: -check-prefix=MIPS64R2
22 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \
23 ; RUN: -check-prefix=MIPS64R2
24 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \
25 ; RUN: -check-prefix=MIPS64R2
26 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \
27 ; RUN: -check-prefix=MIPS64R6
28 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \
29 ; RUN: -check-prefix=MMR3
30 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
31 ; RUN: -check-prefix=MMR6
33 define signext i1 @ashr_i1(i1 signext %a, i1 signext %b) {
34 ; MIPS-LABEL: ashr_i1:
35 ; MIPS: # %bb.0: # %entry
36 ; MIPS-NEXT: jr $ra
37 ; MIPS-NEXT: move $2, $4
38 ;
39 ; MIPS32-LABEL: ashr_i1:
40 ; MIPS32: # %bb.0: # %entry
41 ; MIPS32-NEXT: jr $ra
42 ; MIPS32-NEXT: move $2, $4
43 ;
44 ; 32R2-LABEL: ashr_i1:
45 ; 32R2: # %bb.0: # %entry
46 ; 32R2-NEXT: jr $ra
47 ; 32R2-NEXT: move $2, $4
48 ;
49 ; 32R6-LABEL: ashr_i1:
50 ; 32R6: # %bb.0: # %entry
51 ; 32R6-NEXT: jr $ra
52 ; 32R6-NEXT: move $2, $4
53 ;
54 ; MIPS3-LABEL: ashr_i1:
55 ; MIPS3: # %bb.0: # %entry
56 ; MIPS3-NEXT: jr $ra
57 ; MIPS3-NEXT: move $2, $4
58 ;
59 ; MIPS64-LABEL: ashr_i1:
60 ; MIPS64: # %bb.0: # %entry
61 ; MIPS64-NEXT: jr $ra
62 ; MIPS64-NEXT: move $2, $4
63 ;
64 ; MIPS64R2-LABEL: ashr_i1:
65 ; MIPS64R2: # %bb.0: # %entry
66 ; MIPS64R2-NEXT: jr $ra
67 ; MIPS64R2-NEXT: move $2, $4
68 ;
69 ; MIPS64R6-LABEL: ashr_i1:
70 ; MIPS64R6: # %bb.0: # %entry
71 ; MIPS64R6-NEXT: jr $ra
72 ; MIPS64R6-NEXT: move $2, $4
73 ;
74 ; MMR3-LABEL: ashr_i1:
75 ; MMR3: # %bb.0: # %entry
76 ; MMR3-NEXT: move $2, $4
77 ; MMR3-NEXT: jrc $ra
78 ;
79 ; MMR6-LABEL: ashr_i1:
80 ; MMR6: # %bb.0: # %entry
81 ; MMR6-NEXT: move $2, $4
82 ; MMR6-NEXT: jrc $ra
83 entry:
84 %r = ashr i1 %a, %b
85 ret i1 %r
86 }
88 define signext i8 @ashr_i8(i8 signext %a, i8 signext %b) {
89 ; MIPS-LABEL: ashr_i8:
90 ; MIPS: # %bb.0: # %entry
91 ; MIPS-NEXT: andi $1, $5, 255
92 ; MIPS-NEXT: jr $ra
93 ; MIPS-NEXT: srav $2, $4, $1
94 ;
95 ; MIPS32-LABEL: ashr_i8:
96 ; MIPS32: # %bb.0: # %entry
97 ; MIPS32-NEXT: andi $1, $5, 255
98 ; MIPS32-NEXT: jr $ra
99 ; MIPS32-NEXT: srav $2, $4, $1
100 ;
101 ; 32R2-LABEL: ashr_i8:
102 ; 32R2: # %bb.0: # %entry
103 ; 32R2-NEXT: andi $1, $5, 255
104 ; 32R2-NEXT: jr $ra
105 ; 32R2-NEXT: srav $2, $4, $1
106 ;
107 ; 32R6-LABEL: ashr_i8:
108 ; 32R6: # %bb.0: # %entry
109 ; 32R6-NEXT: andi $1, $5, 255
110 ; 32R6-NEXT: jr $ra
111 ; 32R6-NEXT: srav $2, $4, $1
112 ;
113 ; MIPS3-LABEL: ashr_i8:
114 ; MIPS3: # %bb.0: # %entry
115 ; MIPS3-NEXT: andi $1, $5, 255
116 ; MIPS3-NEXT: jr $ra
117 ; MIPS3-NEXT: srav $2, $4, $1
118 ;
119 ; MIPS64-LABEL: ashr_i8:
120 ; MIPS64: # %bb.0: # %entry
121 ; MIPS64-NEXT: andi $1, $5, 255
122 ; MIPS64-NEXT: jr $ra
123 ; MIPS64-NEXT: srav $2, $4, $1
124 ;
125 ; MIPS64R2-LABEL: ashr_i8:
126 ; MIPS64R2: # %bb.0: # %entry
127 ; MIPS64R2-NEXT: andi $1, $5, 255
128 ; MIPS64R2-NEXT: jr $ra
129 ; MIPS64R2-NEXT: srav $2, $4, $1
130 ;
131 ; MIPS64R6-LABEL: ashr_i8:
132 ; MIPS64R6: # %bb.0: # %entry
133 ; MIPS64R6-NEXT: andi $1, $5, 255
134 ; MIPS64R6-NEXT: jr $ra
135 ; MIPS64R6-NEXT: srav $2, $4, $1
136 ;
137 ; MMR3-LABEL: ashr_i8:
138 ; MMR3: # %bb.0: # %entry
139 ; MMR3-NEXT: andi16 $2, $5, 255
140 ; MMR3-NEXT: jr $ra
141 ; MMR3-NEXT: srav $2, $4, $2
142 ;
143 ; MMR6-LABEL: ashr_i8:
144 ; MMR6: # %bb.0: # %entry
145 ; MMR6-NEXT: andi16 $2, $5, 255
146 ; MMR6-NEXT: srav $2, $4, $2
147 ; MMR6-NEXT: jrc $ra
148 entry:
149 ; FIXME: The andi instruction is redundant.
150 %r = ashr i8 %a, %b
151 ret i8 %r
152 }
154 define signext i16 @ashr_i16(i16 signext %a, i16 signext %b) {
155 ; MIPS-LABEL: ashr_i16:
156 ; MIPS: # %bb.0: # %entry
157 ; MIPS-NEXT: andi $1, $5, 65535
158 ; MIPS-NEXT: jr $ra
159 ; MIPS-NEXT: srav $2, $4, $1
160 ;
161 ; MIPS32-LABEL: ashr_i16:
162 ; MIPS32: # %bb.0: # %entry
163 ; MIPS32-NEXT: andi $1, $5, 65535
164 ; MIPS32-NEXT: jr $ra
165 ; MIPS32-NEXT: srav $2, $4, $1
166 ;
167 ; 32R2-LABEL: ashr_i16:
168 ; 32R2: # %bb.0: # %entry
169 ; 32R2-NEXT: andi $1, $5, 65535
170 ; 32R2-NEXT: jr $ra
171 ; 32R2-NEXT: srav $2, $4, $1
172 ;
173 ; 32R6-LABEL: ashr_i16:
174 ; 32R6: # %bb.0: # %entry
175 ; 32R6-NEXT: andi $1, $5, 65535
176 ; 32R6-NEXT: jr $ra
177 ; 32R6-NEXT: srav $2, $4, $1
178 ;
179 ; MIPS3-LABEL: ashr_i16:
180 ; MIPS3: # %bb.0: # %entry
181 ; MIPS3-NEXT: andi $1, $5, 65535
182 ; MIPS3-NEXT: jr $ra
183 ; MIPS3-NEXT: srav $2, $4, $1
184 ;
185 ; MIPS64-LABEL: ashr_i16:
186 ; MIPS64: # %bb.0: # %entry
187 ; MIPS64-NEXT: andi $1, $5, 65535
188 ; MIPS64-NEXT: jr $ra
189 ; MIPS64-NEXT: srav $2, $4, $1
190 ;
191 ; MIPS64R2-LABEL: ashr_i16:
192 ; MIPS64R2: # %bb.0: # %entry
193 ; MIPS64R2-NEXT: andi $1, $5, 65535
194 ; MIPS64R2-NEXT: jr $ra
195 ; MIPS64R2-NEXT: srav $2, $4, $1
196 ;
197 ; MIPS64R6-LABEL: ashr_i16:
198 ; MIPS64R6: # %bb.0: # %entry
199 ; MIPS64R6-NEXT: andi $1, $5, 65535
200 ; MIPS64R6-NEXT: jr $ra
201 ; MIPS64R6-NEXT: srav $2, $4, $1
202 ;
203 ; MMR3-LABEL: ashr_i16:
204 ; MMR3: # %bb.0: # %entry
205 ; MMR3-NEXT: andi16 $2, $5, 65535
206 ; MMR3-NEXT: jr $ra
207 ; MMR3-NEXT: srav $2, $4, $2
208 ;
209 ; MMR6-LABEL: ashr_i16:
210 ; MMR6: # %bb.0: # %entry
211 ; MMR6-NEXT: andi16 $2, $5, 65535
212 ; MMR6-NEXT: srav $2, $4, $2
213 ; MMR6-NEXT: jrc $ra
214 entry:
215 ; FIXME: The andi instruction is redundant.
216 %r = ashr i16 %a, %b
217 ret i16 %r
218 }
220 define signext i32 @ashr_i32(i32 signext %a, i32 signext %b) {
221 ; MIPS-LABEL: ashr_i32:
222 ; MIPS: # %bb.0: # %entry
223 ; MIPS-NEXT: jr $ra
224 ; MIPS-NEXT: srav $2, $4, $5
225 ;
226 ; MIPS32-LABEL: ashr_i32:
227 ; MIPS32: # %bb.0: # %entry
228 ; MIPS32-NEXT: jr $ra
229 ; MIPS32-NEXT: srav $2, $4, $5
230 ;
231 ; 32R2-LABEL: ashr_i32:
232 ; 32R2: # %bb.0: # %entry
233 ; 32R2-NEXT: jr $ra
234 ; 32R2-NEXT: srav $2, $4, $5
235 ;
236 ; 32R6-LABEL: ashr_i32:
237 ; 32R6: # %bb.0: # %entry
238 ; 32R6-NEXT: jr $ra
239 ; 32R6-NEXT: srav $2, $4, $5
240 ;
241 ; MIPS3-LABEL: ashr_i32:
242 ; MIPS3: # %bb.0: # %entry
243 ; MIPS3-NEXT: jr $ra
244 ; MIPS3-NEXT: srav $2, $4, $5
245 ;
246 ; MIPS64-LABEL: ashr_i32:
247 ; MIPS64: # %bb.0: # %entry
248 ; MIPS64-NEXT: jr $ra
249 ; MIPS64-NEXT: srav $2, $4, $5
250 ;
251 ; MIPS64R2-LABEL: ashr_i32:
252 ; MIPS64R2: # %bb.0: # %entry
253 ; MIPS64R2-NEXT: jr $ra
254 ; MIPS64R2-NEXT: srav $2, $4, $5
255 ;
256 ; MIPS64R6-LABEL: ashr_i32:
257 ; MIPS64R6: # %bb.0: # %entry
258 ; MIPS64R6-NEXT: jr $ra
259 ; MIPS64R6-NEXT: srav $2, $4, $5
260 ;
261 ; MMR3-LABEL: ashr_i32:
262 ; MMR3: # %bb.0: # %entry
263 ; MMR3-NEXT: jr $ra
264 ; MMR3-NEXT: srav $2, $4, $5
265 ;
266 ; MMR6-LABEL: ashr_i32:
267 ; MMR6: # %bb.0: # %entry
268 ; MMR6-NEXT: srav $2, $4, $5
269 ; MMR6-NEXT: jrc $ra
270 entry:
271 %r = ashr i32 %a, %b
272 ret i32 %r
273 }
275 define signext i64 @ashr_i64(i64 signext %a, i64 signext %b) {
276 ; MIPS-LABEL: ashr_i64:
277 ; MIPS: # %bb.0:
278 ; MIPS-NEXT: andi $1, $7, 32
279 ; MIPS-NEXT: bnez $1, $BB4_2
280 ; MIPS-NEXT: srav $3, $4, $7
281 ; MIPS-NEXT: # %bb.1:
282 ; MIPS-NEXT: srlv $1, $5, $7
283 ; MIPS-NEXT: not $2, $7
284 ; MIPS-NEXT: sll $4, $4, 1
285 ; MIPS-NEXT: sllv $2, $4, $2
286 ; MIPS-NEXT: or $1, $2, $1
287 ; MIPS-NEXT: move $2, $3
288 ; MIPS-NEXT: jr $ra
289 ; MIPS-NEXT: move $3, $1
290 ; MIPS-NEXT: $BB4_2:
291 ; MIPS-NEXT: jr $ra
292 ; MIPS-NEXT: sra $2, $4, 31
293 ;
294 ; MIPS32-LABEL: ashr_i64:
295 ; MIPS32: # %bb.0: # %entry
296 ; MIPS32-NEXT: srlv $1, $5, $7
297 ; MIPS32-NEXT: not $2, $7
298 ; MIPS32-NEXT: sll $3, $4, 1
299 ; MIPS32-NEXT: sllv $2, $3, $2
300 ; MIPS32-NEXT: or $3, $2, $1
301 ; MIPS32-NEXT: srav $2, $4, $7
302 ; MIPS32-NEXT: andi $1, $7, 32
303 ; MIPS32-NEXT: movn $3, $2, $1
304 ; MIPS32-NEXT: sra $4, $4, 31
305 ; MIPS32-NEXT: jr $ra
306 ; MIPS32-NEXT: movn $2, $4, $1
307 ;
308 ; 32R2-LABEL: ashr_i64:
309 ; 32R2: # %bb.0: # %entry
310 ; 32R2-NEXT: srlv $1, $5, $7
311 ; 32R2-NEXT: not $2, $7
312 ; 32R2-NEXT: sll $3, $4, 1
313 ; 32R2-NEXT: sllv $2, $3, $2
314 ; 32R2-NEXT: or $3, $2, $1
315 ; 32R2-NEXT: srav $2, $4, $7
316 ; 32R2-NEXT: andi $1, $7, 32
317 ; 32R2-NEXT: movn $3, $2, $1
318 ; 32R2-NEXT: sra $4, $4, 31
319 ; 32R2-NEXT: jr $ra
320 ; 32R2-NEXT: movn $2, $4, $1
321 ;
322 ; 32R6-LABEL: ashr_i64:
323 ; 32R6: # %bb.0: # %entry
324 ; 32R6-NEXT: srav $1, $4, $7
325 ; 32R6-NEXT: andi $3, $7, 32
326 ; 32R6-NEXT: seleqz $2, $1, $3
327 ; 32R6-NEXT: sra $6, $4, 31
328 ; 32R6-NEXT: selnez $6, $6, $3
329 ; 32R6-NEXT: or $2, $6, $2
330 ; 32R6-NEXT: srlv $5, $5, $7
331 ; 32R6-NEXT: not $6, $7
332 ; 32R6-NEXT: sll $4, $4, 1
333 ; 32R6-NEXT: sllv $4, $4, $6
334 ; 32R6-NEXT: or $4, $4, $5
335 ; 32R6-NEXT: seleqz $4, $4, $3
336 ; 32R6-NEXT: selnez $1, $1, $3
337 ; 32R6-NEXT: jr $ra
338 ; 32R6-NEXT: or $3, $1, $4
339 ;
340 ; MIPS3-LABEL: ashr_i64:
341 ; MIPS3: # %bb.0: # %entry
342 ; MIPS3-NEXT: jr $ra
343 ; MIPS3-NEXT: dsrav $2, $4, $5
344 ;
345 ; MIPS64-LABEL: ashr_i64:
346 ; MIPS64: # %bb.0: # %entry
347 ; MIPS64-NEXT: jr $ra
348 ; MIPS64-NEXT: dsrav $2, $4, $5
349 ;
350 ; MIPS64R2-LABEL: ashr_i64:
351 ; MIPS64R2: # %bb.0: # %entry
352 ; MIPS64R2-NEXT: jr $ra
353 ; MIPS64R2-NEXT: dsrav $2, $4, $5
354 ;
355 ; MIPS64R6-LABEL: ashr_i64:
356 ; MIPS64R6: # %bb.0: # %entry
357 ; MIPS64R6-NEXT: jr $ra
358 ; MIPS64R6-NEXT: dsrav $2, $4, $5
359 ;
360 ; MMR3-LABEL: ashr_i64:
361 ; MMR3: # %bb.0: # %entry
362 ; MMR3-NEXT: srlv $2, $5, $7
363 ; MMR3-NEXT: not16 $3, $7
364 ; MMR3-NEXT: sll16 $5, $4, 1
365 ; MMR3-NEXT: sllv $3, $5, $3
366 ; MMR3-NEXT: or16 $3, $2
367 ; MMR3-NEXT: srav $2, $4, $7
368 ; MMR3-NEXT: andi16 $5, $7, 32
369 ; MMR3-NEXT: movn $3, $2, $5
370 ; MMR3-NEXT: sra $1, $4, 31
371 ; MMR3-NEXT: jr $ra
372 ; MMR3-NEXT: movn $2, $1, $5
373 ;
374 ; MMR6-LABEL: ashr_i64:
375 ; MMR6: # %bb.0: # %entry
376 ; MMR6-NEXT: srav $1, $4, $7
377 ; MMR6-NEXT: andi16 $3, $7, 32
378 ; MMR6-NEXT: seleqz $2, $1, $3
379 ; MMR6-NEXT: sra $6, $4, 31
380 ; MMR6-NEXT: selnez $6, $6, $3
381 ; MMR6-NEXT: or $2, $6, $2
382 ; MMR6-NEXT: srlv $5, $5, $7
383 ; MMR6-NEXT: not16 $6, $7
384 ; MMR6-NEXT: sll16 $4, $4, 1
385 ; MMR6-NEXT: sllv $4, $4, $6
386 ; MMR6-NEXT: or $4, $4, $5
387 ; MMR6-NEXT: seleqz $4, $4, $3
388 ; MMR6-NEXT: selnez $1, $1, $3
389 ; MMR6-NEXT: or $3, $1, $4
390 ; MMR6-NEXT: jrc $ra
391 entry:
392 %r = ashr i64 %a, %b
393 ret i64 %r
394 }
396 define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) {
397 ; MIPS-LABEL: ashr_i128:
398 ; MIPS: # %bb.0:
399 ; MIPS-NEXT: lw $2, 28($sp)
400 ; MIPS-NEXT: addiu $1, $zero, 64
401 ; MIPS-NEXT: subu $9, $1, $2
402 ; MIPS-NEXT: sllv $10, $5, $9
403 ; MIPS-NEXT: andi $13, $9, 32
404 ; MIPS-NEXT: andi $3, $2, 32
405 ; MIPS-NEXT: addiu $11, $zero, 0
406 ; MIPS-NEXT: bnez $13, $BB5_2
407 ; MIPS-NEXT: addiu $12, $zero, 0
408 ; MIPS-NEXT: # %bb.1:
409 ; MIPS-NEXT: move $12, $10
410 ; MIPS-NEXT: $BB5_2:
411 ; MIPS-NEXT: not $8, $2
412 ; MIPS-NEXT: bnez $3, $BB5_5
413 ; MIPS-NEXT: srlv $14, $6, $2
414 ; MIPS-NEXT: # %bb.3:
415 ; MIPS-NEXT: sll $1, $6, 1
416 ; MIPS-NEXT: srlv $11, $7, $2
417 ; MIPS-NEXT: sllv $1, $1, $8
418 ; MIPS-NEXT: or $15, $1, $11
419 ; MIPS-NEXT: bnez $13, $BB5_7
420 ; MIPS-NEXT: move $11, $14
421 ; MIPS-NEXT: # %bb.4:
422 ; MIPS-NEXT: b $BB5_6
423 ; MIPS-NEXT: nop
424 ; MIPS-NEXT: $BB5_5:
425 ; MIPS-NEXT: bnez $13, $BB5_7
426 ; MIPS-NEXT: move $15, $14
427 ; MIPS-NEXT: $BB5_6:
428 ; MIPS-NEXT: sllv $1, $4, $9
429 ; MIPS-NEXT: not $9, $9
430 ; MIPS-NEXT: srl $10, $5, 1
431 ; MIPS-NEXT: srlv $9, $10, $9
432 ; MIPS-NEXT: or $10, $1, $9
433 ; MIPS-NEXT: $BB5_7:
434 ; MIPS-NEXT: addiu $24, $2, -64
435 ; MIPS-NEXT: sll $13, $4, 1
436 ; MIPS-NEXT: srav $14, $4, $24
437 ; MIPS-NEXT: andi $1, $24, 32
438 ; MIPS-NEXT: bnez $1, $BB5_10
439 ; MIPS-NEXT: sra $9, $4, 31
440 ; MIPS-NEXT: # %bb.8:
441 ; MIPS-NEXT: srlv $1, $5, $24
442 ; MIPS-NEXT: not $24, $24
443 ; MIPS-NEXT: sllv $24, $13, $24
444 ; MIPS-NEXT: or $25, $24, $1
445 ; MIPS-NEXT: move $24, $14
446 ; MIPS-NEXT: sltiu $14, $2, 64
447 ; MIPS-NEXT: beqz $14, $BB5_12
448 ; MIPS-NEXT: nop
449 ; MIPS-NEXT: # %bb.9:
450 ; MIPS-NEXT: b $BB5_11
451 ; MIPS-NEXT: nop
452 ; MIPS-NEXT: $BB5_10:
453 ; MIPS-NEXT: move $25, $14
454 ; MIPS-NEXT: sltiu $14, $2, 64
455 ; MIPS-NEXT: beqz $14, $BB5_12
456 ; MIPS-NEXT: move $24, $9
457 ; MIPS-NEXT: $BB5_11:
458 ; MIPS-NEXT: or $25, $15, $12
459 ; MIPS-NEXT: $BB5_12:
460 ; MIPS-NEXT: sltiu $12, $2, 1
461 ; MIPS-NEXT: beqz $12, $BB5_18
462 ; MIPS-NEXT: nop
463 ; MIPS-NEXT: # %bb.13:
464 ; MIPS-NEXT: bnez $14, $BB5_19
465 ; MIPS-NEXT: nop
466 ; MIPS-NEXT: $BB5_14:
467 ; MIPS-NEXT: beqz $12, $BB5_20
468 ; MIPS-NEXT: nop
469 ; MIPS-NEXT: $BB5_15:
470 ; MIPS-NEXT: bnez $3, $BB5_21
471 ; MIPS-NEXT: srav $4, $4, $2
472 ; MIPS-NEXT: $BB5_16:
473 ; MIPS-NEXT: srlv $1, $5, $2
474 ; MIPS-NEXT: sllv $2, $13, $8
475 ; MIPS-NEXT: or $3, $2, $1
476 ; MIPS-NEXT: bnez $14, $BB5_23
477 ; MIPS-NEXT: move $2, $4
478 ; MIPS-NEXT: # %bb.17:
479 ; MIPS-NEXT: b $BB5_22
480 ; MIPS-NEXT: nop
481 ; MIPS-NEXT: $BB5_18:
482 ; MIPS-NEXT: beqz $14, $BB5_14
483 ; MIPS-NEXT: move $7, $25
484 ; MIPS-NEXT: $BB5_19:
485 ; MIPS-NEXT: bnez $12, $BB5_15
486 ; MIPS-NEXT: or $24, $11, $10
487 ; MIPS-NEXT: $BB5_20:
488 ; MIPS-NEXT: move $6, $24
489 ; MIPS-NEXT: beqz $3, $BB5_16
490 ; MIPS-NEXT: srav $4, $4, $2
491 ; MIPS-NEXT: $BB5_21:
492 ; MIPS-NEXT: move $2, $9
493 ; MIPS-NEXT: bnez $14, $BB5_23
494 ; MIPS-NEXT: move $3, $4
495 ; MIPS-NEXT: $BB5_22:
496 ; MIPS-NEXT: move $2, $9
497 ; MIPS-NEXT: $BB5_23:
498 ; MIPS-NEXT: bnez $14, $BB5_25
499 ; MIPS-NEXT: nop
500 ; MIPS-NEXT: # %bb.24:
501 ; MIPS-NEXT: move $3, $9
502 ; MIPS-NEXT: $BB5_25:
503 ; MIPS-NEXT: move $4, $6
504 ; MIPS-NEXT: jr $ra
505 ; MIPS-NEXT: move $5, $7
506 ;
507 ; MIPS32-LABEL: ashr_i128:
508 ; MIPS32: # %bb.0: # %entry
509 ; MIPS32-NEXT: lw $9, 28($sp)
510 ; MIPS32-NEXT: srlv $1, $7, $9
511 ; MIPS32-NEXT: not $2, $9
512 ; MIPS32-NEXT: sll $3, $6, 1
513 ; MIPS32-NEXT: sllv $3, $3, $2
514 ; MIPS32-NEXT: addiu $8, $zero, 64
515 ; MIPS32-NEXT: or $1, $3, $1
516 ; MIPS32-NEXT: srlv $10, $6, $9
517 ; MIPS32-NEXT: subu $3, $8, $9
518 ; MIPS32-NEXT: sllv $11, $5, $3
519 ; MIPS32-NEXT: andi $12, $3, 32
520 ; MIPS32-NEXT: andi $13, $9, 32
521 ; MIPS32-NEXT: move $8, $11
522 ; MIPS32-NEXT: movn $8, $zero, $12
523 ; MIPS32-NEXT: movn $1, $10, $13
524 ; MIPS32-NEXT: addiu $14, $9, -64
525 ; MIPS32-NEXT: srlv $15, $5, $14
526 ; MIPS32-NEXT: sll $24, $4, 1
527 ; MIPS32-NEXT: not $25, $14
528 ; MIPS32-NEXT: sllv $25, $24, $25
529 ; MIPS32-NEXT: or $gp, $1, $8
530 ; MIPS32-NEXT: or $1, $25, $15
531 ; MIPS32-NEXT: srav $8, $4, $14
532 ; MIPS32-NEXT: andi $14, $14, 32
533 ; MIPS32-NEXT: movn $1, $8, $14
534 ; MIPS32-NEXT: sllv $15, $4, $3
535 ; MIPS32-NEXT: not $3, $3
536 ; MIPS32-NEXT: srl $25, $5, 1
537 ; MIPS32-NEXT: srlv $3, $25, $3
538 ; MIPS32-NEXT: sltiu $25, $9, 64
539 ; MIPS32-NEXT: movn $1, $gp, $25
540 ; MIPS32-NEXT: or $15, $15, $3
541 ; MIPS32-NEXT: srlv $3, $5, $9
542 ; MIPS32-NEXT: sllv $2, $24, $2
543 ; MIPS32-NEXT: or $5, $2, $3
544 ; MIPS32-NEXT: srav $24, $4, $9
545 ; MIPS32-NEXT: movn $5, $24, $13
546 ; MIPS32-NEXT: sra $2, $4, 31
547 ; MIPS32-NEXT: movz $1, $7, $9
548 ; MIPS32-NEXT: move $3, $2
549 ; MIPS32-NEXT: movn $3, $5, $25
550 ; MIPS32-NEXT: movn $15, $11, $12
551 ; MIPS32-NEXT: movn $10, $zero, $13
552 ; MIPS32-NEXT: or $4, $10, $15
553 ; MIPS32-NEXT: movn $8, $2, $14
554 ; MIPS32-NEXT: movn $8, $4, $25
555 ; MIPS32-NEXT: movz $8, $6, $9
556 ; MIPS32-NEXT: movn $24, $2, $13
557 ; MIPS32-NEXT: movn $2, $24, $25
558 ; MIPS32-NEXT: move $4, $8
559 ; MIPS32-NEXT: jr $ra
560 ; MIPS32-NEXT: move $5, $1
561 ;
562 ; 32R2-LABEL: ashr_i128:
563 ; 32R2: # %bb.0: # %entry
564 ; 32R2-NEXT: lw $9, 28($sp)
565 ; 32R2-NEXT: srlv $1, $7, $9
566 ; 32R2-NEXT: not $2, $9
567 ; 32R2-NEXT: sll $3, $6, 1
568 ; 32R2-NEXT: sllv $3, $3, $2
569 ; 32R2-NEXT: addiu $8, $zero, 64
570 ; 32R2-NEXT: or $1, $3, $1
571 ; 32R2-NEXT: srlv $10, $6, $9
572 ; 32R2-NEXT: subu $3, $8, $9
573 ; 32R2-NEXT: sllv $11, $5, $3
574 ; 32R2-NEXT: andi $12, $3, 32
575 ; 32R2-NEXT: andi $13, $9, 32
576 ; 32R2-NEXT: move $8, $11
577 ; 32R2-NEXT: movn $8, $zero, $12
578 ; 32R2-NEXT: movn $1, $10, $13
579 ; 32R2-NEXT: addiu $14, $9, -64
580 ; 32R2-NEXT: srlv $15, $5, $14
581 ; 32R2-NEXT: sll $24, $4, 1
582 ; 32R2-NEXT: not $25, $14
583 ; 32R2-NEXT: sllv $25, $24, $25
584 ; 32R2-NEXT: or $gp, $1, $8
585 ; 32R2-NEXT: or $1, $25, $15
586 ; 32R2-NEXT: srav $8, $4, $14
587 ; 32R2-NEXT: andi $14, $14, 32
588 ; 32R2-NEXT: movn $1, $8, $14
589 ; 32R2-NEXT: sllv $15, $4, $3
590 ; 32R2-NEXT: not $3, $3
591 ; 32R2-NEXT: srl $25, $5, 1
592 ; 32R2-NEXT: srlv $3, $25, $3
593 ; 32R2-NEXT: sltiu $25, $9, 64
594 ; 32R2-NEXT: movn $1, $gp, $25
595 ; 32R2-NEXT: or $15, $15, $3
596 ; 32R2-NEXT: srlv $3, $5, $9
597 ; 32R2-NEXT: sllv $2, $24, $2
598 ; 32R2-NEXT: or $5, $2, $3
599 ; 32R2-NEXT: srav $24, $4, $9
600 ; 32R2-NEXT: movn $5, $24, $13
601 ; 32R2-NEXT: sra $2, $4, 31
602 ; 32R2-NEXT: movz $1, $7, $9
603 ; 32R2-NEXT: move $3, $2
604 ; 32R2-NEXT: movn $3, $5, $25
605 ; 32R2-NEXT: movn $15, $11, $12
606 ; 32R2-NEXT: movn $10, $zero, $13
607 ; 32R2-NEXT: or $4, $10, $15
608 ; 32R2-NEXT: movn $8, $2, $14
609 ; 32R2-NEXT: movn $8, $4, $25
610 ; 32R2-NEXT: movz $8, $6, $9
611 ; 32R2-NEXT: movn $24, $2, $13
612 ; 32R2-NEXT: movn $2, $24, $25
613 ; 32R2-NEXT: move $4, $8
614 ; 32R2-NEXT: jr $ra
615 ; 32R2-NEXT: move $5, $1
616 ;
617 ; 32R6-LABEL: ashr_i128:
618 ; 32R6: # %bb.0: # %entry
619 ; 32R6-NEXT: lw $3, 28($sp)
620 ; 32R6-NEXT: addiu $1, $zero, 64
621 ; 32R6-NEXT: subu $1, $1, $3
622 ; 32R6-NEXT: sllv $2, $5, $1
623 ; 32R6-NEXT: andi $8, $1, 32
624 ; 32R6-NEXT: selnez $9, $2, $8
625 ; 32R6-NEXT: sllv $10, $4, $1
626 ; 32R6-NEXT: not $1, $1
627 ; 32R6-NEXT: srl $11, $5, 1
628 ; 32R6-NEXT: srlv $1, $11, $1
629 ; 32R6-NEXT: or $1, $10, $1
630 ; 32R6-NEXT: seleqz $1, $1, $8
631 ; 32R6-NEXT: or $1, $9, $1
632 ; 32R6-NEXT: srlv $9, $7, $3
633 ; 32R6-NEXT: not $10, $3
634 ; 32R6-NEXT: sll $11, $6, 1
635 ; 32R6-NEXT: sllv $11, $11, $10
636 ; 32R6-NEXT: or $9, $11, $9
637 ; 32R6-NEXT: andi $11, $3, 32
638 ; 32R6-NEXT: seleqz $9, $9, $11
639 ; 32R6-NEXT: srlv $12, $6, $3
640 ; 32R6-NEXT: selnez $13, $12, $11
641 ; 32R6-NEXT: seleqz $12, $12, $11
642 ; 32R6-NEXT: or $1, $12, $1
643 ; 32R6-NEXT: seleqz $2, $2, $8
644 ; 32R6-NEXT: or $8, $13, $9
645 ; 32R6-NEXT: addiu $9, $3, -64
646 ; 32R6-NEXT: srlv $12, $5, $9
647 ; 32R6-NEXT: sll $13, $4, 1
648 ; 32R6-NEXT: not $14, $9
649 ; 32R6-NEXT: sllv $14, $13, $14
650 ; 32R6-NEXT: sltiu $15, $3, 64
651 ; 32R6-NEXT: or $2, $8, $2
652 ; 32R6-NEXT: selnez $1, $1, $15
653 ; 32R6-NEXT: or $8, $14, $12
654 ; 32R6-NEXT: srav $12, $4, $9
655 ; 32R6-NEXT: andi $9, $9, 32
656 ; 32R6-NEXT: seleqz $14, $12, $9
657 ; 32R6-NEXT: sra $24, $4, 31
658 ; 32R6-NEXT: selnez $25, $24, $9
659 ; 32R6-NEXT: seleqz $8, $8, $9
660 ; 32R6-NEXT: or $14, $25, $14
661 ; 32R6-NEXT: seleqz $14, $14, $15
662 ; 32R6-NEXT: selnez $9, $12, $9
663 ; 32R6-NEXT: seleqz $12, $24, $15
664 ; 32R6-NEXT: or $1, $1, $14
665 ; 32R6-NEXT: selnez $14, $1, $3
666 ; 32R6-NEXT: selnez $1, $2, $15
667 ; 32R6-NEXT: or $2, $9, $8
668 ; 32R6-NEXT: srav $8, $4, $3
669 ; 32R6-NEXT: seleqz $4, $8, $11
670 ; 32R6-NEXT: selnez $9, $24, $11
671 ; 32R6-NEXT: or $4, $9, $4
672 ; 32R6-NEXT: selnez $9, $4, $15
673 ; 32R6-NEXT: seleqz $2, $2, $15
674 ; 32R6-NEXT: seleqz $4, $6, $3
675 ; 32R6-NEXT: seleqz $6, $7, $3
676 ; 32R6-NEXT: or $1, $1, $2
677 ; 32R6-NEXT: selnez $1, $1, $3
678 ; 32R6-NEXT: or $1, $6, $1
679 ; 32R6-NEXT: or $4, $4, $14
680 ; 32R6-NEXT: or $2, $9, $12
681 ; 32R6-NEXT: srlv $3, $5, $3
682 ; 32R6-NEXT: sllv $5, $13, $10
683 ; 32R6-NEXT: or $3, $5, $3
684 ; 32R6-NEXT: seleqz $3, $3, $11
685 ; 32R6-NEXT: selnez $5, $8, $11
686 ; 32R6-NEXT: or $3, $5, $3
687 ; 32R6-NEXT: selnez $3, $3, $15
688 ; 32R6-NEXT: or $3, $3, $12
689 ; 32R6-NEXT: jr $ra
690 ; 32R6-NEXT: move $5, $1
691 ;
692 ; MIPS3-LABEL: ashr_i128:
693 ; MIPS3: # %bb.0: # %entry
694 ; MIPS3-NEXT: sll $2, $7, 0
695 ; MIPS3-NEXT: andi $1, $2, 64
696 ; MIPS3-NEXT: bnez $1, .LBB5_2
697 ; MIPS3-NEXT: dsrav $3, $4, $7
698 ; MIPS3-NEXT: # %bb.1:
699 ; MIPS3-NEXT: dsrlv $1, $5, $7
700 ; MIPS3-NEXT: dsll $4, $4, 1
701 ; MIPS3-NEXT: not $2, $2
702 ; MIPS3-NEXT: dsllv $2, $4, $2
703 ; MIPS3-NEXT: or $1, $2, $1
704 ; MIPS3-NEXT: move $2, $3
705 ; MIPS3-NEXT: jr $ra
706 ; MIPS3-NEXT: move $3, $1
707 ; MIPS3-NEXT: .LBB5_2:
708 ; MIPS3-NEXT: jr $ra
709 ; MIPS3-NEXT: dsra $2, $4, 63
711 ;
712 ; MIPS64-LABEL: ashr_i128:
713 ; MIPS64: # %bb.0: # %entry
714 ; MIPS64-NEXT: dsrlv $1, $5, $7
715 ; MIPS64-NEXT: dsll $2, $4, 1
716 ; MIPS64-NEXT: sll $5, $7, 0
717 ; MIPS64-NEXT: not $3, $5
718 ; MIPS64-NEXT: dsllv $2, $2, $3
719 ; MIPS64-NEXT: or $3, $2, $1
720 ; MIPS64-NEXT: dsrav $2, $4, $7
721 ; MIPS64-NEXT: andi $1, $5, 64
722 ; MIPS64-NEXT: movn $3, $2, $1
723 ; MIPS64-NEXT: dsra $4, $4, 63
724 ; MIPS64-NEXT: jr $ra
725 ; MIPS64-NEXT: movn $2, $4, $1
726 ;
727 ; MIPS64R2-LABEL: ashr_i128:
728 ; MIPS64R2: # %bb.0: # %entry
729 ; MIPS64R2-NEXT: dsrlv $1, $5, $7
730 ; MIPS64R2-NEXT: dsll $2, $4, 1
731 ; MIPS64R2-NEXT: sll $5, $7, 0
732 ; MIPS64R2-NEXT: not $3, $5
733 ; MIPS64R2-NEXT: dsllv $2, $2, $3
734 ; MIPS64R2-NEXT: or $3, $2, $1
735 ; MIPS64R2-NEXT: dsrav $2, $4, $7
736 ; MIPS64R2-NEXT: andi $1, $5, 64
737 ; MIPS64R2-NEXT: movn $3, $2, $1
738 ; MIPS64R2-NEXT: dsra $4, $4, 63
739 ; MIPS64R2-NEXT: jr $ra
740 ; MIPS64R2-NEXT: movn $2, $4, $1
741 ;
742 ; MIPS64R6-LABEL: ashr_i128:
743 ; MIPS64R6: # %bb.0: # %entry
744 ; MIPS64R6-NEXT: dsrav $1, $4, $7
745 ; MIPS64R6-NEXT: sll $3, $7, 0
746 ; MIPS64R6-NEXT: andi $2, $3, 64
747 ; MIPS64R6-NEXT: sll $6, $2, 0
748 ; MIPS64R6-NEXT: seleqz $2, $1, $6
749 ; MIPS64R6-NEXT: dsra $8, $4, 63
750 ; MIPS64R6-NEXT: selnez $8, $8, $6
751 ; MIPS64R6-NEXT: or $2, $8, $2
752 ; MIPS64R6-NEXT: dsrlv $5, $5, $7
753 ; MIPS64R6-NEXT: dsll $4, $4, 1
754 ; MIPS64R6-NEXT: not $3, $3
755 ; MIPS64R6-NEXT: dsllv $3, $4, $3
756 ; MIPS64R6-NEXT: or $3, $3, $5
757 ; MIPS64R6-NEXT: seleqz $3, $3, $6
758 ; MIPS64R6-NEXT: selnez $1, $1, $6
759 ; MIPS64R6-NEXT: jr $ra
760 ; MIPS64R6-NEXT: or $3, $1, $3
761 ;
762 ; MMR3-LABEL: ashr_i128:
763 ; MMR3: # %bb.0: # %entry
764 ; MMR3-NEXT: addiusp -48
765 ; MMR3-NEXT: .cfi_def_cfa_offset 48
766 ; MMR3-NEXT: swp $16, 40($sp)
767 ; MMR3-NEXT: .cfi_offset 17, -4
768 ; MMR3-NEXT: .cfi_offset 16, -8
769 ; MMR3-NEXT: move $8, $7
770 ; MMR3-NEXT: sw $6, 32($sp) # 4-byte Folded Spill
771 ; MMR3-NEXT: sw $5, 36($sp) # 4-byte Folded Spill
772 ; MMR3-NEXT: sw $4, 8($sp) # 4-byte Folded Spill
773 ; MMR3-NEXT: lw $16, 76($sp)
774 ; MMR3-NEXT: srlv $4, $7, $16
775 ; MMR3-NEXT: not16 $3, $16
776 ; MMR3-NEXT: sw $3, 24($sp) # 4-byte Folded Spill
777 ; MMR3-NEXT: sll16 $2, $6, 1
778 ; MMR3-NEXT: sllv $3, $2, $3
779 ; MMR3-NEXT: li16 $2, 64
780 ; MMR3-NEXT: or16 $3, $4
781 ; MMR3-NEXT: srlv $6, $6, $16
782 ; MMR3-NEXT: sw $6, 12($sp) # 4-byte Folded Spill
783 ; MMR3-NEXT: subu16 $7, $2, $16
784 ; MMR3-NEXT: sllv $9, $5, $7
785 ; MMR3-NEXT: andi16 $2, $7, 32
786 ; MMR3-NEXT: sw $2, 28($sp) # 4-byte Folded Spill
787 ; MMR3-NEXT: andi16 $5, $16, 32
788 ; MMR3-NEXT: sw $5, 16($sp) # 4-byte Folded Spill
789 ; MMR3-NEXT: move $4, $9
790 ; MMR3-NEXT: li16 $17, 0
791 ; MMR3-NEXT: movn $4, $17, $2
792 ; MMR3-NEXT: movn $3, $6, $5
793 ; MMR3-NEXT: addiu $2, $16, -64
794 ; MMR3-NEXT: lw $5, 36($sp) # 4-byte Folded Reload
795 ; MMR3-NEXT: srlv $5, $5, $2
796 ; MMR3-NEXT: sw $5, 20($sp) # 4-byte Folded Spill
797 ; MMR3-NEXT: lw $17, 8($sp) # 4-byte Folded Reload
798 ; MMR3-NEXT: sll16 $6, $17, 1
799 ; MMR3-NEXT: sw $6, 4($sp) # 4-byte Folded Spill
800 ; MMR3-NEXT: not16 $5, $2
801 ; MMR3-NEXT: sllv $5, $6, $5
802 ; MMR3-NEXT: or16 $3, $4
803 ; MMR3-NEXT: lw $4, 20($sp) # 4-byte Folded Reload
804 ; MMR3-NEXT: or16 $5, $4
805 ; MMR3-NEXT: srav $1, $17, $2
806 ; MMR3-NEXT: andi16 $2, $2, 32
807 ; MMR3-NEXT: sw $2, 20($sp) # 4-byte Folded Spill
808 ; MMR3-NEXT: movn $5, $1, $2
809 ; MMR3-NEXT: sllv $2, $17, $7
810 ; MMR3-NEXT: not16 $4, $7
811 ; MMR3-NEXT: lw $7, 36($sp) # 4-byte Folded Reload
812 ; MMR3-NEXT: srl16 $6, $7, 1
813 ; MMR3-NEXT: srlv $6, $6, $4
814 ; MMR3-NEXT: sltiu $10, $16, 64
815 ; MMR3-NEXT: movn $5, $3, $10
816 ; MMR3-NEXT: or16 $6, $2
817 ; MMR3-NEXT: srlv $2, $7, $16
818 ; MMR3-NEXT: lw $3, 24($sp) # 4-byte Folded Reload
819 ; MMR3-NEXT: lw $4, 4($sp) # 4-byte Folded Reload
820 ; MMR3-NEXT: sllv $3, $4, $3
821 ; MMR3-NEXT: or16 $3, $2
822 ; MMR3-NEXT: srav $11, $17, $16
823 ; MMR3-NEXT: lw $4, 16($sp) # 4-byte Folded Reload
824 ; MMR3-NEXT: movn $3, $11, $4
825 ; MMR3-NEXT: sra $2, $17, 31
826 ; MMR3-NEXT: movz $5, $8, $16
827 ; MMR3-NEXT: move $8, $2
828 ; MMR3-NEXT: movn $8, $3, $10
829 ; MMR3-NEXT: lw $3, 28($sp) # 4-byte Folded Reload
830 ; MMR3-NEXT: movn $6, $9, $3
831 ; MMR3-NEXT: li16 $3, 0
832 ; MMR3-NEXT: lw $7, 12($sp) # 4-byte Folded Reload
833 ; MMR3-NEXT: movn $7, $3, $4
834 ; MMR3-NEXT: or16 $7, $6
835 ; MMR3-NEXT: lw $3, 20($sp) # 4-byte Folded Reload
836 ; MMR3-NEXT: movn $1, $2, $3
837 ; MMR3-NEXT: movn $1, $7, $10
838 ; MMR3-NEXT: lw $3, 32($sp) # 4-byte Folded Reload
839 ; MMR3-NEXT: movz $1, $3, $16
840 ; MMR3-NEXT: movn $11, $2, $4
841 ; MMR3-NEXT: movn $2, $11, $10
842 ; MMR3-NEXT: move $3, $8
843 ; MMR3-NEXT: move $4, $1
844 ; MMR3-NEXT: lwp $16, 40($sp)
845 ; MMR3-NEXT: addiusp 48
846 ; MMR3-NEXT: jrc $ra
847 ;
848 ; MMR6-LABEL: ashr_i128:
849 ; MMR6: # %bb.0: # %entry
850 ; MMR6-NEXT: addiu $sp, $sp, -16
851 ; MMR6-NEXT: .cfi_def_cfa_offset 16
852 ; MMR6-NEXT: sw $17, 12($sp) # 4-byte Folded Spill
853 ; MMR6-NEXT: sw $16, 8($sp) # 4-byte Folded Spill
854 ; MMR6-NEXT: .cfi_offset 17, -4
855 ; MMR6-NEXT: .cfi_offset 16, -8
856 ; MMR6-NEXT: move $1, $7
857 ; MMR6-NEXT: lw $3, 44($sp)
858 ; MMR6-NEXT: li16 $2, 64
859 ; MMR6-NEXT: subu16 $7, $2, $3
860 ; MMR6-NEXT: sllv $8, $5, $7
861 ; MMR6-NEXT: andi16 $2, $7, 32
862 ; MMR6-NEXT: selnez $9, $8, $2
863 ; MMR6-NEXT: sllv $10, $4, $7
864 ; MMR6-NEXT: not16 $7, $7
865 ; MMR6-NEXT: srl16 $16, $5, 1
866 ; MMR6-NEXT: srlv $7, $16, $7
867 ; MMR6-NEXT: or $7, $10, $7
868 ; MMR6-NEXT: seleqz $7, $7, $2
869 ; MMR6-NEXT: or $7, $9, $7
870 ; MMR6-NEXT: srlv $9, $1, $3
871 ; MMR6-NEXT: not16 $16, $3
872 ; MMR6-NEXT: sw $16, 4($sp) # 4-byte Folded Spill
873 ; MMR6-NEXT: sll16 $17, $6, 1
874 ; MMR6-NEXT: sllv $10, $17, $16
875 ; MMR6-NEXT: or $9, $10, $9
876 ; MMR6-NEXT: andi16 $17, $3, 32
877 ; MMR6-NEXT: seleqz $9, $9, $17
878 ; MMR6-NEXT: srlv $10, $6, $3
879 ; MMR6-NEXT: selnez $11, $10, $17
880 ; MMR6-NEXT: seleqz $10, $10, $17
881 ; MMR6-NEXT: or $10, $10, $7
882 ; MMR6-NEXT: seleqz $12, $8, $2
883 ; MMR6-NEXT: or $8, $11, $9
884 ; MMR6-NEXT: addiu $2, $3, -64
885 ; MMR6-NEXT: srlv $9, $5, $2
886 ; MMR6-NEXT: sll16 $7, $4, 1
887 ; MMR6-NEXT: not16 $16, $2
888 ; MMR6-NEXT: sllv $11, $7, $16
889 ; MMR6-NEXT: sltiu $13, $3, 64
890 ; MMR6-NEXT: or $8, $8, $12
891 ; MMR6-NEXT: selnez $10, $10, $13
892 ; MMR6-NEXT: or $9, $11, $9
893 ; MMR6-NEXT: srav $11, $4, $2
894 ; MMR6-NEXT: andi16 $2, $2, 32
895 ; MMR6-NEXT: seleqz $12, $11, $2
896 ; MMR6-NEXT: sra $14, $4, 31
897 ; MMR6-NEXT: selnez $15, $14, $2
898 ; MMR6-NEXT: seleqz $9, $9, $2
899 ; MMR6-NEXT: or $12, $15, $12
900 ; MMR6-NEXT: seleqz $12, $12, $13
901 ; MMR6-NEXT: selnez $2, $11, $2
902 ; MMR6-NEXT: seleqz $11, $14, $13
903 ; MMR6-NEXT: or $10, $10, $12
904 ; MMR6-NEXT: selnez $10, $10, $3
905 ; MMR6-NEXT: selnez $8, $8, $13
906 ; MMR6-NEXT: or $2, $2, $9
907 ; MMR6-NEXT: srav $9, $4, $3
908 ; MMR6-NEXT: seleqz $4, $9, $17
909 ; MMR6-NEXT: selnez $12, $14, $17
910 ; MMR6-NEXT: or $4, $12, $4
911 ; MMR6-NEXT: selnez $12, $4, $13
912 ; MMR6-NEXT: seleqz $2, $2, $13
913 ; MMR6-NEXT: seleqz $4, $6, $3
914 ; MMR6-NEXT: seleqz $1, $1, $3
915 ; MMR6-NEXT: or $2, $8, $2
916 ; MMR6-NEXT: selnez $2, $2, $3
917 ; MMR6-NEXT: or $1, $1, $2
918 ; MMR6-NEXT: or $4, $4, $10
919 ; MMR6-NEXT: or $2, $12, $11
920 ; MMR6-NEXT: srlv $3, $5, $3
921 ; MMR6-NEXT: lw $5, 4($sp) # 4-byte Folded Reload
922 ; MMR6-NEXT: sllv $5, $7, $5
923 ; MMR6-NEXT: or $3, $5, $3
924 ; MMR6-NEXT: seleqz $3, $3, $17
925 ; MMR6-NEXT: selnez $5, $9, $17
926 ; MMR6-NEXT: or $3, $5, $3
927 ; MMR6-NEXT: selnez $3, $3, $13
928 ; MMR6-NEXT: or $3, $3, $11
929 ; MMR6-NEXT: move $5, $1
930 ; MMR6-NEXT: lw $16, 8($sp) # 4-byte Folded Reload
931 ; MMR6-NEXT: lw $17, 12($sp) # 4-byte Folded Reload
932 ; MMR6-NEXT: addiu $sp, $sp, 16
933 ; MMR6-NEXT: jrc $ra
934 entry:
935 ; o32 shouldn't use TImode helpers.
936 ; GP32-NOT: lw $25, %call16(__ashrti3)($gp)
937 ; MM-NOT: lw $25, %call16(__ashrti3)($2)
939 %r = ashr i128 %a, %b
940 ret i128 %r
941 }