| blob | 9aa81dac1262a11046723ae0df8b2dba48713bf5 |
1 ; ## Full FP16 support enabled by default.\r
2 ; RUN: llc < %s -mtriple=nvptx64-nvidia-cuda -mcpu=sm_53 -asm-verbose=false \\r
3 ; RUN: -O0 -disable-post-ra -frame-pointer=all -verify-machineinstrs \\r
4 ; RUN: | FileCheck -check-prefixes CHECK,CHECK-NOFTZ,CHECK-F16,CHECK-F16-NOFTZ %s\r
5 ; ## Full FP16 with FTZ\r
6 ; RUN: llc < %s -mtriple=nvptx64-nvidia-cuda -mcpu=sm_53 -asm-verbose=false \\r
7 ; RUN: -O0 -disable-post-ra -frame-pointer=all -verify-machineinstrs \\r
8 ; RUN: -nvptx-f32ftz \\r
9 ; RUN: | FileCheck -check-prefixes CHECK,CHECK-F16,CHECK-F16-FTZ %s\r
10 ; ## FP16 support explicitly disabled.\r
11 ; RUN: llc < %s -mtriple=nvptx64-nvidia-cuda -mcpu=sm_53 -asm-verbose=false \\r
12 ; RUN: -O0 -disable-post-ra -frame-pointer=all --nvptx-no-f16-math \\r
13 ; RUN: -verify-machineinstrs \\r
14 ; RUN: | FileCheck -check-prefixes CHECK,CHECK-NOFTZ,CHECK-NOF16 %s\r
15 ; ## FP16 is not supported by hardware.\r
16 ; RUN: llc < %s -O0 -mtriple=nvptx64-nvidia-cuda -mcpu=sm_52 -asm-verbose=false \\r
17 ; RUN: -disable-post-ra -frame-pointer=all -verify-machineinstrs \\r
18 ; RUN: | FileCheck -check-prefixes CHECK,CHECK-NOFTZ,CHECK-NOF16 %s\r
19 \r
20 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"\r
21 \r
22 ; CHECK-LABEL: test_ret_const(\r
23 ; CHECK: mov.b16 [[R:%h[0-9]+]], 0x3C00;\r
24 ; CHECK-NEXT: st.param.b16 [func_retval0+0], [[R]];\r
25 ; CHECK-NEXT: ret;\r
26 define half @test_ret_const() #0 {\r
27 ret half 1.0\r
28 }\r
29 \r
30 ; CHECK-LABEL: test_fadd(\r
31 ; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fadd_param_0];\r
32 ; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fadd_param_1];\r
33 ; CHECK-F16-NOFTZ-NEXT: add.rn.f16 [[R:%h[0-9]+]], [[A]], [[B]];\r
34 ; CHECK-F16-FTZ-NEXT: add.rn.ftz.f16 [[R:%h[0-9]+]], [[A]], [[B]];\r
35 ; CHECK-NOF16-DAG: cvt.f32.f16 [[A32:%f[0-9]+]], [[A]]\r
36 ; CHECK-NOF16-DAG: cvt.f32.f16 [[B32:%f[0-9]+]], [[B]]\r
37 ; CHECK-NOF16-NEXT: add.rn.f32 [[R32:%f[0-9]+]], [[A32]], [[B32]];\r
38 ; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[R32]]\r
39 ; CHECK-NEXT: st.param.b16 [func_retval0+0], [[R]];\r
40 ; CHECK-NEXT: ret;\r
41 define half @test_fadd(half %a, half %b) #0 {\r
42 %r = fadd half %a, %b\r
43 ret half %r\r
44 }\r
45 \r
46 ; CHECK-LABEL: test_fadd_v1f16(\r
47 ; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fadd_v1f16_param_0];\r
48 ; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fadd_v1f16_param_1];\r
49 ; CHECK-F16-NOFTZ-NEXT: add.rn.f16 [[R:%h[0-9]+]], [[A]], [[B]];\r
50 ; CHECK-F16-FTZ-NEXT: add.rn.ftz.f16 [[R:%h[0-9]+]], [[A]], [[B]];\r
51 ; CHECK-NOF16-DAG: cvt.f32.f16 [[A32:%f[0-9]+]], [[A]]\r
52 ; CHECK-NOF16-DAG: cvt.f32.f16 [[B32:%f[0-9]+]], [[B]]\r
53 ; CHECK-NOF16-NEXT: add.rn.f32 [[R32:%f[0-9]+]], [[A32]], [[B32]];\r
54 ; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[R32]]\r
55 ; CHECK-NEXT: st.param.b16 [func_retval0+0], [[R]];\r
56 ; CHECK-NEXT: ret;\r
57 define <1 x half> @test_fadd_v1f16(<1 x half> %a, <1 x half> %b) #0 {\r
58 %r = fadd <1 x half> %a, %b\r
59 ret <1 x half> %r\r
60 }\r
61 \r
62 ; Check that we can lower fadd with immediate arguments.\r
63 ; CHECK-LABEL: test_fadd_imm_0(\r
64 ; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fadd_imm_0_param_0];\r
65 ; CHECK-F16-NOFTZ-DAG: mov.b16 [[A:%h[0-9]+]], 0x3C00;\r
66 ; CHECK-F16-NOFTZ-NEXT: add.rn.f16 [[R:%h[0-9]+]], [[B]], [[A]];\r
67 ; CHECK-F16-FTZ-DAG: mov.b16 [[A:%h[0-9]+]], 0x3C00;\r
68 ; CHECK-F16-FTZ-NEXT: add.rn.ftz.f16 [[R:%h[0-9]+]], [[B]], [[A]];\r
69 ; CHECK-NOF16-DAG: cvt.f32.f16 [[B32:%f[0-9]+]], [[B]]\r
70 ; CHECK-NOF16-NEXT: add.rn.f32 [[R32:%f[0-9]+]], [[B32]], 0f3F800000;\r
71 ; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[R32]]\r
72 ; CHECK-NEXT: st.param.b16 [func_retval0+0], [[R]];\r
73 ; CHECK-NEXT: ret;\r
74 define half @test_fadd_imm_0(half %b) #0 {\r
75 %r = fadd half 1.0, %b\r
76 ret half %r\r
77 }\r
78 \r
79 ; CHECK-LABEL: test_fadd_imm_1(\r
80 ; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fadd_imm_1_param_0];\r
81 ; CHECK-F16-NOFTZ-DAG: mov.b16 [[A:%h[0-9]+]], 0x3C00;\r
82 ; CHECK-F16-NOFTZ-NEXT: add.rn.f16 [[R:%h[0-9]+]], [[B]], [[A]];\r
83 ; CHECK-F16-FTZ-DAG: mov.b16 [[A:%h[0-9]+]], 0x3C00;\r
84 ; CHECK-F16-FTZ-NEXT: add.rn.ftz.f16 [[R:%h[0-9]+]], [[B]], [[A]];\r
85 ; CHECK-NOF16-DAG: cvt.f32.f16 [[B32:%f[0-9]+]], [[B]]\r
86 ; CHECK-NOF16-NEXT: add.rn.f32 [[R32:%f[0-9]+]], [[B32]], 0f3F800000;\r
87 ; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[R32]]\r
88 ; CHECK-NEXT: st.param.b16 [func_retval0+0], [[R]];\r
89 ; CHECK-NEXT: ret;\r
90 define half @test_fadd_imm_1(half %a) #0 {\r
91 %r = fadd half %a, 1.0\r
92 ret half %r\r
93 }\r
94 \r
95 ; CHECK-LABEL: test_fsub(\r
96 ; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fsub_param_0];\r
97 ; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fsub_param_1];\r
98 ; CHECK-F16-NOFTZ-NEXT: sub.rn.f16 [[R:%h[0-9]+]], [[A]], [[B]];\r
99 ; CHECK-F16-FTZ-NEXT: sub.rn.ftz.f16 [[R:%h[0-9]+]], [[A]], [[B]];\r
100 ; CHECK-NOF16-DAG: cvt.f32.f16 [[A32:%f[0-9]+]], [[A]]\r
101 ; CHECK-NOF16-DAG: cvt.f32.f16 [[B32:%f[0-9]+]], [[B]]\r
102 ; CHECK-NOF16-NEXT: sub.rn.f32 [[R32:%f[0-9]+]], [[A32]], [[B32]];\r
103 ; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[R32]]\r
104 ; CHECK-NEXT: st.param.b16 [func_retval0+0], [[R]];\r
105 ; CHECK-NEXT: ret;\r
106 define half @test_fsub(half %a, half %b) #0 {\r
107 %r = fsub half %a, %b\r
108 ret half %r\r
109 }\r
110 \r
111 ; CHECK-LABEL: test_fneg(\r
112 ; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fneg_param_0];\r
113 ; CHECK-F16-NOFTZ-NEXT: mov.b16 [[Z:%h[0-9]+]], 0x0000\r
114 ; CHECK-F16-NOFTZ-NEXT: sub.rn.f16 [[R:%h[0-9]+]], [[Z]], [[A]];\r
115 ; CHECK-F16-FTZ-NEXT: mov.b16 [[Z:%h[0-9]+]], 0x0000\r
116 ; CHECK-F16-FTZ-NEXT: sub.rn.ftz.f16 [[R:%h[0-9]+]], [[Z]], [[A]];\r
117 ; CHECK-NOF16-DAG: cvt.f32.f16 [[A32:%f[0-9]+]], [[A]]\r
118 ; CHECK-NOF16-DAG: mov.f32 [[Z:%f[0-9]+]], 0f00000000;\r
119 ; CHECK-NOF16-NEXT: sub.rn.f32 [[R32:%f[0-9]+]], [[Z]], [[A32]];\r
120 ; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[R32]]\r
121 ; CHECK-NEXT: st.param.b16 [func_retval0+0], [[R]];\r
122 ; CHECK-NEXT: ret;\r
123 define half @test_fneg(half %a) #0 {\r
124 %r = fsub half 0.0, %a\r
125 ret half %r\r
126 }\r
127 \r
128 ; CHECK-LABEL: test_fmul(\r
129 ; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fmul_param_0];\r
130 ; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fmul_param_1];\r
131 ; CHECK-F16-NOFTZ-NEXT: mul.rn.f16 [[R:%h[0-9]+]], [[A]], [[B]];\r
132 ; CHECK-F16-FTZ-NEXT: mul.rn.ftz.f16 [[R:%h[0-9]+]], [[A]], [[B]];\r
133 ; CHECK-NOF16-DAG: cvt.f32.f16 [[A32:%f[0-9]+]], [[A]]\r
134 ; CHECK-NOF16-DAG: cvt.f32.f16 [[B32:%f[0-9]+]], [[B]]\r
135 ; CHECK-NOF16-NEXT: mul.rn.f32 [[R32:%f[0-9]+]], [[A32]], [[B32]];\r
136 ; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[R32]]\r
137 ; CHECK-NEXT: st.param.b16 [func_retval0+0], [[R]];\r
138 ; CHECK-NEXT: ret;\r
139 define half @test_fmul(half %a, half %b) #0 {\r
140 %r = fmul half %a, %b\r
141 ret half %r\r
142 }\r
143 \r
144 ; CHECK-LABEL: test_fdiv(\r
145 ; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fdiv_param_0];\r
146 ; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fdiv_param_1];\r
147 ; CHECK-NOFTZ-DAG: cvt.f32.f16 [[F0:%f[0-9]+]], [[A]];\r
148 ; CHECK-NOFTZ-DAG: cvt.f32.f16 [[F1:%f[0-9]+]], [[B]];\r
149 ; CHECK-NOFTZ-NEXT: div.rn.f32 [[FR:%f[0-9]+]], [[F0]], [[F1]];\r
150 ; CHECK-F16-FTZ-DAG: cvt.ftz.f32.f16 [[F0:%f[0-9]+]], [[A]];\r
151 ; CHECK-F16-FTZ-DAG: cvt.ftz.f32.f16 [[F1:%f[0-9]+]], [[B]];\r
152 ; CHECK-F16-FTZ-NEXT: div.rn.ftz.f32 [[FR:%f[0-9]+]], [[F0]], [[F1]];\r
153 ; CHECK-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[FR]];\r
154 ; CHECK-NEXT: st.param.b16 [func_retval0+0], [[R]];\r
155 ; CHECK-NEXT: ret;\r
156 define half @test_fdiv(half %a, half %b) #0 {\r
157 %r = fdiv half %a, %b\r
158 ret half %r\r
159 }\r
160 \r
161 ; CHECK-LABEL: test_frem(\r
162 ; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_frem_param_0];\r
163 ; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_frem_param_1];\r
164 ; CHECK-NOFTZ-DAG: cvt.f32.f16 [[FA:%f[0-9]+]], [[A]];\r
165 ; CHECK-NOFTZ-DAG: cvt.f32.f16 [[FB:%f[0-9]+]], [[B]];\r
166 ; CHECK-NOFTZ-NEXT: div.rn.f32 [[D:%f[0-9]+]], [[FA]], [[FB]];\r
167 ; CHECK-NOFTZ-NEXT: cvt.rmi.f32.f32 [[DI:%f[0-9]+]], [[D]];\r
168 ; CHECK-NOFTZ-NEXT: mul.f32 [[RI:%f[0-9]+]], [[DI]], [[FB]];\r
169 ; CHECK-NOFTZ-NEXT: sub.f32 [[RF:%f[0-9]+]], [[FA]], [[RI]];\r
170 ; CHECK-F16-FTZ-DAG: cvt.ftz.f32.f16 [[FA:%f[0-9]+]], [[A]];\r
171 ; CHECK-F16-FTZ-DAG: cvt.ftz.f32.f16 [[FB:%f[0-9]+]], [[B]];\r
172 ; CHECK-F16-FTZ-NEXT: div.rn.ftz.f32 [[D:%f[0-9]+]], [[FA]], [[FB]];\r
173 ; CHECK-F16-FTZ-NEXT: cvt.rmi.ftz.f32.f32 [[DI:%f[0-9]+]], [[D]];\r
174 ; CHECK-F16-FTZ-NEXT: mul.ftz.f32 [[RI:%f[0-9]+]], [[DI]], [[FB]];\r
175 ; CHECK-F16-FTZ-NEXT: sub.ftz.f32 [[RF:%f[0-9]+]], [[FA]], [[RI]];\r
176 ; CHECK-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[RF]];\r
177 ; CHECK-NEXT: st.param.b16 [func_retval0+0], [[R]];\r
178 ; CHECK-NEXT: ret;\r
179 define half @test_frem(half %a, half %b) #0 {\r
180 %r = frem half %a, %b\r
181 ret half %r\r
182 }\r
183 \r
184 ; CHECK-LABEL: test_store(\r
185 ; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_store_param_0];\r
186 ; CHECK-DAG: ld.param.u64 %[[PTR:rd[0-9]+]], [test_store_param_1];\r
187 ; CHECK-NEXT: st.b16 [%[[PTR]]], [[A]];\r
188 ; CHECK-NEXT: ret;\r
189 define void @test_store(half %a, half* %b) #0 {\r
190 store half %a, half* %b\r
191 ret void\r
192 }\r
193 \r
194 ; CHECK-LABEL: test_load(\r
195 ; CHECK: ld.param.u64 %[[PTR:rd[0-9]+]], [test_load_param_0];\r
196 ; CHECK-NEXT: ld.b16 [[R:%h[0-9]+]], [%[[PTR]]];\r
197 ; CHECK-NEXT: st.param.b16 [func_retval0+0], [[R]];\r
198 ; CHECK-NEXT: ret;\r
199 define half @test_load(half* %a) #0 {\r
200 %r = load half, half* %a\r
201 ret half %r\r
202 }\r
203 \r
204 ; CHECK-LABEL: .visible .func test_halfp0a1(\r
205 ; CHECK-DAG: ld.param.u64 %[[FROM:rd?[0-9]+]], [test_halfp0a1_param_0];\r
206 ; CHECK-DAG: ld.param.u64 %[[TO:rd?[0-9]+]], [test_halfp0a1_param_1];\r
207 ; CHECK-DAG: ld.u8 [[B0:%r[sd]?[0-9]+]], [%[[FROM]]]\r
208 ; CHECK-DAG: st.u8 [%[[TO]]], [[B0]]\r
209 ; CHECK-DAG: ld.u8 [[B1:%r[sd]?[0-9]+]], [%[[FROM]]+1]\r
210 ; CHECK-DAG: st.u8 [%[[TO]]+1], [[B1]]\r
211 ; CHECK: ret\r
212 define void @test_halfp0a1(half * noalias readonly %from, half * %to) {\r
213 %1 = load half, half * %from , align 1\r
214 store half %1, half * %to , align 1\r
215 ret void\r
216 }\r
217 \r
218 declare half @test_callee(half %a, half %b) #0\r
219 \r
220 ; CHECK-LABEL: test_call(\r
221 ; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_call_param_0];\r
222 ; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_call_param_1];\r
223 ; CHECK: {\r
224 ; CHECK-DAG: .param .b32 param0;\r
225 ; CHECK-DAG: .param .b32 param1;\r
226 ; CHECK-DAG: st.param.b16 [param0+0], [[A]];\r
227 ; CHECK-DAG: st.param.b16 [param1+0], [[B]];\r
228 ; CHECK-DAG: .param .b32 retval0;\r
229 ; CHECK: call.uni (retval0),\r
230 ; CHECK-NEXT: test_callee,\r
231 ; CHECK: );\r
232 ; CHECK-NEXT: ld.param.b16 [[R:%h[0-9]+]], [retval0+0];\r
233 ; CHECK-NEXT: }\r
234 ; CHECK-NEXT: st.param.b16 [func_retval0+0], [[R]];\r
235 ; CHECK-NEXT: ret;\r
236 define half @test_call(half %a, half %b) #0 {\r
237 %r = call half @test_callee(half %a, half %b)\r
238 ret half %r\r
239 }\r
240 \r
241 ; CHECK-LABEL: test_call_flipped(\r
242 ; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_call_flipped_param_0];\r
243 ; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_call_flipped_param_1];\r
244 ; CHECK: {\r
245 ; CHECK-DAG: .param .b32 param0;\r
246 ; CHECK-DAG: .param .b32 param1;\r
247 ; CHECK-DAG: st.param.b16 [param0+0], [[B]];\r
248 ; CHECK-DAG: st.param.b16 [param1+0], [[A]];\r
249 ; CHECK-DAG: .param .b32 retval0;\r
250 ; CHECK: call.uni (retval0),\r
251 ; CHECK-NEXT: test_callee,\r
252 ; CHECK: );\r
253 ; CHECK-NEXT: ld.param.b16 [[R:%h[0-9]+]], [retval0+0];\r
254 ; CHECK-NEXT: }\r
255 ; CHECK-NEXT: st.param.b16 [func_retval0+0], [[R]];\r
256 ; CHECK-NEXT: ret;\r
257 define half @test_call_flipped(half %a, half %b) #0 {\r
258 %r = call half @test_callee(half %b, half %a)\r
259 ret half %r\r
260 }\r
261 \r
262 ; CHECK-LABEL: test_tailcall_flipped(\r
263 ; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_tailcall_flipped_param_0];\r
264 ; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_tailcall_flipped_param_1];\r
265 ; CHECK: {\r
266 ; CHECK-DAG: .param .b32 param0;\r
267 ; CHECK-DAG: .param .b32 param1;\r
268 ; CHECK-DAG: st.param.b16 [param0+0], [[B]];\r
269 ; CHECK-DAG: st.param.b16 [param1+0], [[A]];\r
270 ; CHECK-DAG: .param .b32 retval0;\r
271 ; CHECK: call.uni (retval0),\r
272 ; CHECK-NEXT: test_callee,\r
273 ; CHECK: );\r
274 ; CHECK-NEXT: ld.param.b16 [[R:%h[0-9]+]], [retval0+0];\r
275 ; CHECK-NEXT: }\r
276 ; CHECK-NEXT: st.param.b16 [func_retval0+0], [[R]];\r
277 ; CHECK-NEXT: ret;\r
278 define half @test_tailcall_flipped(half %a, half %b) #0 {\r
279 %r = tail call half @test_callee(half %b, half %a)\r
280 ret half %r\r
281 }\r
282 \r
283 ; CHECK-LABEL: test_select(\r
284 ; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_select_param_0];\r
285 ; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_select_param_1];\r
286 ; CHECK-DAG: setp.eq.b16 [[PRED:%p[0-9]+]], %rs{{.*}}, 1;\r
287 ; CHECK-NEXT: selp.b16 [[R:%h[0-9]+]], [[A]], [[B]], [[PRED]];\r
288 ; CHECK-NEXT: st.param.b16 [func_retval0+0], [[R]];\r
289 ; CHECK-NEXT: ret;\r
290 define half @test_select(half %a, half %b, i1 zeroext %c) #0 {\r
291 %r = select i1 %c, half %a, half %b\r
292 ret half %r\r
293 }\r
294 \r
295 ; CHECK-LABEL: test_select_cc(\r
296 ; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_select_cc_param_0];\r
297 ; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_select_cc_param_1];\r
298 ; CHECK-DAG: ld.param.b16 [[C:%h[0-9]+]], [test_select_cc_param_2];\r
299 ; CHECK-DAG: ld.param.b16 [[D:%h[0-9]+]], [test_select_cc_param_3];\r
300 ; CHECK-F16-NOFTZ: setp.neu.f16 [[PRED:%p[0-9]+]], [[C]], [[D]]\r
301 ; CHECK-NOF16-DAG: cvt.f32.f16 [[DF:%f[0-9]+]], [[D]];\r
302 ; CHECK-NOF16-DAG: cvt.f32.f16 [[CF:%f[0-9]+]], [[C]];\r
303 ; CHECK-NOF16: setp.neu.f32 [[PRED:%p[0-9]+]], [[CF]], [[DF]]\r
304 ; CHECK: selp.b16 [[R:%h[0-9]+]], [[A]], [[B]], [[PRED]];\r
305 ; CHECK-NEXT: st.param.b16 [func_retval0+0], [[R]];\r
306 ; CHECK-NEXT: ret;\r
307 define half @test_select_cc(half %a, half %b, half %c, half %d) #0 {\r
308 %cc = fcmp une half %c, %d\r
309 %r = select i1 %cc, half %a, half %b\r
310 ret half %r\r
311 }\r
312 \r
313 ; CHECK-LABEL: test_select_cc_f32_f16(\r
314 ; CHECK-DAG: ld.param.f32 [[A:%f[0-9]+]], [test_select_cc_f32_f16_param_0];\r
315 ; CHECK-DAG: ld.param.f32 [[B:%f[0-9]+]], [test_select_cc_f32_f16_param_1];\r
316 ; CHECK-DAG: ld.param.b16 [[C:%h[0-9]+]], [test_select_cc_f32_f16_param_2];\r
317 ; CHECK-DAG: ld.param.b16 [[D:%h[0-9]+]], [test_select_cc_f32_f16_param_3];\r
318 ; CHECK-F16-NOFTZ: setp.neu.f16 [[PRED:%p[0-9]+]], [[C]], [[D]]\r
319 ; CHECK-F16-FTZ: setp.neu.ftz.f16 [[PRED:%p[0-9]+]], [[C]], [[D]]\r
320 ; CHECK-NOF16-DAG: cvt.f32.f16 [[DF:%f[0-9]+]], [[D]];\r
321 ; CHECK-NOF16-DAG: cvt.f32.f16 [[CF:%f[0-9]+]], [[C]];\r
322 ; CHECK-NOF16: setp.neu.f32 [[PRED:%p[0-9]+]], [[CF]], [[DF]]\r
323 ; CHECK-NEXT: selp.f32 [[R:%f[0-9]+]], [[A]], [[B]], [[PRED]];\r
324 ; CHECK-NEXT: st.param.f32 [func_retval0+0], [[R]];\r
325 ; CHECK-NEXT: ret;\r
326 define float @test_select_cc_f32_f16(float %a, float %b, half %c, half %d) #0 {\r
327 %cc = fcmp une half %c, %d\r
328 %r = select i1 %cc, float %a, float %b\r
329 ret float %r\r
330 }\r
331 \r
332 ; CHECK-LABEL: test_select_cc_f16_f32(\r
333 ; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_select_cc_f16_f32_param_0];\r
334 ; CHECK-DAG: ld.param.f32 [[C:%f[0-9]+]], [test_select_cc_f16_f32_param_2];\r
335 ; CHECK-DAG: ld.param.f32 [[D:%f[0-9]+]], [test_select_cc_f16_f32_param_3];\r
336 ; CHECK-NOFTZ-DAG: setp.neu.f32 [[PRED:%p[0-9]+]], [[C]], [[D]]\r
337 ; CHECK-F16-FTZ-DAG: setp.neu.ftz.f32 [[PRED:%p[0-9]+]], [[C]], [[D]]\r
338 ; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_select_cc_f16_f32_param_1];\r
339 ; CHECK-NEXT: selp.b16 [[R:%h[0-9]+]], [[A]], [[B]], [[PRED]];\r
340 ; CHECK-NEXT: st.param.b16 [func_retval0+0], [[R]];\r
341 ; CHECK-NEXT: ret;\r
342 define half @test_select_cc_f16_f32(half %a, half %b, float %c, float %d) #0 {\r
343 %cc = fcmp une float %c, %d\r
344 %r = select i1 %cc, half %a, half %b\r
345 ret half %r\r
346 }\r
347 \r
348 ; CHECK-LABEL: test_fcmp_une(\r
349 ; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fcmp_une_param_0];\r
350 ; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fcmp_une_param_1];\r
351 ; CHECK-F16-NOFTZ: setp.neu.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]\r
352 ; CHECK-F16-FTZ: setp.neu.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]\r
353 ; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%f[0-9]+]], [[A]];\r
354 ; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%f[0-9]+]], [[B]];\r
355 ; CHECK-NOF16: setp.neu.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]]\r
356 ; CHECK-NEXT: selp.u32 [[R:%r[0-9]+]], 1, 0, [[PRED]];\r
357 ; CHECK-NEXT: st.param.b32 [func_retval0+0], [[R]];\r
358 ; CHECK-NEXT: ret;\r
359 define i1 @test_fcmp_une(half %a, half %b) #0 {\r
360 %r = fcmp une half %a, %b\r
361 ret i1 %r\r
362 }\r
363 \r
364 ; CHECK-LABEL: test_fcmp_ueq(\r
365 ; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fcmp_ueq_param_0];\r
366 ; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fcmp_ueq_param_1];\r
367 ; CHECK-F16-NOFTZ: setp.equ.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]\r
368 ; CHECK-F16-FTZ: setp.equ.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]\r
369 ; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%f[0-9]+]], [[A]];\r
370 ; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%f[0-9]+]], [[B]];\r
371 ; CHECK-NOF16: setp.equ.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]]\r
372 ; CHECK-NEXT: selp.u32 [[R:%r[0-9]+]], 1, 0, [[PRED]];\r
373 ; CHECK-NEXT: st.param.b32 [func_retval0+0], [[R]];\r
374 ; CHECK-NEXT: ret;\r
375 define i1 @test_fcmp_ueq(half %a, half %b) #0 {\r
376 %r = fcmp ueq half %a, %b\r
377 ret i1 %r\r
378 }\r
379 \r
380 ; CHECK-LABEL: test_fcmp_ugt(\r
381 ; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fcmp_ugt_param_0];\r
382 ; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fcmp_ugt_param_1];\r
383 ; CHECK-F16-NOFTZ: setp.gtu.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]\r
384 ; CHECK-F16-FTZ: setp.gtu.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]\r
385 ; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%f[0-9]+]], [[A]];\r
386 ; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%f[0-9]+]], [[B]];\r
387 ; CHECK-NOF16: setp.gtu.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]]\r
388 ; CHECK-NEXT: selp.u32 [[R:%r[0-9]+]], 1, 0, [[PRED]];\r
389 ; CHECK-NEXT: st.param.b32 [func_retval0+0], [[R]];\r
390 ; CHECK-NEXT: ret;\r
391 define i1 @test_fcmp_ugt(half %a, half %b) #0 {\r
392 %r = fcmp ugt half %a, %b\r
393 ret i1 %r\r
394 }\r
395 \r
396 ; CHECK-LABEL: test_fcmp_uge(\r
397 ; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fcmp_uge_param_0];\r
398 ; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fcmp_uge_param_1];\r
399 ; CHECK-F16-NOFTZ: setp.geu.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]\r
400 ; CHECK-F16-FTZ: setp.geu.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]\r
401 ; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%f[0-9]+]], [[A]];\r
402 ; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%f[0-9]+]], [[B]];\r
403 ; CHECK-NOF16: setp.geu.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]]\r
404 ; CHECK-NEXT: selp.u32 [[R:%r[0-9]+]], 1, 0, [[PRED]];\r
405 ; CHECK-NEXT: st.param.b32 [func_retval0+0], [[R]];\r
406 ; CHECK-NEXT: ret;\r
407 define i1 @test_fcmp_uge(half %a, half %b) #0 {\r
408 %r = fcmp uge half %a, %b\r
409 ret i1 %r\r
410 }\r
411 \r
412 ; CHECK-LABEL: test_fcmp_ult(\r
413 ; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fcmp_ult_param_0];\r
414 ; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fcmp_ult_param_1];\r
415 ; CHECK-F16-NOFTZ: setp.ltu.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]\r
416 ; CHECK-F16-FTZ: setp.ltu.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]\r
417 ; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%f[0-9]+]], [[A]];\r
418 ; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%f[0-9]+]], [[B]];\r
419 ; CHECK-NOF16: setp.ltu.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]]\r
420 ; CHECK-NEXT: selp.u32 [[R:%r[0-9]+]], 1, 0, [[PRED]];\r
421 ; CHECK-NEXT: st.param.b32 [func_retval0+0], [[R]];\r
422 ; CHECK-NEXT: ret;\r
423 define i1 @test_fcmp_ult(half %a, half %b) #0 {\r
424 %r = fcmp ult half %a, %b\r
425 ret i1 %r\r
426 }\r
427 \r
428 ; CHECK-LABEL: test_fcmp_ule(\r
429 ; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fcmp_ule_param_0];\r
430 ; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fcmp_ule_param_1];\r
431 ; CHECK-F16-NOFTZ: setp.leu.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]\r
432 ; CHECK-F16-FTZ: setp.leu.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]\r
433 ; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%f[0-9]+]], [[A]];\r
434 ; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%f[0-9]+]], [[B]];\r
435 ; CHECK-NOF16: setp.leu.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]]\r
436 ; CHECK-NEXT: selp.u32 [[R:%r[0-9]+]], 1, 0, [[PRED]];\r
437 ; CHECK-NEXT: st.param.b32 [func_retval0+0], [[R]];\r
438 ; CHECK-NEXT: ret;\r
439 define i1 @test_fcmp_ule(half %a, half %b) #0 {\r
440 %r = fcmp ule half %a, %b\r
441 ret i1 %r\r
442 }\r
443 \r
444 \r
445 ; CHECK-LABEL: test_fcmp_uno(\r
446 ; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fcmp_uno_param_0];\r
447 ; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fcmp_uno_param_1];\r
448 ; CHECK-F16-NOFTZ: setp.nan.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]\r
449 ; CHECK-F16-FTZ: setp.nan.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]\r
450 ; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%f[0-9]+]], [[A]];\r
451 ; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%f[0-9]+]], [[B]];\r
452 ; CHECK-NOF16: setp.nan.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]]\r
453 ; CHECK-NEXT: selp.u32 [[R:%r[0-9]+]], 1, 0, [[PRED]];\r
454 ; CHECK-NEXT: st.param.b32 [func_retval0+0], [[R]];\r
455 ; CHECK-NEXT: ret;\r
456 define i1 @test_fcmp_uno(half %a, half %b) #0 {\r
457 %r = fcmp uno half %a, %b\r
458 ret i1 %r\r
459 }\r
460 \r
461 ; CHECK-LABEL: test_fcmp_one(\r
462 ; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fcmp_one_param_0];\r
463 ; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fcmp_one_param_1];\r
464 ; CHECK-F16-NOFTZ: setp.ne.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]\r
465 ; CHECK-F16-FTZ: setp.ne.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]\r
466 ; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%f[0-9]+]], [[A]];\r
467 ; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%f[0-9]+]], [[B]];\r
468 ; CHECK-NOF16: setp.ne.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]]\r
469 ; CHECK-NEXT: selp.u32 [[R:%r[0-9]+]], 1, 0, [[PRED]];\r
470 ; CHECK-NEXT: st.param.b32 [func_retval0+0], [[R]];\r
471 ; CHECK-NEXT: ret;\r
472 define i1 @test_fcmp_one(half %a, half %b) #0 {\r
473 %r = fcmp one half %a, %b\r
474 ret i1 %r\r
475 }\r
476 \r
477 ; CHECK-LABEL: test_fcmp_oeq(\r
478 ; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fcmp_oeq_param_0];\r
479 ; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fcmp_oeq_param_1];\r
480 ; CHECK-F16-NOFTZ: setp.eq.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]\r
481 ; CHECK-F16-FTZ: setp.eq.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]\r
482 ; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%f[0-9]+]], [[A]];\r
483 ; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%f[0-9]+]], [[B]];\r
484 ; CHECK-NOF16: setp.eq.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]]\r
485 ; CHECK-NEXT: selp.u32 [[R:%r[0-9]+]], 1, 0, [[PRED]];\r
486 ; CHECK-NEXT: st.param.b32 [func_retval0+0], [[R]];\r
487 ; CHECK-NEXT: ret;\r
488 define i1 @test_fcmp_oeq(half %a, half %b) #0 {\r
489 %r = fcmp oeq half %a, %b\r
490 ret i1 %r\r
491 }\r
492 \r
493 ; CHECK-LABEL: test_fcmp_ogt(\r
494 ; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fcmp_ogt_param_0];\r
495 ; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fcmp_ogt_param_1];\r
496 ; CHECK-F16-NOFTZ: setp.gt.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]\r
497 ; CHECK-F16-FTZ: setp.gt.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]\r
498 ; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%f[0-9]+]], [[A]];\r
499 ; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%f[0-9]+]], [[B]];\r
500 ; CHECK-NOF16: setp.gt.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]]\r
501 ; CHECK-NEXT: selp.u32 [[R:%r[0-9]+]], 1, 0, [[PRED]];\r
502 ; CHECK-NEXT: st.param.b32 [func_retval0+0], [[R]];\r
503 ; CHECK-NEXT: ret;\r
504 define i1 @test_fcmp_ogt(half %a, half %b) #0 {\r
505 %r = fcmp ogt half %a, %b\r
506 ret i1 %r\r
507 }\r
508 \r
509 ; CHECK-LABEL: test_fcmp_oge(\r
510 ; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fcmp_oge_param_0];\r
511 ; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fcmp_oge_param_1];\r
512 ; CHECK-F16-NOFTZ: setp.ge.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]\r
513 ; CHECK-F16-FTZ: setp.ge.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]\r
514 ; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%f[0-9]+]], [[A]];\r
515 ; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%f[0-9]+]], [[B]];\r
516 ; CHECK-NOF16: setp.ge.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]]\r
517 ; CHECK-NEXT: selp.u32 [[R:%r[0-9]+]], 1, 0, [[PRED]];\r
518 ; CHECK-NEXT: st.param.b32 [func_retval0+0], [[R]];\r
519 ; CHECK-NEXT: ret;\r
520 define i1 @test_fcmp_oge(half %a, half %b) #0 {\r
521 %r = fcmp oge half %a, %b\r
522 ret i1 %r\r
523 }\r
524 \r
525 ; XCHECK-LABEL: test_fcmp_olt(\r
526 ; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fcmp_olt_param_0];\r
527 ; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fcmp_olt_param_1];\r
528 ; CHECK-F16-NOFTZ: setp.lt.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]\r
529 ; CHECK-F16-FTZ: setp.lt.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]\r
530 ; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%f[0-9]+]], [[A]];\r
531 ; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%f[0-9]+]], [[B]];\r
532 ; CHECK-NOF16: setp.lt.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]]\r
533 ; CHECK-NEXT: selp.u32 [[R:%r[0-9]+]], 1, 0, [[PRED]];\r
534 ; CHECK-NEXT: st.param.b32 [func_retval0+0], [[R]];\r
535 ; CHECK-NEXT: ret;\r
536 define i1 @test_fcmp_olt(half %a, half %b) #0 {\r
537 %r = fcmp olt half %a, %b\r
538 ret i1 %r\r
539 }\r
540 \r
541 ; XCHECK-LABEL: test_fcmp_ole(\r
542 ; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fcmp_ole_param_0];\r
543 ; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fcmp_ole_param_1];\r
544 ; CHECK-F16-NOFTZ: setp.le.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]\r
545 ; CHECK-F16-FTZ: setp.le.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]\r
546 ; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%f[0-9]+]], [[A]];\r
547 ; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%f[0-9]+]], [[B]];\r
548 ; CHECK-NOF16: setp.le.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]]\r
549 ; CHECK-NEXT: selp.u32 [[R:%r[0-9]+]], 1, 0, [[PRED]];\r
550 ; CHECK-NEXT: st.param.b32 [func_retval0+0], [[R]];\r
551 ; CHECK-NEXT: ret;\r
552 define i1 @test_fcmp_ole(half %a, half %b) #0 {\r
553 %r = fcmp ole half %a, %b\r
554 ret i1 %r\r
555 }\r
556 \r
557 ; CHECK-LABEL: test_fcmp_ord(\r
558 ; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fcmp_ord_param_0];\r
559 ; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fcmp_ord_param_1];\r
560 ; CHECK-F16-NOFTZ: setp.num.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]\r
561 ; CHECK-F16-FTZ: setp.num.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]\r
562 ; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%f[0-9]+]], [[A]];\r
563 ; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%f[0-9]+]], [[B]];\r
564 ; CHECK-NOF16: setp.num.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]]\r
565 ; CHECK-NEXT: selp.u32 [[R:%r[0-9]+]], 1, 0, [[PRED]];\r
566 ; CHECK-NEXT: st.param.b32 [func_retval0+0], [[R]];\r
567 ; CHECK-NEXT: ret;\r
568 define i1 @test_fcmp_ord(half %a, half %b) #0 {\r
569 %r = fcmp ord half %a, %b\r
570 ret i1 %r\r
571 }\r
572 \r
573 ; CHECK-LABEL: test_br_cc(\r
574 ; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_br_cc_param_0];\r
575 ; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_br_cc_param_1];\r
576 ; CHECK-DAG: ld.param.u64 %[[C:rd[0-9]+]], [test_br_cc_param_2];\r
577 ; CHECK-DAG: ld.param.u64 %[[D:rd[0-9]+]], [test_br_cc_param_3];\r
578 ; CHECK-F16-NOFTZ: setp.lt.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]\r
579 ; CHECK-F16-FTZ: setp.lt.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]]\r
580 ; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%f[0-9]+]], [[A]];\r
581 ; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%f[0-9]+]], [[B]];\r
582 ; CHECK-NOF16: setp.lt.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]]\r
583 ; CHECK-NEXT: @[[PRED]] bra [[LABEL:LBB.*]];\r
584 ; CHECK: st.u32 [%[[C]]],\r
585 ; CHECK: [[LABEL]]:\r
586 ; CHECK: st.u32 [%[[D]]],\r
587 ; CHECK: ret;\r
588 define void @test_br_cc(half %a, half %b, i32* %p1, i32* %p2) #0 {\r
589 %c = fcmp uge half %a, %b\r
590 br i1 %c, label %then, label %else\r
591 then:\r
592 store i32 0, i32* %p1\r
593 ret void\r
594 else:\r
595 store i32 0, i32* %p2\r
596 ret void\r
597 }\r
598 \r
599 ; CHECK-LABEL: test_phi(\r
600 ; CHECK: ld.param.u64 %[[P1:rd[0-9]+]], [test_phi_param_0];\r
601 ; CHECK: ld.b16 {{%h[0-9]+}}, [%[[P1]]];\r
602 ; CHECK: [[LOOP:LBB[0-9_]+]]:\r
603 ; CHECK: mov.b16 [[R:%h[0-9]+]], [[AB:%h[0-9]+]];\r
604 ; CHECK: ld.b16 [[AB:%h[0-9]+]], [%[[P1]]];\r
605 ; CHECK: {\r
606 ; CHECK: st.param.b64 [param0+0], %[[P1]];\r
607 ; CHECK: call.uni (retval0),\r
608 ; CHECK-NEXT: test_dummy\r
609 ; CHECK: }\r
610 ; CHECK: setp.eq.b32 [[PRED:%p[0-9]+]], %r{{[0-9]+}}, 1;\r
611 ; CHECK: @[[PRED]] bra [[LOOP]];\r
612 ; CHECK: st.param.b16 [func_retval0+0], [[R]];\r
613 ; CHECK: ret;\r
614 define half @test_phi(half* %p1) #0 {\r
615 entry:\r
616 %a = load half, half* %p1\r
617 br label %loop\r
618 loop:\r
619 %r = phi half [%a, %entry], [%b, %loop]\r
620 %b = load half, half* %p1\r
621 %c = call i1 @test_dummy(half* %p1)\r
622 br i1 %c, label %loop, label %return\r
623 return:\r
624 ret half %r\r
625 }\r
626 declare i1 @test_dummy(half* %p1) #0\r
627 \r
628 ; CHECK-LABEL: test_fptosi_i32(\r
629 ; CHECK: ld.param.b16 [[A:%h[0-9]+]], [test_fptosi_i32_param_0];\r
630 ; CHECK: cvt.rzi.s32.f16 [[R:%r[0-9]+]], [[A]];\r
631 ; CHECK: st.param.b32 [func_retval0+0], [[R]];\r
632 ; CHECK: ret;\r
633 define i32 @test_fptosi_i32(half %a) #0 {\r
634 %r = fptosi half %a to i32\r
635 ret i32 %r\r
636 }\r
637 \r
638 ; CHECK-LABEL: test_fptosi_i64(\r
639 ; CHECK: ld.param.b16 [[A:%h[0-9]+]], [test_fptosi_i64_param_0];\r
640 ; CHECK: cvt.rzi.s64.f16 [[R:%rd[0-9]+]], [[A]];\r
641 ; CHECK: st.param.b64 [func_retval0+0], [[R]];\r
642 ; CHECK: ret;\r
643 define i64 @test_fptosi_i64(half %a) #0 {\r
644 %r = fptosi half %a to i64\r
645 ret i64 %r\r
646 }\r
647 \r
648 ; CHECK-LABEL: test_fptoui_i32(\r
649 ; CHECK: ld.param.b16 [[A:%h[0-9]+]], [test_fptoui_i32_param_0];\r
650 ; CHECK: cvt.rzi.u32.f16 [[R:%r[0-9]+]], [[A]];\r
651 ; CHECK: st.param.b32 [func_retval0+0], [[R]];\r
652 ; CHECK: ret;\r
653 define i32 @test_fptoui_i32(half %a) #0 {\r
654 %r = fptoui half %a to i32\r
655 ret i32 %r\r
656 }\r
657 \r
658 ; CHECK-LABEL: test_fptoui_i64(\r
659 ; CHECK: ld.param.b16 [[A:%h[0-9]+]], [test_fptoui_i64_param_0];\r
660 ; CHECK: cvt.rzi.u64.f16 [[R:%rd[0-9]+]], [[A]];\r
661 ; CHECK: st.param.b64 [func_retval0+0], [[R]];\r
662 ; CHECK: ret;\r
663 define i64 @test_fptoui_i64(half %a) #0 {\r
664 %r = fptoui half %a to i64\r
665 ret i64 %r\r
666 }\r
667 \r
668 ; CHECK-LABEL: test_uitofp_i32(\r
669 ; CHECK: ld.param.u32 [[A:%r[0-9]+]], [test_uitofp_i32_param_0];\r
670 ; CHECK: cvt.rn.f16.u32 [[R:%h[0-9]+]], [[A]];\r
671 ; CHECK: st.param.b16 [func_retval0+0], [[R]];\r
672 ; CHECK: ret;\r
673 define half @test_uitofp_i32(i32 %a) #0 {\r
674 %r = uitofp i32 %a to half\r
675 ret half %r\r
676 }\r
677 \r
678 ; CHECK-LABEL: test_uitofp_i64(\r
679 ; CHECK: ld.param.u64 [[A:%rd[0-9]+]], [test_uitofp_i64_param_0];\r
680 ; CHECK: cvt.rn.f16.u64 [[R:%h[0-9]+]], [[A]];\r
681 ; CHECK: st.param.b16 [func_retval0+0], [[R]];\r
682 ; CHECK: ret;\r
683 define half @test_uitofp_i64(i64 %a) #0 {\r
684 %r = uitofp i64 %a to half\r
685 ret half %r\r
686 }\r
687 \r
688 ; CHECK-LABEL: test_sitofp_i32(\r
689 ; CHECK: ld.param.u32 [[A:%r[0-9]+]], [test_sitofp_i32_param_0];\r
690 ; CHECK: cvt.rn.f16.s32 [[R:%h[0-9]+]], [[A]];\r
691 ; CHECK: st.param.b16 [func_retval0+0], [[R]];\r
692 ; CHECK: ret;\r
693 define half @test_sitofp_i32(i32 %a) #0 {\r
694 %r = sitofp i32 %a to half\r
695 ret half %r\r
696 }\r
697 \r
698 ; CHECK-LABEL: test_sitofp_i64(\r
699 ; CHECK: ld.param.u64 [[A:%rd[0-9]+]], [test_sitofp_i64_param_0];\r
700 ; CHECK: cvt.rn.f16.s64 [[R:%h[0-9]+]], [[A]];\r
701 ; CHECK: st.param.b16 [func_retval0+0], [[R]];\r
702 ; CHECK: ret;\r
703 define half @test_sitofp_i64(i64 %a) #0 {\r
704 %r = sitofp i64 %a to half\r
705 ret half %r\r
706 }\r
707 \r
708 ; CHECK-LABEL: test_uitofp_i32_fadd(\r
709 ; CHECK-DAG: ld.param.u32 [[A:%r[0-9]+]], [test_uitofp_i32_fadd_param_0];\r
710 ; CHECK-DAG: cvt.rn.f16.u32 [[C:%h[0-9]+]], [[A]];\r
711 ; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_uitofp_i32_fadd_param_1];\r
712 ; CHECK-F16-NOFTZ: add.rn.f16 [[R:%h[0-9]+]], [[B]], [[C]];\r
713 ; CHECK-F16-FTZ: add.rn.ftz.f16 [[R:%h[0-9]+]], [[B]], [[C]];\r
714 ; CHECK-NOF16-DAG: cvt.f32.f16 [[B32:%f[0-9]+]], [[B]]\r
715 ; CHECK-NOF16-DAG: cvt.f32.f16 [[C32:%f[0-9]+]], [[C]]\r
716 ; CHECK-NOF16-NEXT: add.rn.f32 [[R32:%f[0-9]+]], [[B32]], [[C32]];\r
717 ; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[R32]]\r
718 ; CHECK: st.param.b16 [func_retval0+0], [[R]];\r
719 ; CHECK: ret;\r
720 define half @test_uitofp_i32_fadd(i32 %a, half %b) #0 {\r
721 %c = uitofp i32 %a to half\r
722 %r = fadd half %b, %c\r
723 ret half %r\r
724 }\r
725 \r
726 ; CHECK-LABEL: test_sitofp_i32_fadd(\r
727 ; CHECK-DAG: ld.param.u32 [[A:%r[0-9]+]], [test_sitofp_i32_fadd_param_0];\r
728 ; CHECK-DAG: cvt.rn.f16.s32 [[C:%h[0-9]+]], [[A]];\r
729 ; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_sitofp_i32_fadd_param_1];\r
730 ; CHECK-F16-NOFTZ: add.rn.f16 [[R:%h[0-9]+]], [[B]], [[C]];\r
731 ; CHECK-F16-FTZ: add.rn.ftz.f16 [[R:%h[0-9]+]], [[B]], [[C]];\r
732 ; XCHECK-NOF16-DAG: cvt.f32.f16 [[B32:%f[0-9]+]], [[B]]\r
733 ; XCHECK-NOF16-DAG: cvt.f32.f16 [[C32:%f[0-9]+]], [[C]]\r
734 ; XCHECK-NOF16-NEXT: add.rn.f32 [[R32:%f[0-9]+]], [[B32]], [[C32]];\r
735 ; XCHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[R32]]\r
736 ; CHECK: st.param.b16 [func_retval0+0], [[R]];\r
737 ; CHECK: ret;\r
738 define half @test_sitofp_i32_fadd(i32 %a, half %b) #0 {\r
739 %c = sitofp i32 %a to half\r
740 %r = fadd half %b, %c\r
741 ret half %r\r
742 }\r
743 \r
744 ; CHECK-LABEL: test_fptrunc_float(\r
745 ; CHECK: ld.param.f32 [[A:%f[0-9]+]], [test_fptrunc_float_param_0];\r
746 ; CHECK: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[A]];\r
747 ; CHECK: st.param.b16 [func_retval0+0], [[R]];\r
748 ; CHECK: ret;\r
749 define half @test_fptrunc_float(float %a) #0 {\r
750 %r = fptrunc float %a to half\r
751 ret half %r\r
752 }\r
753 \r
754 ; CHECK-LABEL: test_fptrunc_double(\r
755 ; CHECK: ld.param.f64 [[A:%fd[0-9]+]], [test_fptrunc_double_param_0];\r
756 ; CHECK: cvt.rn.f16.f64 [[R:%h[0-9]+]], [[A]];\r
757 ; CHECK: st.param.b16 [func_retval0+0], [[R]];\r
758 ; CHECK: ret;\r
759 define half @test_fptrunc_double(double %a) #0 {\r
760 %r = fptrunc double %a to half\r
761 ret half %r\r
762 }\r
763 \r
764 ; CHECK-LABEL: test_fpext_float(\r
765 ; CHECK: ld.param.b16 [[A:%h[0-9]+]], [test_fpext_float_param_0];\r
766 ; CHECK-NOFTZ: cvt.f32.f16 [[R:%f[0-9]+]], [[A]];\r
767 ; CHECK-F16-FTZ: cvt.ftz.f32.f16 [[R:%f[0-9]+]], [[A]];\r
768 ; CHECK: st.param.f32 [func_retval0+0], [[R]];\r
769 ; CHECK: ret;\r
770 define float @test_fpext_float(half %a) #0 {\r
771 %r = fpext half %a to float\r
772 ret float %r\r
773 }\r
774 \r
775 ; CHECK-LABEL: test_fpext_double(\r
776 ; CHECK: ld.param.b16 [[A:%h[0-9]+]], [test_fpext_double_param_0];\r
777 ; CHECK: cvt.f64.f16 [[R:%fd[0-9]+]], [[A]];\r
778 ; CHECK: st.param.f64 [func_retval0+0], [[R]];\r
779 ; CHECK: ret;\r
780 define double @test_fpext_double(half %a) #0 {\r
781 %r = fpext half %a to double\r
782 ret double %r\r
783 }\r
784 \r
785 \r
786 ; CHECK-LABEL: test_bitcast_halftoi16(\r
787 ; CHECK: ld.param.b16 [[AH:%h[0-9]+]], [test_bitcast_halftoi16_param_0];\r
788 ; CHECK: mov.b16 [[AS:%rs[0-9]+]], [[AH]]\r
789 ; CHECK: cvt.u32.u16 [[R:%r[0-9]+]], [[AS]]\r
790 ; CHECK: st.param.b32 [func_retval0+0], [[R]];\r
791 ; CHECK: ret;\r
792 define i16 @test_bitcast_halftoi16(half %a) #0 {\r
793 %r = bitcast half %a to i16\r
794 ret i16 %r\r
795 }\r
796 \r
797 ; CHECK-LABEL: test_bitcast_i16tohalf(\r
798 ; CHECK: ld.param.u16 [[AS:%rs[0-9]+]], [test_bitcast_i16tohalf_param_0];\r
799 ; CHECK: mov.b16 [[AH:%h[0-9]+]], [[AS]]\r
800 ; CHECK: st.param.b16 [func_retval0+0], [[AH]];\r
801 ; CHECK: ret;\r
802 define half @test_bitcast_i16tohalf(i16 %a) #0 {\r
803 %r = bitcast i16 %a to half\r
804 ret half %r\r
805 }\r
806 \r
807 \r
808 declare half @llvm.sqrt.f16(half %a) #0\r
809 declare half @llvm.powi.f16(half %a, i32 %b) #0\r
810 declare half @llvm.sin.f16(half %a) #0\r
811 declare half @llvm.cos.f16(half %a) #0\r
812 declare half @llvm.pow.f16(half %a, half %b) #0\r
813 declare half @llvm.exp.f16(half %a) #0\r
814 declare half @llvm.exp2.f16(half %a) #0\r
815 declare half @llvm.log.f16(half %a) #0\r
816 declare half @llvm.log10.f16(half %a) #0\r
817 declare half @llvm.log2.f16(half %a) #0\r
818 declare half @llvm.fma.f16(half %a, half %b, half %c) #0\r
819 declare half @llvm.fabs.f16(half %a) #0\r
820 declare half @llvm.minnum.f16(half %a, half %b) #0\r
821 declare half @llvm.maxnum.f16(half %a, half %b) #0\r
822 declare half @llvm.copysign.f16(half %a, half %b) #0\r
823 declare half @llvm.floor.f16(half %a) #0\r
824 declare half @llvm.ceil.f16(half %a) #0\r
825 declare half @llvm.trunc.f16(half %a) #0\r
826 declare half @llvm.rint.f16(half %a) #0\r
827 declare half @llvm.nearbyint.f16(half %a) #0\r
828 declare half @llvm.round.f16(half %a) #0\r
829 declare half @llvm.fmuladd.f16(half %a, half %b, half %c) #0\r
830 \r
831 ; CHECK-LABEL: test_sqrt(\r
832 ; CHECK: ld.param.b16 [[A:%h[0-9]+]], [test_sqrt_param_0];\r
833 ; CHECK-NOFTZ: cvt.f32.f16 [[AF:%f[0-9]+]], [[A]];\r
834 ; CHECK-NOFTZ: sqrt.rn.f32 [[RF:%f[0-9]+]], [[AF]];\r
835 ; CHECK-F16-FTZ: cvt.ftz.f32.f16 [[AF:%f[0-9]+]], [[A]];\r
836 ; CHECK-F16-FTZ: sqrt.rn.ftz.f32 [[RF:%f[0-9]+]], [[AF]];\r
837 ; CHECK: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[RF]];\r
838 ; CHECK: st.param.b16 [func_retval0+0], [[R]];\r
839 ; CHECK: ret;\r
840 define half @test_sqrt(half %a) #0 {\r
841 %r = call half @llvm.sqrt.f16(half %a)\r
842 ret half %r\r
843 }\r
844 \r
845 ;;; Can't do this yet: requires libcall.\r
846 ; XCHECK-LABEL: test_powi(\r
847 ;define half @test_powi(half %a, i32 %b) #0 {\r
848 ; %r = call half @llvm.powi.f16(half %a, i32 %b)\r
849 ; ret half %r\r
850 ;}\r
851 \r
852 ; CHECK-LABEL: test_sin(\r
853 ; CHECK: ld.param.b16 [[A:%h[0-9]+]], [test_sin_param_0];\r
854 ; CHECK-NOFTZ: cvt.f32.f16 [[AF:%f[0-9]+]], [[A]];\r
855 ; CHECK-F16-FTZ: cvt.ftz.f32.f16 [[AF:%f[0-9]+]], [[A]];\r
856 ; CHECK: sin.approx.f32 [[RF:%f[0-9]+]], [[AF]];\r
857 ; CHECK: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[RF]];\r
858 ; CHECK: st.param.b16 [func_retval0+0], [[R]];\r
859 ; CHECK: ret;\r
860 define half @test_sin(half %a) #0 #1 {\r
861 %r = call half @llvm.sin.f16(half %a)\r
862 ret half %r\r
863 }\r
864 \r
865 ; CHECK-LABEL: test_cos(\r
866 ; CHECK: ld.param.b16 [[A:%h[0-9]+]], [test_cos_param_0];\r
867 ; CHECK-NOFTZ: cvt.f32.f16 [[AF:%f[0-9]+]], [[A]];\r
868 ; CHECK-F16-FTZ: cvt.ftz.f32.f16 [[AF:%f[0-9]+]], [[A]];\r
869 ; CHECK: cos.approx.f32 [[RF:%f[0-9]+]], [[AF]];\r
870 ; CHECK: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[RF]];\r
871 ; CHECK: st.param.b16 [func_retval0+0], [[R]];\r
872 ; CHECK: ret;\r
873 define half @test_cos(half %a) #0 #1 {\r
874 %r = call half @llvm.cos.f16(half %a)\r
875 ret half %r\r
876 }\r
877 \r
878 ;;; Can't do this yet: requires libcall.\r
879 ; XCHECK-LABEL: test_pow(\r
880 ;define half @test_pow(half %a, half %b) #0 {\r
881 ; %r = call half @llvm.pow.f16(half %a, half %b)\r
882 ; ret half %r\r
883 ;}\r
884 \r
885 ;;; Can't do this yet: requires libcall.\r
886 ; XCHECK-LABEL: test_exp(\r
887 ;define half @test_exp(half %a) #0 {\r
888 ; %r = call half @llvm.exp.f16(half %a)\r
889 ; ret half %r\r
890 ;}\r
891 \r
892 ;;; Can't do this yet: requires libcall.\r
893 ; XCHECK-LABEL: test_exp2(\r
894 ;define half @test_exp2(half %a) #0 {\r
895 ; %r = call half @llvm.exp2.f16(half %a)\r
896 ; ret half %r\r
897 ;}\r
898 \r
899 ;;; Can't do this yet: requires libcall.\r
900 ; XCHECK-LABEL: test_log(\r
901 ;define half @test_log(half %a) #0 {\r
902 ; %r = call half @llvm.log.f16(half %a)\r
903 ; ret half %r\r
904 ;}\r
905 \r
906 ;;; Can't do this yet: requires libcall.\r
907 ; XCHECK-LABEL: test_log10(\r
908 ;define half @test_log10(half %a) #0 {\r
909 ; %r = call half @llvm.log10.f16(half %a)\r
910 ; ret half %r\r
911 ;}\r
912 \r
913 ;;; Can't do this yet: requires libcall.\r
914 ; XCHECK-LABEL: test_log2(\r
915 ;define half @test_log2(half %a) #0 {\r
916 ; %r = call half @llvm.log2.f16(half %a)\r
917 ; ret half %r\r
918 ;}\r
919 \r
920 ; CHECK-LABEL: test_fma(\r
921 ; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fma_param_0];\r
922 ; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fma_param_1];\r
923 ; CHECK-DAG: ld.param.b16 [[C:%h[0-9]+]], [test_fma_param_2];\r
924 ; CHECK-F16-NOFTZ: fma.rn.f16 [[R:%h[0-9]+]], [[A]], [[B]], [[C]];\r
925 ; CHECK-F16-FTZ: fma.rn.ftz.f16 [[R:%h[0-9]+]], [[A]], [[B]], [[C]];\r
926 ; CHECK-NOF16-DAG: cvt.f32.f16 [[A32:%f[0-9]+]], [[A]]\r
927 ; CHECK-NOF16-DAG: cvt.f32.f16 [[B32:%f[0-9]+]], [[B]]\r
928 ; CHECK-NOF16-DAG: cvt.f32.f16 [[C32:%f[0-9]+]], [[C]]\r
929 ; CHECK-NOF16-NEXT: fma.rn.f32 [[R32:%f[0-9]+]], [[A32]], [[B32]], [[C32]];\r
930 ; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[R32]]\r
931 ; CHECK: st.param.b16 [func_retval0+0], [[R]];\r
932 ; CHECK: ret\r
933 define half @test_fma(half %a, half %b, half %c) #0 {\r
934 %r = call half @llvm.fma.f16(half %a, half %b, half %c)\r
935 ret half %r\r
936 }\r
937 \r
938 ; CHECK-LABEL: test_fabs(\r
939 ; CHECK: ld.param.b16 [[A:%h[0-9]+]], [test_fabs_param_0];\r
940 ; CHECK-NOFTZ: cvt.f32.f16 [[AF:%f[0-9]+]], [[A]];\r
941 ; CHECK-NOFTZ: abs.f32 [[RF:%f[0-9]+]], [[AF]];\r
942 ; CHECK-F16-FTZ: cvt.ftz.f32.f16 [[AF:%f[0-9]+]], [[A]];\r
943 ; CHECK-F16-FTZ: abs.ftz.f32 [[RF:%f[0-9]+]], [[AF]];\r
944 ; CHECK: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[RF]];\r
945 ; CHECK: st.param.b16 [func_retval0+0], [[R]];\r
946 ; CHECK: ret;\r
947 define half @test_fabs(half %a) #0 {\r
948 %r = call half @llvm.fabs.f16(half %a)\r
949 ret half %r\r
950 }\r
951 \r
952 ; CHECK-LABEL: test_minnum(\r
953 ; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_minnum_param_0];\r
954 ; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_minnum_param_1];\r
955 ; CHECK-NOFTZ-DAG: cvt.f32.f16 [[AF:%f[0-9]+]], [[A]];\r
956 ; CHECK-NOFTZ-DAG: cvt.f32.f16 [[BF:%f[0-9]+]], [[B]];\r
957 ; CHECK-NOFTZ: min.f32 [[RF:%f[0-9]+]], [[AF]], [[BF]];\r
958 ; CHECK-F16-FTZ-DAG: cvt.ftz.f32.f16 [[AF:%f[0-9]+]], [[A]];\r
959 ; CHECK-F16-FTZ-DAG: cvt.ftz.f32.f16 [[BF:%f[0-9]+]], [[B]];\r
960 ; CHECK-F16-FTZ: min.ftz.f32 [[RF:%f[0-9]+]], [[AF]], [[BF]];\r
961 ; CHECK: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[RF]];\r
962 ; CHECK: st.param.b16 [func_retval0+0], [[R]];\r
963 ; CHECK: ret;\r
964 define half @test_minnum(half %a, half %b) #0 {\r
965 %r = call half @llvm.minnum.f16(half %a, half %b)\r
966 ret half %r\r
967 }\r
968 \r
969 ; CHECK-LABEL: test_maxnum(\r
970 ; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_maxnum_param_0];\r
971 ; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_maxnum_param_1];\r
972 ; CHECK-NOFTZ-DAG: cvt.f32.f16 [[AF:%f[0-9]+]], [[A]];\r
973 ; CHECK-NOFTZ-DAG: cvt.f32.f16 [[BF:%f[0-9]+]], [[B]];\r
974 ; CHECK-NOFTZ: max.f32 [[RF:%f[0-9]+]], [[AF]], [[BF]];\r
975 ; CHECK-F16-FTZ-DAG: cvt.ftz.f32.f16 [[AF:%f[0-9]+]], [[A]];\r
976 ; CHECK-F16-FTZ-DAG: cvt.ftz.f32.f16 [[BF:%f[0-9]+]], [[B]];\r
977 ; CHECK-F16-FTZ: max.ftz.f32 [[RF:%f[0-9]+]], [[AF]], [[BF]];\r
978 ; CHECK: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[RF]];\r
979 ; CHECK: st.param.b16 [func_retval0+0], [[R]];\r
980 ; CHECK: ret;\r
981 define half @test_maxnum(half %a, half %b) #0 {\r
982 %r = call half @llvm.maxnum.f16(half %a, half %b)\r
983 ret half %r\r
984 }\r
985 \r
986 ; CHECK-LABEL: test_copysign(\r
987 ; CHECK-DAG: ld.param.b16 [[AH:%h[0-9]+]], [test_copysign_param_0];\r
988 ; CHECK-DAG: ld.param.b16 [[BH:%h[0-9]+]], [test_copysign_param_1];\r
989 ; CHECK-DAG: mov.b16 [[AS:%rs[0-9]+]], [[AH]];\r
990 ; CHECK-DAG: mov.b16 [[BS:%rs[0-9]+]], [[BH]];\r
991 ; CHECK-DAG: and.b16 [[AX:%rs[0-9]+]], [[AS]], 32767;\r
992 ; CHECK-DAG: and.b16 [[BX:%rs[0-9]+]], [[BS]], -32768;\r
993 ; CHECK: or.b16 [[RX:%rs[0-9]+]], [[AX]], [[BX]];\r
994 ; CHECK: mov.b16 [[R:%h[0-9]+]], [[RX]];\r
995 ; CHECK: st.param.b16 [func_retval0+0], [[R]];\r
996 ; CHECK: ret;\r
997 define half @test_copysign(half %a, half %b) #0 {\r
998 %r = call half @llvm.copysign.f16(half %a, half %b)\r
999 ret half %r\r
1000 }\r
1001 \r
1002 ; CHECK-LABEL: test_copysign_f32(\r
1003 ; CHECK-DAG: ld.param.b16 [[AH:%h[0-9]+]], [test_copysign_f32_param_0];\r
1004 ; CHECK-DAG: ld.param.f32 [[BF:%f[0-9]+]], [test_copysign_f32_param_1];\r
1005 ; CHECK-DAG: mov.b16 [[A:%rs[0-9]+]], [[AH]];\r
1006 ; CHECK-DAG: mov.b32 [[B:%r[0-9]+]], [[BF]];\r
1007 ; CHECK-DAG: and.b16 [[AX:%rs[0-9]+]], [[A]], 32767;\r
1008 ; CHECK-DAG: and.b32 [[BX0:%r[0-9]+]], [[B]], -2147483648;\r
1009 ; CHECK-DAG: shr.u32 [[BX1:%r[0-9]+]], [[BX0]], 16;\r
1010 ; CHECK-DAG: cvt.u16.u32 [[BX2:%rs[0-9]+]], [[BX1]];\r
1011 ; CHECK: or.b16 [[RX:%rs[0-9]+]], [[AX]], [[BX2]];\r
1012 ; CHECK: mov.b16 [[R:%h[0-9]+]], [[RX]];\r
1013 ; CHECK: st.param.b16 [func_retval0+0], [[R]];\r
1014 ; CHECK: ret;\r
1015 define half @test_copysign_f32(half %a, float %b) #0 {\r
1016 %tb = fptrunc float %b to half\r
1017 %r = call half @llvm.copysign.f16(half %a, half %tb)\r
1018 ret half %r\r
1019 }\r
1020 \r
1021 ; CHECK-LABEL: test_copysign_f64(\r
1022 ; CHECK-DAG: ld.param.b16 [[AH:%h[0-9]+]], [test_copysign_f64_param_0];\r
1023 ; CHECK-DAG: ld.param.f64 [[BD:%fd[0-9]+]], [test_copysign_f64_param_1];\r
1024 ; CHECK-DAG: mov.b16 [[A:%rs[0-9]+]], [[AH]];\r
1025 ; CHECK-DAG: mov.b64 [[B:%rd[0-9]+]], [[BD]];\r
1026 ; CHECK-DAG: and.b16 [[AX:%rs[0-9]+]], [[A]], 32767;\r
1027 ; CHECK-DAG: and.b64 [[BX0:%rd[0-9]+]], [[B]], -9223372036854775808;\r
1028 ; CHECK-DAG: shr.u64 [[BX1:%rd[0-9]+]], [[BX0]], 48;\r
1029 ; CHECK-DAG: cvt.u16.u64 [[BX2:%rs[0-9]+]], [[BX1]];\r
1030 ; CHECK: or.b16 [[RX:%rs[0-9]+]], [[AX]], [[BX2]];\r
1031 ; CHECK: mov.b16 [[R:%h[0-9]+]], [[RX]];\r
1032 ; CHECK: st.param.b16 [func_retval0+0], [[R]];\r
1033 ; CHECK: ret;\r
1034 define half @test_copysign_f64(half %a, double %b) #0 {\r
1035 %tb = fptrunc double %b to half\r
1036 %r = call half @llvm.copysign.f16(half %a, half %tb)\r
1037 ret half %r\r
1038 }\r
1039 \r
1040 ; CHECK-LABEL: test_copysign_extended(\r
1041 ; CHECK-DAG: ld.param.b16 [[AH:%h[0-9]+]], [test_copysign_extended_param_0];\r
1042 ; CHECK-DAG: ld.param.b16 [[BH:%h[0-9]+]], [test_copysign_extended_param_1];\r
1043 ; CHECK-DAG: mov.b16 [[AS:%rs[0-9]+]], [[AH]];\r
1044 ; CHECK-DAG: mov.b16 [[BS:%rs[0-9]+]], [[BH]];\r
1045 ; CHECK-DAG: and.b16 [[AX:%rs[0-9]+]], [[AS]], 32767;\r
1046 ; CHECK-DAG: and.b16 [[BX:%rs[0-9]+]], [[BS]], -32768;\r
1047 ; CHECK: or.b16 [[RX:%rs[0-9]+]], [[AX]], [[BX]];\r
1048 ; CHECK: mov.b16 [[R:%h[0-9]+]], [[RX]];\r
1049 ; CHECK-NOFTZ: cvt.f32.f16 [[XR:%f[0-9]+]], [[R]];\r
1050 ; CHECK-F16-FTZ: cvt.ftz.f32.f16 [[XR:%f[0-9]+]], [[R]];\r
1051 ; CHECK: st.param.f32 [func_retval0+0], [[XR]];\r
1052 ; CHECK: ret;\r
1053 define float @test_copysign_extended(half %a, half %b) #0 {\r
1054 %r = call half @llvm.copysign.f16(half %a, half %b)\r
1055 %xr = fpext half %r to float\r
1056 ret float %xr\r
1057 }\r
1058 \r
1059 ; CHECK-LABEL: test_floor(\r
1060 ; CHECK: ld.param.b16 [[A:%h[0-9]+]], [test_floor_param_0];\r
1061 ; CHECK: cvt.rmi.f16.f16 [[R:%h[0-9]+]], [[A]];\r
1062 ; CHECK: st.param.b16 [func_retval0+0], [[R]];\r
1063 ; CHECK: ret;\r
1064 define half @test_floor(half %a) #0 {\r
1065 %r = call half @llvm.floor.f16(half %a)\r
1066 ret half %r\r
1067 }\r
1068 \r
1069 ; CHECK-LABEL: test_ceil(\r
1070 ; CHECK: ld.param.b16 [[A:%h[0-9]+]], [test_ceil_param_0];\r
1071 ; CHECK: cvt.rpi.f16.f16 [[R:%h[0-9]+]], [[A]];\r
1072 ; CHECK: st.param.b16 [func_retval0+0], [[R]];\r
1073 ; CHECK: ret;\r
1074 define half @test_ceil(half %a) #0 {\r
1075 %r = call half @llvm.ceil.f16(half %a)\r
1076 ret half %r\r
1077 }\r
1078 \r
1079 ; CHECK-LABEL: test_trunc(\r
1080 ; CHECK: ld.param.b16 [[A:%h[0-9]+]], [test_trunc_param_0];\r
1081 ; CHECK: cvt.rzi.f16.f16 [[R:%h[0-9]+]], [[A]];\r
1082 ; CHECK: st.param.b16 [func_retval0+0], [[R]];\r
1083 ; CHECK: ret;\r
1084 define half @test_trunc(half %a) #0 {\r
1085 %r = call half @llvm.trunc.f16(half %a)\r
1086 ret half %r\r
1087 }\r
1088 \r
1089 ; CHECK-LABEL: test_rint(\r
1090 ; CHECK: ld.param.b16 [[A:%h[0-9]+]], [test_rint_param_0];\r
1091 ; CHECK: cvt.rni.f16.f16 [[R:%h[0-9]+]], [[A]];\r
1092 ; CHECK: st.param.b16 [func_retval0+0], [[R]];\r
1093 ; CHECK: ret;\r
1094 define half @test_rint(half %a) #0 {\r
1095 %r = call half @llvm.rint.f16(half %a)\r
1096 ret half %r\r
1097 }\r
1098 \r
1099 ; CHECK-LABEL: test_nearbyint(\r
1100 ; CHECK: ld.param.b16 [[A:%h[0-9]+]], [test_nearbyint_param_0];\r
1101 ; CHECK: cvt.rni.f16.f16 [[R:%h[0-9]+]], [[A]];\r
1102 ; CHECK: st.param.b16 [func_retval0+0], [[R]];\r
1103 ; CHECK: ret;\r
1104 define half @test_nearbyint(half %a) #0 {\r
1105 %r = call half @llvm.nearbyint.f16(half %a)\r
1106 ret half %r\r
1107 }\r
1108 \r
1109 ; CHECK-LABEL: test_round(\r
1110 ; CHECK: ld.param.b16 {{.*}}, [test_round_param_0];\r
1111 ; check the use of sign mask and 0.5 to implement round\r
1112 ; CHECK: and.b32 [[R:%r[0-9]+]], {{.*}}, -2147483648;\r
1113 ; CHECK: or.b32 {{.*}}, [[R]], 1056964608;\r
1114 ; CHECK: st.param.b16 [func_retval0+0], {{.*}};\r
1115 ; CHECK: ret;\r
1116 define half @test_round(half %a) #0 {\r
1117 %r = call half @llvm.round.f16(half %a)\r
1118 ret half %r\r
1119 }\r
1120 \r
1121 ; CHECK-LABEL: test_fmuladd(\r
1122 ; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fmuladd_param_0];\r
1123 ; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fmuladd_param_1];\r
1124 ; CHECK-DAG: ld.param.b16 [[C:%h[0-9]+]], [test_fmuladd_param_2];\r
1125 ; CHECK-F16-NOFTZ: fma.rn.f16 [[R:%h[0-9]+]], [[A]], [[B]], [[C]];\r
1126 ; CHECK-F16-FTZ: fma.rn.ftz.f16 [[R:%h[0-9]+]], [[A]], [[B]], [[C]];\r
1127 ; CHECK-NOF16-DAG: cvt.f32.f16 [[A32:%f[0-9]+]], [[A]]\r
1128 ; CHECK-NOF16-DAG: cvt.f32.f16 [[B32:%f[0-9]+]], [[B]]\r
1129 ; CHECK-NOF16-DAG: cvt.f32.f16 [[C32:%f[0-9]+]], [[C]]\r
1130 ; CHECK-NOF16-NEXT: fma.rn.f32 [[R32:%f[0-9]+]], [[A32]], [[B32]], [[C32]];\r
1131 ; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[R32]]\r
1132 ; CHECK: st.param.b16 [func_retval0+0], [[R]];\r
1133 ; CHECK: ret;\r
1134 define half @test_fmuladd(half %a, half %b, half %c) #0 {\r
1135 %r = call half @llvm.fmuladd.f16(half %a, half %b, half %c)\r
1136 ret half %r\r
1137 }\r
1138 \r
1139 attributes #0 = { nounwind }\r
1140 attributes #1 = { "unsafe-fp-math" = "true" }\r