[MIParser] Set RegClassOrRegBank during instruction parsing
[llvm-complete.git] / test / CodeGen / PowerPC / bitcast-peephole.mir
blob15238576362b7c2d25ac1637af13127ec9892cec
1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2 # RUN: llc -mtriple=powerpc64le-linux-gnu -run-pass=peephole-opt -verify-machineinstrs -o - %s | FileCheck %s
4 ---
5 name:            bitCast
6 tracksRegLiveness: true
7 body:             |
8   bb.0.entry:
9     ; CHECK-LABEL: name: bitCast
10     ; CHECK: [[XXLEQVOnes:%[0-9]+]]:vsrc = XXLEQVOnes
11     ; CHECK: $v2 = COPY [[XXLEQVOnes]]
12     ; CHECK: BLR8 implicit $lr8, implicit $rm, implicit $v2
13     %0:vsrc = XXLEQVOnes
14     $v2 = COPY %0
15     BLR8 implicit $lr8, implicit $rm, implicit $v2
17 ...
19 # This used to hit an assertion:
20 #   llvm/include/llvm/CodeGen/MachineInstr.h:417: const
21 #   llvm::MachineOperand &llvm::MachineInstr::getOperand(unsigned int)
22 #   const: Assertion `i < getNumOperands() && "getOperand() out of range!"' failed.