1 ; FIXME: FastISel currently returns false if it hits code that uses VSX
2 ; registers and with -fast-isel-abort=1 turned on the test case will then fail.
3 ; When fastisel better supports VSX fix up this test case.
5 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s
6 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx | FileCheck %s
7 ; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=970 -mattr=-vsx | FileCheck %s --check-prefix=PPC970
8 ; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu -mcpu=e500 -mattr=spe | FileCheck %s --check-prefix=SPE
10 ;; Tests for 970 don't use -fast-isel-abort=1 because we intentionally punt
11 ;; to SelectionDAG in some cases.
15 define void @sitofp_single_i64(i64 %a, float %b) nounwind {
17 ; CHECK: sitofp_single_i64
18 ; PPC970: sitofp_single_i64
19 %b.addr = alloca float, align 4
20 %conv = sitofp i64 %a to float
28 store float %conv, float* %b.addr, align 4
32 define void @sitofp_single_i32(i32 %a, float %b) nounwind {
34 ; CHECK: sitofp_single_i32
35 ; PPC970: sitofp_single_i32
36 %b.addr = alloca float, align 4
37 %conv = sitofp i32 %a to float
47 store float %conv, float* %b.addr, align 4
51 define void @sitofp_single_i16(i16 %a, float %b) nounwind {
53 ; CHECK: sitofp_single_i16
54 ; PPC970: sitofp_single_i16
55 %b.addr = alloca float, align 4
56 %conv = sitofp i16 %a to float
68 store float %conv, float* %b.addr, align 4
72 define void @sitofp_single_i8(i8 %a) nounwind {
74 ; CHECK: sitofp_single_i8
75 ; PPC970: sitofp_single_i8
76 %b.addr = alloca float, align 4
77 %conv = sitofp i8 %a to float
89 store float %conv, float* %b.addr, align 4
93 define void @sitofp_double_i32(i32 %a, double %b) nounwind {
95 ; CHECK: sitofp_double_i32
96 ; PPC970: sitofp_double_i32
97 %b.addr = alloca double, align 8
98 %conv = sitofp i32 %a to double
109 store double %conv, double* %b.addr, align 8
113 define void @sitofp_double_i64(i64 %a, double %b) nounwind {
115 ; CHECK: sitofp_double_i64
116 ; PPC970: sitofp_double_i64
117 %b.addr = alloca double, align 8
118 %conv = sitofp i64 %a to double
125 store double %conv, double* %b.addr, align 8
129 define void @sitofp_double_i16(i16 %a, double %b) nounwind {
131 ; CHECK: sitofp_double_i16
132 ; PPC970: sitofp_double_i16
133 %b.addr = alloca double, align 8
134 %conv = sitofp i16 %a to double
145 store double %conv, double* %b.addr, align 8
149 define void @sitofp_double_i8(i8 %a, double %b) nounwind {
151 ; CHECK: sitofp_double_i8
152 ; PPC970: sitofp_double_i8
153 %b.addr = alloca double, align 8
154 %conv = sitofp i8 %a to double
165 store double %conv, double* %b.addr, align 8
171 define void @uitofp_single_i64(i64 %a, float %b) nounwind {
173 ; CHECK: uitofp_single_i64
174 ; PPC970: uitofp_single_i64
175 %b.addr = alloca float, align 4
176 %conv = uitofp i64 %a to float
180 ; PPC970-NOT: fcfidus
181 store float %conv, float* %b.addr, align 4
185 define void @uitofp_single_i32(i32 %a, float %b) nounwind {
187 ; CHECK: uitofp_single_i32
188 ; PPC970: uitofp_single_i32
189 %b.addr = alloca float, align 4
190 %conv = uitofp i32 %a to float
198 ; PPC970-NOT: fcfidus
200 store float %conv, float* %b.addr, align 4
204 define void @uitofp_single_i16(i16 %a, float %b) nounwind {
206 ; CHECK: uitofp_single_i16
207 ; PPC970: uitofp_single_i16
208 %b.addr = alloca float, align 4
209 %conv = uitofp i16 %a to float
210 ; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 48
214 ; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16
219 ; SPE: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16
221 store float %conv, float* %b.addr, align 4
225 define void @uitofp_single_i8(i8 %a) nounwind {
227 ; CHECK: uitofp_single_i8
228 ; PPC970: uitofp_single_i8
229 %b.addr = alloca float, align 4
230 %conv = uitofp i8 %a to float
231 ; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 56
235 ; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24
240 ; SPE: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24
242 store float %conv, float* %b.addr, align 4
246 define void @uitofp_double_i64(i64 %a, double %b) nounwind {
248 ; CHECK: uitofp_double_i64
249 ; PPC970: uitofp_double_i64
250 %b.addr = alloca double, align 8
251 %conv = uitofp i64 %a to double
256 store double %conv, double* %b.addr, align 8
260 define void @uitofp_double_i32(i32 %a, double %b) nounwind {
262 ; CHECK: uitofp_double_i32
263 ; PPC970: uitofp_double_i32
264 %b.addr = alloca double, align 8
265 %conv = uitofp i32 %a to double
274 store double %conv, double* %b.addr, align 8
278 define void @uitofp_double_i16(i16 %a, double %b) nounwind {
280 ; CHECK: uitofp_double_i16
281 ; PPC970: uitofp_double_i16
282 %b.addr = alloca double, align 8
283 %conv = uitofp i16 %a to double
284 ; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 48
288 ; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16
292 ; SPE: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16
294 store double %conv, double* %b.addr, align 8
298 define void @uitofp_double_i8(i8 %a, double %b) nounwind {
300 ; CHECK: uitofp_double_i8
301 ; PPC970: uitofp_double_i8
302 %b.addr = alloca double, align 8
303 %conv = uitofp i8 %a to double
304 ; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 56
308 ; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24
312 ; SPE: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24
314 store double %conv, double* %b.addr, align 8
320 define void @fptosi_float_i32(float %a) nounwind {
322 ; CHECK: fptosi_float_i32
323 ; PPC970: fptosi_float_i32
324 %b.addr = alloca i32, align 4
325 %conv = fptosi float %a to i32
333 store i32 %conv, i32* %b.addr, align 4
337 define void @fptosi_float_i64(float %a) nounwind {
339 ; CHECK: fptosi_float_i64
340 ; PPC970: fptosi_float_i64
341 %b.addr = alloca i64, align 4
342 %conv = fptosi float %a to i64
349 store i64 %conv, i64* %b.addr, align 4
353 define void @fptosi_double_i32(double %a) nounwind {
355 ; CHECK: fptosi_double_i32
356 ; PPC970: fptosi_double_i32
357 %b.addr = alloca i32, align 8
358 %conv = fptosi double %a to i32
366 store i32 %conv, i32* %b.addr, align 8
370 define void @fptosi_double_i64(double %a) nounwind {
372 ; CHECK: fptosi_double_i64
373 ; PPC970: fptosi_double_i64
374 %b.addr = alloca i64, align 8
375 %conv = fptosi double %a to i64
382 store i64 %conv, i64* %b.addr, align 8
388 define void @fptoui_float_i32(float %a) nounwind {
390 ; CHECK: fptoui_float_i32
391 ; PPC970: fptoui_float_i32
392 %b.addr = alloca i32, align 4
393 %conv = fptoui float %a to i32
401 store i32 %conv, i32* %b.addr, align 4
405 define void @fptoui_float_i64(float %a) nounwind {
407 ; CHECK: fptoui_float_i64
408 ; PPC970: fptoui_float_i64
409 %b.addr = alloca i64, align 4
410 %conv = fptoui float %a to i64
414 ; PPC970-NOT: fctiduz
415 store i64 %conv, i64* %b.addr, align 4
419 define void @fptoui_double_i32(double %a) nounwind {
421 ; CHECK: fptoui_double_i32
422 ; PPC970: fptoui_double_i32
423 %b.addr = alloca i32, align 8
424 %conv = fptoui double %a to i32
432 store i32 %conv, i32* %b.addr, align 8
436 define void @fptoui_double_i64(double %a) nounwind {
438 ; CHECK: fptoui_double_i64
439 ; PPC970: fptoui_double_i64
440 %b.addr = alloca i64, align 8
441 %conv = fptoui double %a to i64
445 ; PPC970-NOT: fctiduz
446 store i64 %conv, i64* %b.addr, align 8