1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=powerpc64le-- | FileCheck %s
4 declare i8 @llvm.fshl.i8(i8, i8, i8)
5 declare i16 @llvm.fshl.i16(i16, i16, i16)
6 declare i32 @llvm.fshl.i32(i32, i32, i32)
7 declare i64 @llvm.fshl.i64(i64, i64, i64)
8 declare <4 x i32> @llvm.fshl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
10 declare i8 @llvm.fshr.i8(i8, i8, i8)
11 declare i16 @llvm.fshr.i16(i16, i16, i16)
12 declare i32 @llvm.fshr.i32(i32, i32, i32)
13 declare i64 @llvm.fshr.i64(i64, i64, i64)
14 declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
16 ; When first 2 operands match, it's a rotate.
18 define i8 @rotl_i8_const_shift(i8 %x) {
19 ; CHECK-LABEL: rotl_i8_const_shift:
21 ; CHECK-NEXT: rlwinm 4, 3, 27, 0, 31
22 ; CHECK-NEXT: rlwimi 4, 3, 3, 0, 28
25 %f = call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 3)
29 define i64 @rotl_i64_const_shift(i64 %x) {
30 ; CHECK-LABEL: rotl_i64_const_shift:
32 ; CHECK-NEXT: rotldi 3, 3, 3
34 %f = call i64 @llvm.fshl.i64(i64 %x, i64 %x, i64 3)
38 ; When first 2 operands match, it's a rotate (by variable amount).
40 define i16 @rotl_i16(i16 %x, i16 %z) {
41 ; CHECK-LABEL: rotl_i16:
43 ; CHECK-NEXT: neg 5, 4
44 ; CHECK-NEXT: clrlwi 6, 3, 16
45 ; CHECK-NEXT: rlwinm 4, 4, 0, 28, 31
46 ; CHECK-NEXT: clrlwi 5, 5, 28
47 ; CHECK-NEXT: slw 3, 3, 4
48 ; CHECK-NEXT: srw 4, 6, 5
49 ; CHECK-NEXT: or 3, 3, 4
51 %f = call i16 @llvm.fshl.i16(i16 %x, i16 %x, i16 %z)
55 define i32 @rotl_i32(i32 %x, i32 %z) {
56 ; CHECK-LABEL: rotl_i32:
58 ; CHECK-NEXT: rlwnm 3, 3, 4, 0, 31
60 %f = call i32 @llvm.fshl.i32(i32 %x, i32 %x, i32 %z)
64 define i64 @rotl_i64(i64 %x, i64 %z) {
65 ; CHECK-LABEL: rotl_i64:
67 ; CHECK-NEXT: rldcl 3, 3, 4, 0
69 %f = call i64 @llvm.fshl.i64(i64 %x, i64 %x, i64 %z)
75 define <4 x i32> @rotl_v4i32(<4 x i32> %x, <4 x i32> %z) {
76 ; CHECK-LABEL: rotl_v4i32:
78 ; CHECK-NEXT: xxlxor 36, 36, 36
79 ; CHECK-NEXT: vslw 5, 2, 3
80 ; CHECK-NEXT: vsubuwm 3, 4, 3
81 ; CHECK-NEXT: vsrw 2, 2, 3
82 ; CHECK-NEXT: xxlor 34, 37, 34
84 %f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> %z)
88 ; Vector rotate by constant splat amount.
90 define <4 x i32> @rotl_v4i32_const_shift(<4 x i32> %x) {
91 ; CHECK-LABEL: rotl_v4i32_const_shift:
93 ; CHECK-NEXT: vspltisw 3, -16
94 ; CHECK-NEXT: vspltisw 4, 13
95 ; CHECK-NEXT: vspltisw 5, 3
96 ; CHECK-NEXT: vsubuwm 3, 4, 3
97 ; CHECK-NEXT: vslw 4, 2, 5
98 ; CHECK-NEXT: vsrw 2, 2, 3
99 ; CHECK-NEXT: xxlor 34, 36, 34
101 %f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 3, i32 3, i32 3, i32 3>)
105 ; Repeat everything for funnel shift right.
107 define i8 @rotr_i8_const_shift(i8 %x) {
108 ; CHECK-LABEL: rotr_i8_const_shift:
110 ; CHECK-NEXT: rlwinm 4, 3, 29, 0, 31
111 ; CHECK-NEXT: rlwimi 4, 3, 5, 0, 26
112 ; CHECK-NEXT: mr 3, 4
114 %f = call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 3)
118 define i32 @rotr_i32_const_shift(i32 %x) {
119 ; CHECK-LABEL: rotr_i32_const_shift:
121 ; CHECK-NEXT: rlwinm 3, 3, 29, 0, 31
123 %f = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 3)
127 ; When first 2 operands match, it's a rotate (by variable amount).
129 define i16 @rotr_i16(i16 %x, i16 %z) {
130 ; CHECK-LABEL: rotr_i16:
132 ; CHECK-NEXT: neg 5, 4
133 ; CHECK-NEXT: clrlwi 6, 3, 16
134 ; CHECK-NEXT: rlwinm 4, 4, 0, 28, 31
135 ; CHECK-NEXT: clrlwi 5, 5, 28
136 ; CHECK-NEXT: srw 4, 6, 4
137 ; CHECK-NEXT: slw 3, 3, 5
138 ; CHECK-NEXT: or 3, 3, 4
140 %f = call i16 @llvm.fshr.i16(i16 %x, i16 %x, i16 %z)
144 define i32 @rotr_i32(i32 %x, i32 %z) {
145 ; CHECK-LABEL: rotr_i32:
147 ; CHECK-NEXT: neg 4, 4
148 ; CHECK-NEXT: rlwnm 3, 3, 4, 0, 31
150 %f = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 %z)
154 define i64 @rotr_i64(i64 %x, i64 %z) {
155 ; CHECK-LABEL: rotr_i64:
157 ; CHECK-NEXT: neg 4, 4
158 ; CHECK-NEXT: rldcl 3, 3, 4, 0
160 %f = call i64 @llvm.fshr.i64(i64 %x, i64 %x, i64 %z)
166 define <4 x i32> @rotr_v4i32(<4 x i32> %x, <4 x i32> %z) {
167 ; CHECK-LABEL: rotr_v4i32:
169 ; CHECK-NEXT: xxlxor 36, 36, 36
170 ; CHECK-NEXT: vsrw 5, 2, 3
171 ; CHECK-NEXT: vsubuwm 3, 4, 3
172 ; CHECK-NEXT: vslw 2, 2, 3
173 ; CHECK-NEXT: xxlor 34, 34, 37
175 %f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> %z)
179 ; Vector rotate by constant splat amount.
181 define <4 x i32> @rotr_v4i32_const_shift(<4 x i32> %x) {
182 ; CHECK-LABEL: rotr_v4i32_const_shift:
184 ; CHECK-NEXT: vspltisw 3, -16
185 ; CHECK-NEXT: vspltisw 4, 13
186 ; CHECK-NEXT: vspltisw 5, 3
187 ; CHECK-NEXT: vsubuwm 3, 4, 3
188 ; CHECK-NEXT: vsrw 4, 2, 5
189 ; CHECK-NEXT: vslw 2, 2, 3
190 ; CHECK-NEXT: xxlor 34, 34, 36
192 %f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 3, i32 3, i32 3, i32 3>)
196 define i32 @rotl_i32_shift_by_bitwidth(i32 %x) {
197 ; CHECK-LABEL: rotl_i32_shift_by_bitwidth:
200 %f = call i32 @llvm.fshl.i32(i32 %x, i32 %x, i32 32)
204 define i32 @rotr_i32_shift_by_bitwidth(i32 %x) {
205 ; CHECK-LABEL: rotr_i32_shift_by_bitwidth:
208 %f = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 32)
212 define <4 x i32> @rotl_v4i32_shift_by_bitwidth(<4 x i32> %x) {
213 ; CHECK-LABEL: rotl_v4i32_shift_by_bitwidth:
216 %f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 32, i32 32, i32 32, i32 32>)
220 define <4 x i32> @rotr_v4i32_shift_by_bitwidth(<4 x i32> %x) {
221 ; CHECK-LABEL: rotr_v4i32_shift_by_bitwidth:
224 %f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 32, i32 32, i32 32, i32 32>)